CN102709293A - Novel low-voltage high-performance nonvolatile memory based on separate nano graphene floating gate - Google Patents
Novel low-voltage high-performance nonvolatile memory based on separate nano graphene floating gate Download PDFInfo
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- CN102709293A CN102709293A CN201210184172XA CN201210184172A CN102709293A CN 102709293 A CN102709293 A CN 102709293A CN 201210184172X A CN201210184172X A CN 201210184172XA CN 201210184172 A CN201210184172 A CN 201210184172A CN 102709293 A CN102709293 A CN 102709293A
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Abstract
The invention discloses a novel low-voltage high-performance nonvolatile memory based on a separate nano graphene floating gate. The novel low-voltage high-performance nonvolatile memory comprises a substrate, a tunneling layer, a storage layer, a barrier layer and a gate electrode, wherein the storage layer is of separate nano graphene, and by utilizing the density and size modulating action of the nano graphene and the energy band modulating action of the tunneling layer, the charge distribution and holding characteristic of the storage layer can be optimized. By introducing the separate nano graphene floating gate, a nonvolatile flash memory with low energy consumption under low-voltage operation can be realized; and by effectively controlling the density and size of the nano graphene and modulating the energy band structure of the tunneling oxidizing layer, the charge distribution and holding characteristic of the storage layer can be optimized, and the high-performance operation of devices can be realized.
Description
Technical field
The present invention relates to floating gate type nonvolatile memory spare, relate in particular to a kind of novel high performance discrete nano-graphene floating gate type nonvolatile memory of low pressure that has, belong to nano material manufacturing and memory technology field.
Background technology
The electronic information epoch; Nonvolatile memory has a wide range of applications and irreplaceable status in the fields such as electronics of computer, multimedia application, mobile network communication, consumer electronics product and national defence as one of most important IC products.Especially the flash memory of advantages such as fast, the high density of its main product-have program speed, low-power consumption, small size and high reliability has occupied most markets of nonvolatile memory.
Yet, As market improve constantly the continuous development with technology, the microelectric technique node is constantly pushed ahead; Data capacity increases sharp; Storage density improves further, and then has proposed more requirement to nonvolatile memory, like small size piece more; Bigger capacity, better speed, lower power consumption, higher reliability etc.But, along with further the reducing of device feature size (below 45 nanometers), run into very large challenge as traditional floating polysilicon gate device of non-volatile burst flash memory mainstream technology, cause program voltage to be difficult to reduce like traditional floating boom; The tunnel oxide layer thickness can't reduce with the device size equal proportion, and own warp is to a limit; Simultaneously cell size dwindle difficult problems such as having increased random fluctuation and technology fluctuation, can't satisfy the requirement of ultrahigh density storage, or the like.
But on device contractility problem, receive serious restriction in order to solve traditional FGS floating gate structure, arise at the historic moment based on the flash memory of discrete nanocrystalline floating gate structure.Nanocrystalline floating gate structure is compared with traditional FGS floating gate structure, exists following advantage: 1) the nanocrystalline effect that receives coulomb blockade effect and quantum limitation effect makes device can realize retention performance good under the thin-oxide; 2) nanocrystalline discrete FGS floating gate structure can adopt thinner tunnel oxide under the prerequisite of not sacrificing device reliability, improve erasable speed; Only the little charge in nanocrystalline is operated when 3) device is worked, can realize the purpose of low-power consumption storage; 4) local defect in the tunnel oxide is less to all charge affects of discrete distribution in nanocrystalline, and device has more excellent tolerance; 5) owing to the coupling that does not have between drain electrode and floating boom, thereby reduce the punchthrough effect that drain electrode causes, made and when device is read, to use big drain voltage and little channel length, and then reduced the area of device, reduced cost.Because these above-mentioned unique good characteristics, well-known semiconductor company in many worlds and R&D institution have all dropped into great amount of manpower, financial resources and have been engaged in the research and development of nanocrystal FGS floating gate structure memory, and have obtained certain achievement.
At present, research is maximum nanocrystallinely mainly comprises: semiconductor nano, metallic nano crystal, oxide nanocrystalline, metallorganic are nanocrystalline etc.But, the floating-gate memory of above-mentioned these nanocrystalline materials also is faced with many problems in the scaled down process, and charge storage descends when causing reduced scale like the quantum limitation effect of semiconductor nano; Metallic nano crystal costs an arm and a leg, a lot of technology of preparing can't with the CMOS process compatible, can't realize being prone to the homogeneous and controllable of size diffusion during high annealing or chemical reaction takes place, can't realize during reduced scale that highdensity device is integrated; The nanocrystalline chemical stability of metallorganic is relatively poor, can't high annealing, and retention performance is poor; Oxide nanocrystalline can't reduce power consumption, charge storage a little less than, or the like.Therefore, new material, new construction and new technology are the important development directions of present integrated circuit technique, also are to solve the core scheme that the development of nano-crystal floating gate type memory technology encounters problems.
Summary of the invention
Given this, main purpose of the present invention is to provide a kind of integrated novel low pressure high-performance nonvolatile memory based on discrete nano-graphene floating boom of the microminiaturized high-density storage of nanoscale that can be used for.
In order to achieve the above object; A kind of novel low pressure high-performance nonvolatile memory based on discrete nano-graphene floating boom provided by the invention comprises: substrate, tunnel layer, accumulation layer, barrier layer and gate electrode; Said accumulation layer is discrete nano-graphene; Utilize the density and the size modulating action of nano-graphene, and tunnel layer can be with modulating action, but CHARGE DISTRIBUTION in the optimal Storage layer and retention performance.
Preferably, said area is to be made up of silicon chip, germanium silicon chip or other similar semi-conducting material.
Preferably, said tunnel layer and barrier layer adopt broad stopband width dielectric material to process.
Preferably, said accumulation layer by the nano-graphene of separation with have the electric charge capture dielectric material and stack gradually the layer structure that forms more than 2 layers or 2 layers.
Preferably, said electric charge capture dielectric material is selected from Si
3N
4, Al
2O
3, HfO
2Or HfAlO, the thickness of said electric charge capture dielectric material is in the 0.5-5 nanometer.
Key of the present invention is the floating boom accumulation layer that discrete nano-graphene constitutes; Electric charge mainly is present in nano-graphene and nano-graphene and dielectric layer at the interface, can characterize the charge storage (being superior to unidimensional metal or semiconductor nano with the density magnitude) of nano-graphene floating boom through scanning Kelvin probe microscopy.The preparation of nano-graphene realizes in the surperficial catalyst-free direct growth of amorphous/polycrystalline/single crystalline substrate (like metal, semiconductor, insulator etc.) through the plasma reinforced chemical vapour deposition technology.Growth mechanism be exactly utilize carbon containing gas (like methane CH
4) be excited into plasma state, under lower temperature (about 525 ℃), it is auxiliary to need not catalyst, and the active group of carbon containing is in the direct deposition and form according to two-dimensional growth (the Frank-van dar Merwe) pattern of nucleation-grow up of substrate surface.The size of nano-graphene and density can be passed through growth conditions (temperature, time etc.) homogeneous and controllable, thereby can come the CHARGE DISTRIBUTION in the control store layer through effectively controlling the density and the size of nano-graphene.
In addition, through the bulk graphene film with methods such as chemical vapour deposition (CVD), extension, chemical synthesis, redox preparations carry out the various different cycles that patterning obtains, the graphene nano structure of different size also can be used for substituting the nano-graphene floating boom.
In this structure, substrate is to be made up of silicon chip, germanium silicon chip or other similar semi-conducting materials.The broad stopband dielectric material is adopted on tunnel layer and barrier layer, like SiO
2, Al
2O
3, HfO
2, or other has the material of similarity.Each thickness of thin layer can be adjusted according to the difference of material therefor.Through the band structure of modulation tunnel layer dielectric material, but the charge-retention property of optimised devices, the high performance operation of realization device.
That this structure constitutes is simple, preparation method and required technology and traditional cmos process compatibility.Tunnel layer, accumulation layer, barrier layer can adopt deposition technique to form successively, carry out the technologies such as graphical definition of area of grid afterwards again.The preparation method that said manufacture method relates to thin film deposition or nano-graphene technology comprises thermal oxidation; Plasma reinforced chemical vapour deposition technology, atom layer deposition process, thermal evaporation technology, pulse laser deposition process, electron beam evaporation process etc., and relate to gate figure structure processing technology and comprise like conventional methods such as photoetching, etching, flattening surface, annealing.Because the nano-graphene floating boom has high chemical stability, thereby so device can improve the crystal mass on tunnel layer and barrier layer by high annealing.
The method of operation of this structure is identical with legacy memory, can adopt modes such as FN tunnelling, channel hot electron injection (CHE) programming to realize programming operation.Can adopt that the FN grid are wiped, the band-to-band-tunneling hot hole injects modes such as (BBTH) and realizes erase operation.Reading of information can be accomplished through read forward or back read operation.
Can find out from technique scheme; The present invention has following beneficial effect: the present invention is through introducing nano-graphene discrete floating boom; Realized the low energy consumption non-volatile burst flash memory under low voltage operated, through the density and the size of effective control nano-graphene, and the band structure of modulation tunnel oxide; But CHARGE DISTRIBUTION in the optimal Storage layer and retention performance, the high performance operation of realization device.Simultaneously, this programme is through introducing nano-graphene/electric charge capture dielectric layer stacked structure, the stored charge distribution of optimised devices and capacity greatly.Because nano-graphene has low dimension characteristic (thickness < 1nm) and high charge storage, it is integrated to can be used for the microminiaturized high-density memory device of nanometer.Among the present invention material and device preparing process all with the CMOS process compatible on traditional silicon plane, and the preparation cost of nano-graphene is cheap, is beneficial to industry and promotes.
Description of drawings
Fig. 1 is the cellular construction sketch map of nano-graphene floating gate type nonvolatile memory of the present invention;
Fig. 2 is the surface topography map of nano-graphene floating boom;
Fig. 3 a is the cellular construction sketch map of nano-graphene floating gate type nonvolatile memory in the instantiation of the present invention, and Fig. 3 b is the band structure sketch map of the memory of Fig. 3 a;
Fig. 4 is the stability test of nano-graphene floating boom in the instantiation of the present invention before and after high annealing figure as a result;
Fig. 5 contrasts the operating voltage and the memory window test result comparison diagram of structure for nano-graphene floating gate type nonvolatile memory structure in the instantiation of the present invention and legacy memory;
Fig. 6 is for passing through the modulation of nano-graphene density and size is optimized the charge storage capacity of nano-graphene floating gate type nonvolatile memory structure in the instantiation of the present invention;
Fig. 7 is for passing through the modulation of tunnel layer material is optimized the data retention characteristics of nano-graphene floating gate type nonvolatile memory structure in the instantiation of the present invention;
Fig. 8 distributes and uniformity test figure for the surface potential of the high density nanometer scale memory cell array of nano-graphene floating gate type nonvolatile memory structure in the instantiation of the present invention.
Embodiment
For making the object of the invention, technical scheme and advantage clearer, combine specific embodiment once, and, the present invention is done further detailed description with reference to accompanying drawing.
Fig. 1 is the cellular construction sketch map of nano-graphene floating gate type nonvolatile memory of the present invention.Structure of the present invention comprises substrate, tunnel layer, accumulation layer, barrier layer and gate electrode.Broad stopband dielectric material such as SiO can be adopted in tunnel layer and barrier layer
2, Al
2O
3, HfO
2, or other has the material of similarity.Each thickness of thin layer can be adjusted according to the difference of employing material.Accumulation layer then adopts the nano-graphene floating boom to constitute, play main memory action be nano-graphene and nano-graphene and dielectric layer at the interface.The surface topography map of nano-graphene is as shown in Figure 2, and height is the thickness of single-layer graphene about the 0.4-0.7 nanometer, and the size adjustable scope of nano-graphene is big-several nanometers ~ hundreds of nanometer, and the adjustable density scope is 0 ~ 10
11Cm
2
Certainly, as accumulation layer of the present invention, can adopt the structure of nano-graphene/electric charge capture dielectric material multiple-level stack.This structure is charge storage capacity and the CHARGE DISTRIBUTION in the optimal Storage layer further, and its key is to introduce dielectric material such as the Si with high defect concentration
3N
4, Al
2O
3, HfO
2HfAlO, or other has the material of similarity, with nano-graphene constitute jointly the multiple-level stack structure (nano-graphene/dielectric material/... / nano-graphene/dielectric material); The thin layer of dielectric material thickness that inserts is about the 0.5-5 nanometer, and position and number can according to circumstances be adjusted.This is a big advantage of nano-graphene floating boom, can directly not have the catalysis controllable growth on the substrate arbitrarily, thus the combination property that can utilize different tunneling medium layer of compatible technology direct regulation and control and electric charge capture layer to come optimised devices.
Prepared the nano-graphene floating gate type nonvolatile memory shown in Fig. 3 a in the specific embodiment of the invention, substrate is p type Si, and tunnel layer is SiO
2, form by thermal oxidation method.Accumulation layer is a nano-graphene, and by the preparation of plasma-reinforced chemical sedimentation, height is the thickness of single-layer graphene about the 0.4-0.7 nanometer, and size is about the 6-8 nanometer, and density is greater than 1X10
11Cm
2There is Al on the barrier layer
2O
3Constitute, thickness is 15 nanometers, is formed by atom layer deposition process.Electrode material is Al, and the electron beam evaporation deposition preparation is arranged.The band structure figure of this device correspondence is shown in Fig. 3 b.In order to contrast the performance of nano-graphene floating gate type nonvolatile memory, in specific embodiment, also prepared the device of contrasting of traditional individual layer accumulation layer capacitance structure, material preparation process is all identical.
Fig. 4 is the raman scattering spectrum of nano-graphene floating boom before and after device high temperature (1000 ° of C) annealing in process in the specific embodiment of the invention, by its typical characteristic peak G (1592cm
-1) can know that nano-graphene has fabulous heat-resisting quantity and chemical stability, does not spread the annealing back, does not have and medium oxide layer generation chemical reaction yet.
Fig. 5 be in the specific embodiment of the invention nano-graphene floating gate type nonvolatile memory structure and legacy memory according to the operating voltage and the memory window test result comparison diagram of structure.Because nano-graphene has the high density of states and metal edge attitude, discrete nano-graphene floating-gate memory just obtained under the scanning voltage of ± 8V ~ memory window of 4.5V, corresponding contrasts the effect that structure then almost can't see storage.Therefore, discrete nano-graphene floating gate type nonvolatile memory has been realized the big memory window under low voltage operated.
Fig. 6 is through the modulation of nano-graphene density and size being optimized the charge storage capacity of nano-graphene floating gate type nonvolatile memory structure in the specific embodiment of the invention.Can know size more little (6 ~ 8 nanometer), the high more (> of saturated density by Fig. 6; 1X10
11Cm
2) the storage capacity of nano-graphene floating boom the strongest.This be because; Nano-graphene is a semimetal character; Its Bohr radius is that 0.74 nanometer is (with the same magnitude of metal; Bohr radius like Au is 0.5 nanometer), the quantum size restriction effect that therefore has a strong impact on semiconductor nano (Bohr radius of Si is 11 nanometers) storage characteristics is also not obvious for the influence of the nano-graphene below 10 nanometers.Add that nano-graphene has metallic zigzag marginality; Its size is more little; The effect of marginality is obvious more; Even therefore the size of nano-graphene still has fabulous charge storage (depositing ~ 20 electronics like the single nano-graphene average energy that is of a size of 6 nanometers) below 10 nanometers, be superior to unidimensional metallic nano crystal.It is integrated that these characteristics of nano-graphene can be used for the microminiaturized high-density storage of nanometer.
Fig. 7 is through the modulation of tunnel layer band structure being optimized the data retention characteristics of nano-graphene floating gate type nonvolatile memory structure in the specific embodiment of the invention.The general requirement of nonvolatile storage has the hold facility more than 10 years, and this just means the electric charge necessary < 50% of its loss.The intrinsic mechanism of loss of charge mechanism mainly comprises thermionic emission (Schottky emission), Frenkel-Poole emission, FN tunnelling, direct Tunneling etc.Since the work function of nano-graphene very big (~ 4.8eV); So the potential barrier between nano-graphene and the tunnelling medium silica is big (shown in Fig. 3 b); General in addition in data maintenance process the electric field in the tunneling medium layer very a little less than; Be difficult to reach the FN tunnelling, therefore the leakage mechanism in electric charge maintenance process mainly is direct Tunneling.Can know that by Fig. 7 the silica that utilizes shown in Fig. 3 a is loss 44% in 10 years as its retention performance of nano-graphene floating-gate memory of tunnel layer.If utilize high k material such as HfO
2Be used as tunneling medium layer, then the charge-retention property of device can be greatly improved (10 years loss 28%).This is because the energy barrier height at the nano-graphene of high work function and high k material interface place increases on the one hand, has reduced the probability of direct Tunneling; High on the other hand k material has bigger dielectric constant, thereby has further reduced the electric field of tunneling medium layer in the electric charge maintenance process, has improved the retention performance of device.
Fig. 8 characterizes the nanometer scale storage characteristics of nano-graphene floating boom for utilizing scanning Kelvin probe microscope in the instantiation of the present invention.The a point is a programmed state among the figure, and the b point is an erase state, is depicted as the storage array of a 10X10, injecting voltage is+and 2V (electronics)/-2V (hole), each memory cell is the 500X500 nanometer
2, spacing is 500 nanometers, can find out that the nano-graphene floating boom in this specific embodiment has the discreteness and the uniformity of extremely strong charge storage and height, the high-density storage that can be used for nanometer scale fully is integrated.
By on can know, in an embodiment of the present invention,, realized that a kind of novel low energy consumption high-performance is thermally-stabilised and can be used for the microminiaturized integrated nano-graphene floating boom flash memory of high density nanometer through introducing the nano-graphene floating boom of discrete.Density, size and the design multiple-level stack structure of this scheme through effectively controlling nano-graphene can be optimized CHARGE DISTRIBUTION and memory capacity.Simultaneously,, can improve data retention characteristics, realize the high reliability operation of device through regulating the band structure of tunneling medium layer.The material preparation of the present invention-discrete nano-graphene floating-gate memory and device manufacturing process and conventional silicon planar CMOS process compatible, with low cost, be beneficial to wide industrial and use.
Above-described specific embodiment; The object of the invention, technical scheme and beneficial effect have been carried out further explain, and institute it should be understood that the above is merely specific embodiment of the present invention; Be not limited to the present invention; All within spirit of the present invention and principle, any modification of being made, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (5)
1. novel low pressure high-performance nonvolatile memory based on discrete nano-graphene floating boom; Comprise substrate, tunnel layer, accumulation layer, barrier layer and gate electrode; It is characterized in that said accumulation layer is discrete nano-graphene, utilize the density and the size modulating action of nano-graphene; And tunnel layer can be with modulating action, but CHARGE DISTRIBUTION in the optimal Storage layer and retention performance.
2. memory according to claim 1 is characterized in that, said area is to be made up of silicon chip, germanium silicon chip or other similar semi-conducting material.
3. memory according to claim 1 is characterized in that, said tunnel layer and barrier layer adopt broad stopband width dielectric material to process.
4. memory according to claim 1 is characterized in that, said accumulation layer by the nano-graphene of separation with have the electric charge capture dielectric material and stack gradually the layer structure that forms more than 2 layers or 2 layers.
5. memory according to claim 4 is characterized in that, said electric charge capture dielectric material is selected from Si
3N
4, Al
2O
3, HfO
2Or HfAlO, the thickness of said electric charge capture dielectric material is in the 0.5-5 nanometer.
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| CN107680973A (en) * | 2017-09-01 | 2018-02-09 | 河北大学 | A kind of big memory window trapped-charge memory based on graphene oxide quantum dot and preparation method thereof |
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| CN113165867A (en) * | 2018-11-13 | 2021-07-23 | 哈利法科技大学 | Single nanoparticle-based non-volatile memory systems for compact and high data storage electronics |
| CN110211963A (en) * | 2019-06-11 | 2019-09-06 | 南京邮电大学 | A kind of metal-oxide-semiconductor memory and preparation method |
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| CN112436010B (en) * | 2020-11-17 | 2022-09-13 | 北京理工大学 | Flexible memory based on two-dimensional material |
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