CN102709292A - SONOS (silicon oxide nitride oxide silicon) device with plurality of grades of storage layers and medium layers and forming method thereof - Google Patents
SONOS (silicon oxide nitride oxide silicon) device with plurality of grades of storage layers and medium layers and forming method thereof Download PDFInfo
- Publication number
- CN102709292A CN102709292A CN2012101617194A CN201210161719A CN102709292A CN 102709292 A CN102709292 A CN 102709292A CN 2012101617194 A CN2012101617194 A CN 2012101617194A CN 201210161719 A CN201210161719 A CN 201210161719A CN 102709292 A CN102709292 A CN 102709292A
- Authority
- CN
- China
- Prior art keywords
- layer
- dielectric layer
- accumulation
- laminated construction
- semiconductor substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Landscapes
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
The invention provides an SONOS (Silicon Oxide Nitride Oxide Silicon) device with a plurality of grades of storage layers and medium layers and a forming method of the SONOS device. The SONOS device with a plurality of the grades of the storage layers and the medium layers comprises a semiconductor substrate, a storage structure located on the surface of the semiconductor substrate, a grid electrode layer arranged on the surface of the storage structure, a source electrode and a drain electrode in the semiconductor substrate at two sides of the grid electrode layer, wherein the storage structure comprises a tunneling medium layer, an overlapping structure located on the surface of the tunneling medium layer and a top medium layer located on the surface of the overlapping structure; and the overlapping structure at least comprises two storage layers and a medium layer located between the two storage layers. The SONOS device with a plurality of the grades of the storage layers and the medium layers disclosed by the embodiment of the invention has a strong storage capability.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, relate in particular to a kind of SONOS device and forming method thereof with multistage accumulation layer and dielectric layer.
Background technology
Usually; The semiconductor memory that is used to store data is divided into volatile memory and nonvolatile memory; The data of volatile memory are lost when power interruptions easily, even and nonvolatile memory when power interruptions, its data still can be held.Compare with other nonvolatile storage technologies (for example disc driver), nonvolatile semiconductor memory is less relatively, and therefore, nonvolatile semiconductor memory is widely used in GSM, storage card etc.
Non-volatile memory cells can be realized by FGS floating gate structure or SONOS (silicon-oxide-nitride-oxide-silicon is called for short SONOS) structure two big major techniques.Wherein, Floating gate type memory has thicker tunnel oxide relatively, and good charge holding performance is provided, and the technological process ratio is easier to control; But in case there is defective in the tunnel oxide that forms, stored charge is lost from the polysilicon accumulation layer along defective easily.And the thinner thickness of the tunnel oxide of SONOS memory; Utilize the silicon nitride medium layer of insulation to capture and stored charge; The trap that silicon nitride is used for catching electric charge is independently; Can not cause losing in a large number of electric charge because of a defective, and SONOS also has anti-erasable ability is good, operating voltage is low and power is low, technical process is simple and with the advantages such as CMOS process compatible of standard.
Please refer to Fig. 1, the SONOS structure of prior art comprises: Semiconductor substrate 100; Be positioned at the tunneling medium layer 101 on said Semiconductor substrate 100 surfaces; What be positioned at said tunneling medium layer 101 surfaces catches charge layer 103; Be positioned at said top medium layer 105 of catching charge layer 103 surfaces; Wherein, The material of tunneling medium layer 101 is a silica; The material of catching charge layer 103 is a silicon nitride, and the material of top medium layer 105 is a silica, said tunneling medium layer 101, catches the laminated construction that charge layer 103 and top medium layer 105 have constituted ONO (oxide-nitride-oxide); Be positioned at the gate electrode layer 107 on said top medium layer 105 surface; Be positioned at the source electrode 109 and drain electrode 111 of the Semiconductor substrate 100 of said laminated construction both sides.
Yet the charge layer of catching of prior art is caught the limited in one's ability of electric charge, and the storage capacity of memory remains further to be promoted.More related contents about the SONOS device please refer to the Chinese patent of publication number for " CN102290444A ".
Summary of the invention
The problem that the present invention solves provide a kind of storage capacity strong have SONOS device of multistage accumulation layer and dielectric layer and forming method thereof.
For addressing the above problem, embodiments of the invention provide a kind of SONOS device with multistage accumulation layer and dielectric layer, comprising:
Semiconductor substrate;
Be positioned at the storage organization of said semiconductor substrate surface; Said storage organization comprises tunneling medium layer, is positioned at the laminated construction on said tunneling medium layer surface and the top medium layer that is positioned at said laminated construction surface; Wherein, said laminated construction comprises at least two accumulation layers and the dielectric layer between said two accumulation layers;
Be positioned at the gate electrode layer on said storage organization surface;
Be positioned at the source electrode and the drain electrode of the Semiconductor substrate of said gate electrode layer both sides.
Alternatively, the material of said accumulation layer is silicon nitride, polysilicon or germanium.
Alternatively, the thickness of said accumulation layer is
Alternatively, the material of said dielectric layer is silica, aluminium oxide or hafnium oxide.
Alternatively, the thickness of said dielectric layer is
Alternatively, the thickness of said dielectric layer is
Accordingly, the inventor also provides and has formed above-mentioned any and have the formation method of the SONOS device of multistage accumulation layer and dielectric layer, comprising:
Semiconductor substrate is provided;
Formation is positioned at the storage organization of said semiconductor substrate surface; The formation step of said storage organization comprises: form tunneling medium layer, form the laminated construction that is positioned at said tunneling medium layer surface and form the top medium layer that is positioned at said laminated construction surface; Wherein, said laminated construction comprises at least two accumulation layers and the dielectric layer between said two accumulation layers;
Formation is positioned at the gate electrode layer on said storage organization surface;
Formation is positioned at the source electrode and the drain electrode of the Semiconductor substrate of said gate electrode layer both sides.
Alternatively, the formation technology of said laminated construction is chemical vapor deposition method or molecular beam epitaxial process.
Alternatively, also comprise: after forming laminated construction, said laminated construction is heat-treated.
Alternatively, said heat treatment is: in the atmosphere of nitrogen or nitrous oxide, anneal.
Compared with prior art, embodiments of the invention have the following advantages:
Formed storage organization at semiconductor substrate surface; The formation step of said storage organization comprises: form laminated construction; Accumulation layer and dielectric layer alternated in the said laminated construction; Help to form the strong SONOS device of storage capacity, and it is simple to form technology with multistage accumulation layer and dielectric layer.
Said SONOS device with multistage accumulation layer and dielectric layer; Comprise laminated construction in its storage organization; Accumulation layer and dielectric layer in the said laminated construction pile up alternately, when said SONOS device with multistage accumulation layer and dielectric layer is worked, form the SQW that separates in the laminated construction; The ability of its trapped electrons is strengthened, and storage capacity improves.
Further; The thickness of said dielectric layer strengthens less than the coupling between the accumulation layer adjacent in
laminated construction; Originally the SQW that separates can be extended to little band; Help further to strengthen the ability of its trapped electrons, storage capacity is better.
Description of drawings
Fig. 1 is the cross-sectional view of nonvolatile memory of the SONOS structure of prior art;
Fig. 2 is the schematic flow sheet of formation method of the SONOS device of multistage accumulation layer of having of the embodiment of the invention and dielectric layer;
Fig. 3-Fig. 6 is the cross-sectional view of forming process of the SONOS device of multistage accumulation layer of having of the embodiment of the invention and dielectric layer;
Fig. 7 is for being with distribution map to the SONOS device with multistage accumulation layer and dielectric layer shown in Figure 6 when not applying voltage.
Embodiment
Said as background technology, the storage capacity of the nonvolatile memory of prior art is limited.
Please continue with reference to figure 1; Through analyzing, the inventor finds, prior art between said gate electrode layer 107 and Semiconductor substrate 100, apply positive voltage (be generally+10V); When source electrode 109 applies identical low-voltage (being generally 0V) with drain electrode on 111; Electronics in the raceway groove sends tunnelling and passes tunneling medium layer 101, is stored in and catches in the charge layer 103, accomplishes the electron tunneling programming operation; Between gate electrode layer 107 and Semiconductor substrate 100, apply negative voltage (be generally-10V); When source electrode 109 applies identical low-voltage (being generally 0V) with drain electrode on 111, can accomplish and catch the electron tunneling of catching in the charge layer 103 and pass tunneling medium layer 101 and get into the erase operation of Semiconductor substrate 100.To catch the ability of electric charge relevant with catching charge layer 103 for the storage capacity of nonvolatile memory; Promptly relevant with the number of catching charge layer 103 interior holes; Prior art to catch charge layer 103 holes numbers limited, cause the storage capacity of nonvolatile memory limited.
Through further research; The inventor finds that if will saidly catch the laminated construction that charge layer 103 (shown in Figure 1) is adjusted into accumulation layer and dielectric layer alternated, the electronics in the raceway groove needs only and caught by the accumulation layer in the laminated construction; Just accomplished electron tunneling programming operation (stored information); A plurality of accumulation layers have more hole, so the enhancing of the ability of trapped electrons, and the storage capacity of nonvolatile memory is improved.
Further; The inventor finds; After the thickness of accumulation layer in the laminated construction was less than certain value (electron mean free path), said laminated construction promptly can form the SQW of a plurality of separation, helps to provide more hole; Catch more electronics, to improve the storage capacity of nonvolatile memory.
Further, the inventor finds, when the thickness of dielectric layer in the laminated construction gradually during attenuation; Coupling between the adjacent accumulation layer strengthens; The energy level that originally in each SQW, separates will be extended to little band (can be with), because free electron has more state in little band, the hole number of generation is before more; The ability of trapped electrons further strengthens, and the storage capacity of the nonvolatile memory of formation is better.
For making those skilled in the art better understand the present invention, the present invention is elaborated below in conjunction with accompanying drawing and specific embodiment.
Please refer to Fig. 2, the formation method of the SONOS device with multistage accumulation layer and dielectric layer of the embodiment of the invention comprises:
Step S201 provides Semiconductor substrate;
Step S203; Formation is positioned at the storage organization of said semiconductor substrate surface; The formation step of said storage organization comprises: form tunneling medium layer, form the laminated construction that is positioned at said tunneling medium layer surface and form the top medium layer that is positioned at said laminated construction surface; Wherein, said laminated construction comprises at least two accumulation layers and the dielectric layer between said two accumulation layers;
Step S205 forms the gate electrode layer that is positioned at said storage organization surface;
Step S207 forms the source electrode and the drain electrode of the Semiconductor substrate that is positioned at said gate electrode layer both sides.
Concrete, please refer to Fig. 3-Fig. 6, Fig. 3-Fig. 6 shows the cross-sectional view of forming process of the SONOS device of multistage accumulation layer of having of the embodiment of the invention and dielectric layer.
Please refer to Fig. 3, Semiconductor substrate 300 is provided.
Said Semiconductor substrate 300 is used to subsequent technique provides workbench.Said Semiconductor substrate 300 is a body silicon, and its material is monocrystalline silicon, monocrystalline germanium, single-crystal silicon Germanium III-V compounds of group (for example gallium arsenic, indium phosphide and gallium nitride etc.) or monocrystalline silicon carbide, and perhaps said Semiconductor substrate 300 is silicon-on-insulator (SOI).In an embodiment of the present invention, said Semiconductor substrate 300 is a body silicon, and its material is a monocrystalline silicon.
Please refer to Fig. 4, form the tunnelling dielectric film 301 that is positioned at said Semiconductor substrate 300 surfaces, form the laminate film 309 that is positioned at said tunnelling dielectric film 301 surfaces, form the top medium film 311 that is positioned at said laminate film 309 surfaces; Form the gate electrode layer film 313 that covers said top medium film 311 surfaces.
Said tunnelling dielectric film 301 is used for follow-up formation tunneling medium layer, and isolated lamination structure and Semiconductor substrate 300.The material of said tunnelling dielectric film 301 is silica, aluminium oxide or hafnium oxide etc.The formation technology of said tunnelling dielectric film 301 is chemical vapor deposition method or molecular beam epitaxial process.In an embodiment of the present invention, the material of said tunnelling dielectric film 301 is a silica, and it forms technology is chemical vapor deposition method.
The storage capacity of considering nonvolatile memory is relevant with the number of the accumulation layer holes of follow-up formation; The inventor will catch the laminated construction that charge layer 103 (shown in Figure 1) is adjusted into accumulation layer and dielectric layer alternated; A plurality of accumulation layers have more hole; Electronics in the raceway groove is as long as caught by the arbitrary accumulation layer in the laminated construction; Just accomplished electron tunneling programming operation (stored information), said ability with laminated construction trapped electrons of a plurality of accumulation layers and dielectric layer strengthens, and the storage capacity of nonvolatile memory is improved.
Said laminate film 309 comprises first memory films 303, second memory films 307 and first dielectric film 305 between said first memory films 303, second memory films 307 at least; Be used for follow-up formation laminated construction; Wherein, Said first memory films 303, second memory films 307 are respectively applied for and form first accumulation layer, second accumulation layer, and the material of said first memory films 303, second memory films 307 is silicon nitride, polysilicon or germanium etc.; Said first dielectric film 305 is used to form dielectric layer, and the material of said first dielectric film 305 is silica, aluminium oxide or hafnium oxide etc.The formation technology of said first memory films 303, second memory films 307 and said first dielectric film 305 is chemical vapor deposition method or molecular beam epitaxial process.
In an embodiment of the present invention, the material of said first memory films 303, second memory films 307 is a silicon nitride, and the material of said first dielectric film 305 is a silica; The formation technology of said first memory films 303, second memory films 307 and said first dielectric film 305 is chemical vapor deposition method.
Further; The inventor finds; After the thickness of accumulation layer in the laminated construction of follow-up formation was less than certain value (electron mean free path), said laminated construction promptly can form the SQW of a plurality of separation, helps to provide more hole; Catch more electronics, to improve the storage capacity of nonvolatile memory.Therefore; The inventor with the thickness of said first memory films 303, second memory films 307 be provided with less; Make that for
thickness of first accumulation layer, second accumulation layer of follow-up formation is little, to improve the storage capacity of nonvolatile memory.In an embodiment of the present invention; The thickness of said first memory films 303, second memory films 307 is for having formed the SQW of a plurality of separation in
laminated construction, the storage capacity of nonvolatile memory is strong.
Further, the inventor also finds, when the thickness of dielectric layer in the laminated construction of follow-up formation gradually during attenuation; Coupling between the adjacent accumulation layer strengthens; The energy level that originally in each SQW, separates will be extended to little band (can be with), because free electron has more state in little band, the hole number of generation is before more; The ability of trapped electrons further strengthens, and the storage capacity of the nonvolatile memory of formation is better.
Therefore; The thickness that the inventor also is used to form first dielectric film of first dielectric layer in the follow-up formation laminated construction is set to
to obtain first dielectric layer of thickness for
; Make the energy level that originally in each SQW, separates be extended to little band, further promote the storage capacity of nonvolatile memory.Because the formation technology of said first dielectric film 305 is chemical vapor deposition method; When the thickness of first dielectric film 305 that forms was
, the quality of said first dielectric film 305 was better.In an embodiment of the present invention, the thickness of said first dielectric film 305 is beneficial to the strong nonvolatile memory of follow-up formation storage capacity for
.
Said top medium film 311 is used for follow-up formation top medium layer, with isolated lamination structure and gate electrode layer.The material of said top medium film 311 is silica, aluminium oxide or hafnium oxide etc., and it forms technology is chemical vapor deposition method or molecular beam epitaxial process.In an embodiment of the present invention, the material of said top medium film 311 is a silica, and the formation technology of said top medium film 311 is chemical vapor deposition method.
Said gate electrode film 313 is used for follow-up formation gate electrode layer.The material of said gate electrode film 313 is polysilicon, W, Cu, Ag, TiN, TaN or TiAl etc.The formation technology of said gate electrode film 313 is chemical vapor deposition method or molecular beam epitaxial process.In an embodiment of the present invention, the material of said gate electrode film 313 is tungsten (W), and the formation technology of said gate electrode film 313 is chemical vapor deposition method.Be well known to those skilled in the art owing to form the technology of gate electrode film 313, repeat no more at this.
Need to prove, in an embodiment of the present invention, also comprise: form the mask layer (not shown) be positioned at said gate electrode film 313 surfaces, said mask layer has defined the position and the size of gate electrode layer, laminated construction, is beneficial to the carrying out of subsequent technique.
Please refer to Fig. 5, is mask with said mask layer, and the said top medium film of etching, laminate film and tunnelling dielectric film form the storage organization (not indicating) that is positioned at said Semiconductor substrate 300 surfaces successively.
The formation technology of said storage organization is etching technics, for example anisotropic dry etch process.The formation step of said storage organization comprises: form tunneling medium layer 301a, form the laminated construction 309a that is positioned at said tunneling medium layer surface and form the top medium layer 311a that is positioned at said laminated construction 309a surface; Wherein, said laminated construction 309a comprises at least the first accumulation layer 303a, the second accumulation layer 307a and the first dielectric layer 305a between the said first accumulation layer 303a, the second accumulation layer 307a.
Said tunneling medium layer 301a is used for the first accumulation layer 303a of isolation of semiconductor substrate 300 and laminated construction; Said tunneling medium layer 301a obtains after by tunnelling dielectric film etching; The material of said tunneling medium layer 301a is identical with the material of tunnelling dielectric film, is silica, aluminium oxide or hafnium oxide etc.
The said first accumulation layer 303a, the second accumulation layer 307a are used for trapped electrons, accomplish the electron tunneling programming operation.The said first accumulation layer 303a, the second accumulation layer 307a are respectively by forming after said first memory films, the second memory films etching; The material of the said first accumulation layer 303a is identical with the material of said first memory films; The material of the said second accumulation layer 307a is identical with the material of said second memory films, is silicon nitride, polysilicon or germanium etc.The thickness of the said first accumulation layer 303a, the said second accumulation layer 307a is identical with said first memory films, second memory films respectively, is
The said first dielectric layer 305a is used to isolate the first accumulation layer 303a and the second accumulation layer 307a.The said first dielectric layer 305a obtains after by the dielectric film etching, and therefore, the material of the said first dielectric layer 305a is identical with the material of said dielectric film, is silica, aluminium oxide or hafnium oxide etc.The thickness of the said first dielectric layer 305a is identical with the thickness of said first dielectric film; Good for
for the quality of the first dielectric layer 305a that makes formation; Usually the thickness of the first dielectric layer 305a that forms be
in an embodiment of the present invention, the thickness of the said first dielectric layer 305a is
Said top medium layer 311a is used for the isolate gate electrode layer 313a and the second accumulation layer 307a.The material of said top medium layer 311a is identical with the material of said top medium film, is silica, aluminium oxide or hafnium oxide etc.
Said gate electrode layer 313a is used to form gate electrode.The material of said gate electrode layer 313a is identical with the material of said gate electrode film, is polysilicon, W, Cu, Ag, TiN, TaN or TiAl etc.
In an embodiment of the present invention; The material of said tunneling medium layer 301a, the first dielectric layer 305a, top medium layer 311a is a silica; The material of the said first accumulation layer 303a, the second accumulation layer 307a is a silicon nitride, and the material of said gate electrode layer 313a is tungsten (W); The thickness of the said first accumulation layer 303a, the second accumulation layer 307a is that the thickness of
said first dielectric layer 305a is thinner owing to the first dielectric layer 305a for
; Coupling between the first accumulation layer 303a, the second accumulation layer 307a strengthens; Feasible script is formed on the SQW in the first accumulation layer 303a, the second accumulation layer 307a; Be expanded into little band; Free electron has more state in said little band; The hole number that produces is before more; The ability of trapped electrons further strengthens, and the storage capacity of the nonvolatile memory of formation is better.
Need to prove; In other embodiments of the invention; Can also form the 3rd accumulation layer and second dielectric layer between said second accumulation layer and the 3rd accumulation layer; Even form the 4th accumulation layer, and the 3rd dielectric layer between said the 3rd accumulation layer and the 4th accumulation layer etc., specifically decide according to actual conditions.
Need to prove that be the better quality of the laminated construction 309a that makes formation, the memory property of the SONOS device of follow-up formation is better.In the embodiments of the invention, also comprise: after forming laminated construction, said laminated construction 309a is heat-treated.Wherein, said heat treatment is for to anneal in the atmosphere of nitrogen or nitrous oxide.
Need to prove, please refer to Fig. 6, in an embodiment of the present invention, also comprise: the source electrode 315 and drain electrode 317 that form the Semiconductor substrate 300 that is positioned at said gate electrode layer 313a both sides.
Said source electrode 315 forms through the back of in the Semiconductor substrate 300 of said gate electrode layer 313a both sides, mixing with drain electrode 317.The technology that forms source electrode 315 and drain electrode 317 owing to mix is well known to those skilled in the art, repeats no more at this.
After above-mentioned steps is accomplished, the completing of the SONOS device with multistage accumulation layer and dielectric layer of the embodiment of the invention.Formation technology in the embodiment of the invention is simple; Adopt chemical vapor deposition method or molecular beam epitaxial process to form, and because the thinner thickness of accumulation layer in the laminated construction that forms, the thickness of dielectric layer is also thinner; Coupling in the laminated construction in each accumulation layer strengthens; Formed little band, more be prone to catch free electron, thereby the storage capacity of the SONOS device of multistage accumulation layer of having of formation and dielectric layer is strengthened.
Accordingly, please continue with reference to figure 6, the inventor also provides a kind of SONOS device with multistage accumulation layer and dielectric layer, comprising:
Be positioned at the storage organization (not indicating) on said Semiconductor substrate 300 surfaces; Said storage organization comprises tunneling medium layer 301a, is positioned at the laminated construction 309a on said tunneling medium layer 301a surface and the top medium layer 311a that is positioned at said laminated construction 309a surface; Wherein, said laminated construction 309a comprises at least two accumulation layers (the first accumulation layer 303a and the second accumulation layer 307a) and the dielectric layer (the first dielectric layer 305a) between said two accumulation layers;
Be positioned at the gate electrode layer 313a on said storage organization surface;
Be positioned at the source electrode 315 and drain electrode 317 of the Semiconductor substrate 300 of said gate electrode layer 313a both sides.
Wherein, Said Semiconductor substrate 300 is a body silicon; Its material is monocrystalline silicon, monocrystalline germanium, single-crystal silicon Germanium III-V compounds of group (for example gallium arsenic, indium phosphide and gallium nitride etc.) or monocrystalline silicon carbide, and perhaps said Semiconductor substrate 300 is silicon-on-insulator (SOI).In the embodiments of the invention, said Semiconductor substrate 300 is a body silicon, and its material is a monocrystalline silicon.
Said tunneling medium layer 301a is used for the first accumulation layer 303a of isolation of semiconductor substrate 300 and laminated construction, and the material of said tunneling medium layer 301a is silica, aluminium oxide or hafnium oxide etc.In an embodiment of the present invention, the material of said tunneling medium layer 301a is a silica.
The said first accumulation layer 303a, the second accumulation layer 307a are used for trapped electrons, accomplish the electron tunneling programming operation.The material of the said first accumulation layer 303a, the second accumulation layer 307a is silicon nitride, polysilicon or germanium etc.; Thickness is
in an embodiment of the present invention; The material of the said first accumulation layer 303a, the second accumulation layer 307a is a silicon nitride, and its thickness is
The said first dielectric layer 305a is used to isolate the first accumulation layer 303a and the second accumulation layer 307a.The material of the said first dielectric layer 305a is silica, aluminium oxide or hafnium oxide etc., and thickness is
and when the quality of the first dielectric layer 305a of thickness when
good.In an embodiment of the present invention; The material of the said first dielectric layer 305a is a silica, and its thickness is
Please refer to Fig. 7, Fig. 7 is for being with distribution map to the SONOS device with multistage accumulation layer and dielectric layer shown in Figure 6 when not applying voltage.
Wherein, be followed successively by the energy band diagram of Semiconductor substrate 300, tunneling medium layer 301a, the first accumulation layer 303a, the first dielectric layer 305a, the second accumulation layer 307a, top medium layer 311a, gate electrode layer 313a from right to left.When the high pressure write operation; Electronics is at first crossed the potential barrier of tunneling medium layer 301a, gets into the memory location of the first accumulation layer 303a, because the potential barrier of the first dielectric layer 305a is thinner; Portions of electronics can continue to cross the first dielectric layer 305a, gets into the memory location of the second accumulation layer 307a.Under the situation that electric charge keeps, owing to there is not applied voltage, the pressure drop on the potential barrier is less, and the first dielectric layer 305a is difficult for being crossed by electronics, and like this compared with traditional structure, the more difficult leakage of electronics can improve the data confining force of device.
Because the thinner thickness of the said first accumulation layer 303a, the second accumulation layer 307a, meeting forms the SQW of a plurality of separation among the laminated construction 309a, helps to provide more hole, catches more electronics, to improve the storage capacity of nonvolatile memory.In an embodiment of the present invention; The thickness of the said first dielectric layer 305a is also thinner; The first accumulation layer 303a, the coupling between the second accumulation layer 307a that lay respectively at said first dielectric layer 305a lower surface and upper surface strengthen; The energy level that originally separates in each SQW will be extended to little band, and the ability of trapped electrons further strengthens, and the storage capacity of the nonvolatile memory of formation (the SONOS device with multistage accumulation layer and dielectric layer) is better.
Please continue with reference to figure 6, said top medium layer 311a is used for the isolate gate electrode layer 313a and the second accumulation layer 307a.The material of said top medium layer 311a is silica, aluminium oxide or hafnium oxide etc.In an embodiment of the present invention, the material of said top medium layer 311a is a silica.
Said gate electrode layer 313a is used to form gate electrode.The material of said gate electrode layer 313a is polysilicon, W, Cu, Ag, TiN, TaN or TiAl etc.In an embodiment of the present invention, the material W of said gate electrode layer 313a.
Need to prove; In other embodiments of the invention; Said SONOS device with multistage accumulation layer and dielectric layer can also comprise: at said the 3rd accumulation layer and second dielectric layer between said second accumulation layer and the 3rd accumulation layer; Even can also comprise the 4th accumulation layer, and the 3rd dielectric layer between said the 3rd accumulation layer and the 4th accumulation layer etc., specifically decide according to actual conditions.
The SONOS device with multistage accumulation layer and dielectric layer of the embodiment of the invention; Comprise laminated construction in its storage organization; Accumulation layer and dielectric layer in the said laminated construction pile up alternately, when said SONOS device with multistage accumulation layer and dielectric layer is worked, form the SQW that separates in the laminated construction; The ability of its trapped electrons is strengthened, and storage capacity improves.And the dielectric layer of the embodiment of the invention is thinner, and the coupling in the laminated construction between first accumulation layer and second accumulation layer strengthens, and the SQW that separates originally can be extended to little band, helps further to strengthen the ability of its trapped electrons, and storage capacity is better.
To sum up; Formed storage organization at semiconductor substrate surface; The formation step of said storage organization comprises: form laminated construction; Accumulation layer and dielectric layer alternated in the said laminated construction help to form the strong SONOS device with multistage accumulation layer and dielectric layer of storage capacity, and it is simple to form technology.
Said SONOS device with multistage accumulation layer and dielectric layer; Comprise laminated construction in its storage organization; Accumulation layer and dielectric layer in the said laminated construction pile up alternately, when said SONOS device with multistage accumulation layer and dielectric layer is worked, form the SQW that separates in the laminated construction; The ability of its trapped electrons is strengthened, and storage capacity improves.
Further; The thickness of said dielectric layer strengthens less than the coupling between the accumulation layer adjacent in
laminated construction; Originally the SQW that separates can be extended to little band; Help further to strengthen the ability of its trapped electrons, storage capacity is better.
Though the present invention with preferred embodiment openly as above; But it is not to be used for limiting the present invention; Any those skilled in the art are not breaking away from the spirit and scope of the present invention; Can utilize the method and the technology contents of above-mentioned announcement that technical scheme of the present invention is made possible change and modification, therefore, every content that does not break away from technical scheme of the present invention; To any simple modification, equivalent variations and modification that above embodiment did, all belong to the protection range of technical scheme of the present invention according to technical spirit of the present invention.
Claims (10)
1. SONOS device with multistage accumulation layer and dielectric layer comprises:
Semiconductor substrate;
It is characterized in that, also comprise:
Be positioned at the storage organization of said semiconductor substrate surface; Said storage organization comprises tunneling medium layer, is positioned at the laminated construction on said tunneling medium layer surface and the top medium layer that is positioned at said laminated construction surface; Wherein, said laminated construction comprises at least two accumulation layers and the dielectric layer between said two accumulation layers;
Be positioned at the gate electrode layer on said storage organization surface;
Be positioned at the source electrode and the drain electrode of the Semiconductor substrate of said gate electrode layer both sides.
2. the SONOS device with multistage accumulation layer and dielectric layer as claimed in claim 1 is characterized in that the material of said accumulation layer is silicon nitride, polysilicon or germanium.
3. the SONOS device with multistage accumulation layer and dielectric layer as claimed in claim 1; It is characterized in that the thickness of said accumulation layer is
4. the SONOS device with multistage accumulation layer and dielectric layer as claimed in claim 1 is characterized in that the material of said dielectric layer is silica, aluminium oxide or hafnium oxide.
5. like claim 1 or 3 described SONOS devices with multistage accumulation layer and dielectric layer; It is characterized in that the thickness of said dielectric layer is
6. like claim 1 or 3 described SONOS devices with multistage accumulation layer and dielectric layer; It is characterized in that the thickness of said dielectric layer is
7. one kind like each described formation method with SONOS device of multistage accumulation layer and dielectric layer of claim 1-6, it is characterized in that, comprising:
Semiconductor substrate is provided;
Formation is positioned at the storage organization of said semiconductor substrate surface; The formation step of said storage organization comprises: form tunneling medium layer, form the laminated construction that is positioned at said tunneling medium layer surface and form the top medium layer that is positioned at said laminated construction surface; Wherein, said laminated construction comprises at least two accumulation layers and the dielectric layer between said two accumulation layers;
Formation is positioned at the gate electrode layer on said storage organization surface;
Formation is positioned at the source electrode and the drain electrode of the Semiconductor substrate of said gate electrode layer both sides.
8. the formation method with SONOS device of multistage accumulation layer and dielectric layer as claimed in claim 7,
It is characterized in that the formation technology of said laminated construction is chemical vapor deposition method or molecular beam epitaxial process.
9. the formation method with SONOS device of multistage accumulation layer and dielectric layer as claimed in claim 7 is characterized in that, also comprises: after forming laminated construction, said laminated construction is heat-treated.
10. the formation method with SONOS device of multistage accumulation layer and dielectric layer as claimed in claim 9 is characterized in that said heat treatment is: in the atmosphere of nitrogen or nitrous oxide, anneal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012101617194A CN102709292A (en) | 2012-05-22 | 2012-05-22 | SONOS (silicon oxide nitride oxide silicon) device with plurality of grades of storage layers and medium layers and forming method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012101617194A CN102709292A (en) | 2012-05-22 | 2012-05-22 | SONOS (silicon oxide nitride oxide silicon) device with plurality of grades of storage layers and medium layers and forming method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN102709292A true CN102709292A (en) | 2012-10-03 |
Family
ID=46901946
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2012101617194A Pending CN102709292A (en) | 2012-05-22 | 2012-05-22 | SONOS (silicon oxide nitride oxide silicon) device with plurality of grades of storage layers and medium layers and forming method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102709292A (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6285596B1 (en) * | 1997-04-25 | 2001-09-04 | Nippon Steel Corporation | Multi-level type nonvolatile semiconductor memory device |
| TW200910532A (en) * | 2007-08-22 | 2009-03-01 | Macronix Int Co Ltd | Non-volatile memory device and method for manufacturing the same |
| CN101924109A (en) * | 2009-06-11 | 2010-12-22 | 上海华虹Nec电子有限公司 | Structure and method for improving data storage capability of silicon oxide nitride oxide semiconductor (SONOS) flash memory |
| CN102290444A (en) * | 2011-08-31 | 2011-12-21 | 上海宏力半导体制造有限公司 | SONOS (Silicon Oxide Nitride Oxide Semiconductor) structure and SONOS (Silicon Oxide Nitride Oxide Semiconductor) memory |
-
2012
- 2012-05-22 CN CN2012101617194A patent/CN102709292A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6285596B1 (en) * | 1997-04-25 | 2001-09-04 | Nippon Steel Corporation | Multi-level type nonvolatile semiconductor memory device |
| TW200910532A (en) * | 2007-08-22 | 2009-03-01 | Macronix Int Co Ltd | Non-volatile memory device and method for manufacturing the same |
| CN101924109A (en) * | 2009-06-11 | 2010-12-22 | 上海华虹Nec电子有限公司 | Structure and method for improving data storage capability of silicon oxide nitride oxide semiconductor (SONOS) flash memory |
| CN102290444A (en) * | 2011-08-31 | 2011-12-21 | 上海宏力半导体制造有限公司 | SONOS (Silicon Oxide Nitride Oxide Semiconductor) structure and SONOS (Silicon Oxide Nitride Oxide Semiconductor) memory |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9431257B2 (en) | Salicided structure to integrate a flash memory device with a high κ, metal gate logic device | |
| CN105190889B (en) | Tungsten silicide gate-source and cell pillar fabrication of vertical NAND strings to control turn-on current | |
| US8283716B2 (en) | High performance flash memory devices | |
| JP2008098602A (en) | Laminated thin film transistor type nonvolatile memory device and method of manufacturing thereof | |
| CN102315173A (en) | Preparation method of three-dimensional multivalued nonvolatile memory | |
| KR100745400B1 (en) | Gate structure and method of forming the same, non-volatile memory device and method of manufacturing the same | |
| US8604535B2 (en) | Non-volatile memory device and method of manufacturing the same | |
| CN1607667A (en) | Nonvolatile memory cell employing a plurality of dielectric nanoclusters and method of fabricating the same | |
| US9490016B2 (en) | Semiconductor device and method for fabricating the same | |
| US8999828B2 (en) | Method and device for a split-gate flash memory with an extended word gate below a channel region | |
| CN102290444A (en) | SONOS (Silicon Oxide Nitride Oxide Semiconductor) structure and SONOS (Silicon Oxide Nitride Oxide Semiconductor) memory | |
| US9570457B2 (en) | Method to control the common drain of a pair of control gates and to improve inter-layer dielectric (ILD) filling between the control gates | |
| CN102280378B (en) | The forming method of SONOS structure | |
| US20160268387A1 (en) | Split-gate flash memory with improved program efficiency | |
| CN102810541A (en) | Memory and manufacturing method thereof | |
| US11450680B2 (en) | Split gate charge trapping memory cells having different select gate and memory gate heights | |
| CN102709292A (en) | SONOS (silicon oxide nitride oxide silicon) device with plurality of grades of storage layers and medium layers and forming method thereof | |
| US10714479B2 (en) | One-transistor dram cell device based on polycrystalline silicon with FinFET structure and fabrication method thereof | |
| CN103094355A (en) | Nanocrystalline memory and manufacturing method thereof | |
| US9401434B2 (en) | E-flash cell band engineering for erasing speed enhancement | |
| CN112103292B (en) | Memory and manufacturing method thereof | |
| CN108054168B (en) | Flash memory unit structure and manufacturing method thereof | |
| CN112768454B (en) | Erasing operation method of three-dimensional memory | |
| US20160172200A1 (en) | Method for fabricating non-volatile memory device | |
| KR20100111130A (en) | Vertical type non volatile memory device and method for fabricating the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| ASS | Succession or assignment of patent right |
Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HONGLI SEMICONDUCTOR MANUFACTURE CO LTD, SHANGHAI Effective date: 20140408 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20140408 Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399 Applicant after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: Zuchongzhi road in Pudong Zhangjiang hi tech park Shanghai city Pudong New Area No. 1399 201203 Applicant before: Hongli Semiconductor Manufacture Co., Ltd., Shanghai |
|
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20121003 |