CN102709270A - MIM (Metal Insulator Metal) capacitor and forming method thereof - Google Patents
MIM (Metal Insulator Metal) capacitor and forming method thereof Download PDFInfo
- Publication number
- CN102709270A CN102709270A CN2012101647490A CN201210164749A CN102709270A CN 102709270 A CN102709270 A CN 102709270A CN 2012101647490 A CN2012101647490 A CN 2012101647490A CN 201210164749 A CN201210164749 A CN 201210164749A CN 102709270 A CN102709270 A CN 102709270A
- Authority
- CN
- China
- Prior art keywords
- dielectric layer
- pole plate
- capacitor
- opening
- interlayer dielectric
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Landscapes
- Semiconductor Integrated Circuits (AREA)
Abstract
The invention provides an MIM (Metal Insulator Metal) capacitor and a forming method thereof. The MIM capacitor comprises a base, a first polar plate, an interlayer medium layer, a capacitor medium layer, and a second polar plate, wherein the first polar plate is located on the base; the interlayer medium layer with an opening is located on the first polar plate, and the first polar plate is exposed from the opening; the capacitor medium layer is located on the bottom part of the opening; and the second polar plate is located on the capacitor medium layer, and further higher than the opening. According to the technical scheme, i.e. the MIM capacitor and the forming method thereof, RC (Resistor Capacitor) delay in connection between the second polar plate and the structures of other devices can be reduced.
Description
Technical field
The present invention relates to technical field of semiconductors, relate in particular to MIM capacitor and forming method thereof.
Background technology
Capacity cell be usually used in as in the integrated circuits such as radio frequency IC, monolithic microwave IC as electronic passive device.Common capacity cell comprises metal-oxide semiconductor (MOS) (MOS) electric capacity, PN junction electric capacity and MIM (metal-insulator-metal is called for short MIM) electric capacity etc.Wherein, MIM electric capacity provides the electrology characteristic that is superior to mos capacitance and PN junction electric capacity in some special applications; This is because mos capacitance and PN junction electric capacity all are subject to itself structure, and electrode is easy to generate cavitation layer when work, causes its frequency characteristic to reduce.And MIM electric capacity can provide frequency and temperature correlated characteristic preferably.In addition, in semiconductor was made, MIM electric capacity can be formed at interlayer metal and copper-connection processing procedure, had also reduced degree of difficulty and the complexity integrated with the CMOS front-end process.
With reference to figure 1, traditional M IM electric capacity comprises: be positioned at first pole plate 11 in the substrate 10, be positioned at the capacitor dielectric layer 12 on first pole plate 11, be positioned at second pole plate 12 on the capacitor dielectric layer 12.Usually; For first pole plate 11, second pole plate 12 are electrically connected with other devices; Form interlayer dielectric layer 14, cover MIM capacitor and substrate 10, formation is electrically connected with first pole plate 11 in interlayer dielectric layer 14 afterwards first plug 16, second plug 15 that is electrically connected with second pole plate 12; Afterwards, on interlayer dielectric layer 14, form conductive layer, conductive layer is carried out photoetching, etching form the conducting block 17 that is electrically connected with first plug 15, the conducting block 18 that is electrically connected with second plug 16.Much more more can be with reference to U.S. Patent No. document US on the 8th 7317221B2 January in 2008 about the content of MIM capacitor.
Yet in the MIM capacitor of prior art, second pole plate 13 is electrically connected with other device architectures through first plug 15, and first plug has resistance, and this has the problem of RC delay when having caused second pole plate 13 to be connected with other device architectures.
Summary of the invention
The problem that the present invention solves is the MIM capacitor of prior art, and second pole plate has the problem that RC postpones when being connected with other devices.
For addressing the above problem, the present invention provides a kind of MIM capacitor, comprising:
Substrate;
Be positioned at said suprabasil first pole plate;
Be positioned at the interlayer dielectric layer that has opening on said first pole plate, and said opening exposes said first pole plate;
Be positioned at the capacitor dielectric layer of said open bottom;
Be positioned at second pole plate on the said capacitor dielectric layer, and said second pole plate exceeds said opening.
Optional, said capacitor dielectric layer also is positioned at the sidewall of said opening.
Optional, said first pole plate has the marginal portion that exceeds second pole plate;
Said capacitor also comprises: be positioned at the plug of said interlayer dielectric layer, and said plug is positioned on the said marginal portion; Be positioned at the conducting block on the said plug.
Optional, said conducting block, plug are identical with the material of said second pole plate.
Optional, the material of said second pole plate is an aluminium.
The present invention also provides a kind of method that forms MIM capacitor, comprising:
Substrate is provided;
In said substrate, form first pole plate;
Formation has the interlayer dielectric layer of opening, covers said first pole plate and substrate, and said opening exposes said first pole plate;
Form the capacitor dielectric layer in said open bottom;
In said opening, on the capacitor dielectric layer, form second pole plate that exceeds said opening.
Optional, the step that in said substrate, forms first pole plate specifically comprises:
In said substrate, form first conductive layer;
To said first conductive layer carry out photoetching, etching technics forms first pole plate.
Optional, the step that forms the interlayer dielectric layer with opening comprises:
Form interlayer dielectric layer, cover said first pole plate and substrate;
Said interlayer dielectric layer is carried out photoetching, etching technics formation opening.
Optional, said capacitor dielectric layer also is formed on the sidewall of said opening, and the step that forms the capacitor dielectric layer comprises:
Form dielectric layer, cover the upper surface of sidewall, bottom and the interlayer dielectric layer of said opening;
Said dielectric layer is carried out photoetching, etching formation capacitor dielectric layer.
Optional, the step that forms second pole plate comprises:
Form second conductive layer, cover said interlayer dielectric layer and capacitor dielectric layer, and exceed said opening;
To said second conductive layer carry out photoetching, etching technics forms second pole plate.
Optional, also comprise: after forming the capacitor dielectric layer, form before second conductive layer, in said interlayer dielectric layer, form through hole;
When forming second conductive layer, said second conductive layer is also filled said through hole and is formed plug, and said plug is electrically connected with said first pole plate;
During graphical second conductive layer, on said plug, also formed conducting block.
Compared with prior art, the present invention has the following advantages:
MIM capacitor of the present invention, second pole plate is positioned at the interlayer dielectric layer on first pole plate, and exceeds interlayer dielectric layer, directly is electrically connected with other device architectures; Rather than as prior art, second pole plate is electrically connected with other device architectures through first plug that is positioned at interlayer dielectric layer; Therefore, be equivalent to increase the quantity of first plug in the prior art, be equivalent to increase the quantity of circuit parallel resistance, corresponding resistance value has also just reduced, the RC delay in the time of therefore can reducing second pole plate and be connected with other device architectures.
Description of drawings
Fig. 1 is the cross-sectional view of MIM capacitor in the prior art;
Fig. 2 is the schematic flow sheet of method of the formation MIM capacitor of the specific embodiment of the invention;
Fig. 3-Fig. 8 is the cross-sectional view of method of the formation MIM capacitor of the specific embodiment of the invention.
Embodiment
For make above-mentioned purpose of the present invention, feature and advantage can be more obviously understandable, does detailed explanation below in conjunction with the accompanying drawing specific embodiments of the invention.
Set forth detail in the following description so that make much of the present invention.But the present invention can be different from alternate manner described here and implements with multiple, and those skilled in the art can do similar popularization under the situation of intension of the present invention.Therefore the present invention does not receive the restriction of following disclosed embodiment.
Fig. 2 is the schematic flow sheet of method of the formation MIM capacitor of the specific embodiment of the invention; Fig. 3-Fig. 8 is the cross-sectional view of method of the formation MIM capacitor of the specific embodiment of the invention; Below in conjunction with referring to figs. 2 and 3 to Fig. 8, the method for the formation MIM capacitor of the specific embodiment of the invention is detailed.
In conjunction with referring to figs. 2 and 3, description of step S21 provides substrate 30.The material of substrate 30 can be monocrystalline silicon (Si), monocrystalline germanium (Ge), SiGe (GeSi) or carborundum (SiC); Also can be silicon-on-insulator (SOI) or germanium on insulator (GOI); Perhaps can also be other material, for example III-V compounds of group such as GaAs.Can be formed with device architecture in the substrate 30, for example MOS transistor etc.Also can not form device architecture in the substrate 30.
In conjunction with reference to figure 2 and Fig. 4, description of step S22 forms first pole plate 41 in said substrate 30.Concrete, the step that forms first pole plate comprises: in substrate 30, form first conductive layer, to said first conductive layer carry out photoetching, etching technics forms first pole plate 41.This first conductive layer can be metal, and material can be electrode metal commonly used such as Cu or Al.The material of first conductive layer also can be metallic compound or metal alloy, for example can select a kind of among TiN, TaN, Al-Cu, the Ru or their combination in any.First conductive layer can be single layer structure, also can be laminated construction, such as, first conductive layer is the individual layer aluminium lamination, first conductive layer is the laminated construction of aluminium lamination and copper layer.
In conjunction with referring to figs. 2 and 5, description of step S23, form interlayer dielectric layer 32 with opening 31, cover said first pole plate 41 and substrate 30, said opening 31 exposes said first pole plate 41.Wherein, the size of second pole plate that forms promptly of another pole plate of the size of opening 31 and capacitor dielectric layer need equate that second pole plate afterwards is formed in the opening 31.
Concrete, the step that forms the interlayer dielectric layer with opening comprises: form interlayer dielectric layer 32, cover said first pole plate 41 and substrate 30; Said interlayer dielectric layer 32 is carried out photoetching, etching technics formation opening 31.Wherein, the material of interlayer dielectric layer can well known to a person skilled in the art dielectric material for silica or silicon nitride etc., and the formation method of interlayer dielectric layer can be selected chemical vapor deposition method.
In conjunction with referring to figs. 2 and 6, description of step S24, form capacitor dielectric layer 42 in said opening 31 bottoms.In the present embodiment, the step that forms capacitor dielectric layer 42 comprises: utilize chemical vapor deposition method to form dielectric layer, cover the upper surface of sidewall, bottom and the interlayer dielectric layer of said opening; Then to said dielectric layer being carried out photoetching, etching formation capacitor dielectric layer 42.Wherein, capacitor dielectric layer 42 also is formed on the sidewall and interlayer dielectric layer 32 of said opening 31.
Among the present invention, as long as the capacitor dielectric layer is formed on the effect that the dielectric layer between first pole plate and second pole plate promptly can be played in the bottom of opening 31.In the embodiment of the invention, owing to utilize photoetching, etching technics etching dielectric layer to form the capacitor dielectric layer; In photoetching process, if etch away the dielectric layer of sidewall, then need the photoresist layer of pairs of openings sidewall to make public, develop; Owing to the photoresist layer of the photoresist layer on the interlayer dielectric layer, opening sidewalls is different apart from the distance of exposure device; Can cause the inhomogeneous or incomplete situation of making public of photoresist layer exposure on the opening sidewalls; Cause in the developing process photoresist on the sidewall not removed fully; Thereby influence the figure of photoresist layer, the dielectric layer on the sidewall can not be removed fully.Because the capacitor dielectric layer on the sidewall can not influence the performance of MIM capacitor, therefore, for technology simply can also form the capacitor dielectric layer on the sidewall of opening.
In addition; Because the restriction of lithographic accuracy during photoetching, litho pattern can not only cover the sidewall and the bottom of opening, on interlayer dielectric layer, around the opening, has photoresist; Therefore, the marginal portion on interlayer dielectric layer, around the opening also is formed with the capacitor dielectric layer.And; Because the capacitor dielectric layer on interlayer dielectric layer can not influence the performance of MIM capacitor; Therefore; Can be on interlayer dielectric layer, the marginal portion around the opening also forms the capacitor dielectric layer, can reduce the requirement to the litho pattern precision like this, need not limit sidewall and bottom that litho pattern only covers opening.
Because among the present invention; Need first pole plate be electrically connected with other device architecture circuit through the plug that is positioned at interlayer dielectric layer; Therefore the length of first pole plate is greater than the length of second pole plate; Make first pole plate have the marginal portion that exceeds second pole plate, promptly first pole plate has and does not have the part relative with second pole plate.After forming capacitor dielectric layer 42, with reference to figure 7, interlayer dielectric layer 32 is carried out photoetching, etching, part goes up, forms through hole 51 in the interlayer dielectric layer on the edge of.
In conjunction with reference to figs. 2 and 7, Fig. 8, description of step S25 forms second pole plate 43 that exceeds said opening 31 in said opening 31, on the capacitor dielectric layer 42.When forming second pole plate, also formed the plug 52 that is connected with first pole plate in the interlayer dielectric layer and be positioned at the conducting block 53 on the plug 52.Concrete, the step that forms second pole plate 43, plug 52 and conducting block 53 comprises: form second conductive layer, cover said interlayer dielectric layer and capacitor dielectric layer, and exceed said opening and through hole, the interior electric conducting material of through hole is as plug 52; Second conductive layer is carried out flatening process, afterwards to said second conductive layer carry out photoetching, etching technics forms second pole plate 43 and conducting block 53.This second conductive layer can be metal, and material can be electrode metal commonly used such as Cu or Al.Second conductive layer can be single layer structure, also can be laminated construction, such as, second conductive layer is the individual layer aluminium lamination, second conductive layer is the laminated construction of aluminium lamination and copper layer.
Wherein, second pole plate also is positioned on the interlayer dielectric layer, the marginal portion around the opening, when utilizing graphical second conductive layer of photoetching, etching technics, need not carry out strictness control to litho pattern, the reduction technology difficulty like this.
Among the present invention,, rather than be electrically connected the step of formation through hole, plug and the conducting block that then can not have to describe in the above specific embodiment with other device architectures through the plug in the interlayer dielectric layer if first pole plate is electrically connected with intrabasement device architecture.
With reference to figure 8, the present invention also provides a kind of MIM capacitor, comprising:
Be positioned at said suprabasil first pole plate 41;
Be positioned at the interlayer dielectric layer 32 that has opening on said first pole plate 41, and said opening exposes said first pole plate 41;
Be positioned at the capacitor dielectric layer 42 of said open bottom;
Be positioned at second pole plate 43 on the said capacitor dielectric layer 42, and said second pole plate exceeds said opening.
In the specific embodiment of the invention, capacitor dielectric layer 42 also is positioned on the sidewall and interlayer dielectric layer 32 of said opening, parameatal marginal portion.First pole plate 41 has the marginal portion that exceeds second pole plate 43, and this first pole plate 41 is electrically connected with the marginal portion of second pole plate through the plug 52 that is positioned at said interlayer dielectric layer 32; Plug 52 is electrically connected with other device architectures through position conducting block 53 on it.Conducting block is identical with the material of said second pole plate.
Among the present invention,, rather than be electrically connected with other device architectures, then can not have plug and the conducting block described in the above specific embodiment through the plug in the interlayer dielectric layer if first pole plate is electrically connected with intrabasement device architecture.
About forming the embodiment part of MIM capacitor method, can be incorporated herein about the content of structure and material, do not do at this and give unnecessary details.
MIM capacitor of the present invention, second pole plate is positioned at the interlayer dielectric layer on first pole plate, and exceeds interlayer dielectric layer, directly is electrically connected with other device architectures; Rather than as prior art, second pole plate is electrically connected with other device architectures through first plug that is positioned at interlayer dielectric layer; Therefore, be equivalent to increase the quantity of first plug in the prior art, be equivalent to increase the quantity of circuit parallel resistance, corresponding resistance value has also just reduced, the RC delay in the time of therefore can reducing second pole plate and be connected with other device architectures.
Though the present invention with preferred embodiment openly as above; But it is not to be used for limiting the present invention; Any those skilled in the art are not breaking away from the spirit and scope of the present invention; Can utilize the method and the technology contents of above-mentioned announcement that technical scheme of the present invention is made possible change and modification, therefore, every content that does not break away from technical scheme of the present invention; To any simple modification, equivalent variations and modification that above embodiment did, all belong to the protection range of technical scheme of the present invention according to technical spirit of the present invention.
Claims (11)
1. a MIM capacitor is characterized in that, comprising:
Substrate;
Be positioned at said suprabasil first pole plate;
Be positioned at the interlayer dielectric layer that has opening on said first pole plate, and said opening exposes said first pole plate;
Be positioned at the capacitor dielectric layer of said open bottom;
Be positioned at second pole plate on the said capacitor dielectric layer, and said second pole plate exceeds said opening.
2. MIM capacitor as claimed in claim 1 is characterized in that said capacitor dielectric layer also is positioned at the sidewall of said opening.
3. MIM capacitor as claimed in claim 1 is characterized in that, said first pole plate has the marginal portion that exceeds second pole plate;
Said capacitor also comprises: be positioned at the plug of said interlayer dielectric layer, and said plug is positioned on the said marginal portion; Be positioned at the conducting block on the said plug.
4. MIM capacitor as claimed in claim 3 is characterized in that, said conducting block, plug are identical with the material of said second pole plate.
5. MIM capacitor as claimed in claim 1 is characterized in that, the material of said second pole plate is an aluminium.
6. a method that forms MIM capacitor is characterized in that, comprising:
Substrate is provided;
In said substrate, form first pole plate;
Formation has the interlayer dielectric layer of opening, covers said first pole plate and substrate, and said opening exposes said first pole plate;
Form the capacitor dielectric layer in said open bottom;
In said opening, on the capacitor dielectric layer, form second pole plate that exceeds said opening.
7. the method for formation MIM capacitor as claimed in claim 6 is characterized in that, the step that in said substrate, forms first pole plate specifically comprises:
In said substrate, form first conductive layer;
To said first conductive layer carry out photoetching, etching technics forms first pole plate.
8. the method for formation MIM capacitor as claimed in claim 6 is characterized in that, the step that forms the interlayer dielectric layer with opening comprises:
Form interlayer dielectric layer, cover said first pole plate and substrate;
Said interlayer dielectric layer is carried out photoetching, etching technics formation opening.
9. the method for formation MIM capacitor as claimed in claim 6 is characterized in that, said capacitor dielectric layer also is formed on the sidewall of said opening, and the step that forms the capacitor dielectric layer comprises:
Form dielectric layer, cover the upper surface of sidewall, bottom and the interlayer dielectric layer of said opening;
Said dielectric layer is carried out photoetching, etching formation capacitor dielectric layer.
10. the method for formation MIM capacitor as claimed in claim 6 is characterized in that, the step that forms second pole plate comprises:
Form second conductive layer, cover said interlayer dielectric layer and capacitor dielectric layer, and exceed said opening;
To said second conductive layer carry out photoetching, etching technics forms second pole plate.
11. the method for formation MIM capacitor as claimed in claim 10 is characterized in that, also comprises: after forming the capacitor dielectric layer, form before second conductive layer, in said interlayer dielectric layer, form through hole;
When forming second conductive layer, said second conductive layer is also filled said through hole and is formed plug, and said plug is electrically connected with said first pole plate;
During graphical second conductive layer, on said plug, also formed conducting block.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012101647490A CN102709270A (en) | 2012-05-23 | 2012-05-23 | MIM (Metal Insulator Metal) capacitor and forming method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012101647490A CN102709270A (en) | 2012-05-23 | 2012-05-23 | MIM (Metal Insulator Metal) capacitor and forming method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN102709270A true CN102709270A (en) | 2012-10-03 |
Family
ID=46901928
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2012101647490A Pending CN102709270A (en) | 2012-05-23 | 2012-05-23 | MIM (Metal Insulator Metal) capacitor and forming method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102709270A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103426728A (en) * | 2013-08-29 | 2013-12-04 | 上海宏力半导体制造有限公司 | Capacitor structure and manufacturing method thereof |
| CN108538816A (en) * | 2018-02-07 | 2018-09-14 | 厦门市三安集成电路有限公司 | A kind of MIM capacitor and production method of silicon nitride-polyimides complex media |
| CN110071096A (en) * | 2019-03-13 | 2019-07-30 | 福建省福联集成电路有限公司 | A kind of stacked capacitor and production method improving capacitance and pressure resistance |
| CN111128957A (en) * | 2019-12-26 | 2020-05-08 | 华虹半导体(无锡)有限公司 | MIM capacitor with embedded structure and manufacturing method thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1253661A (en) * | 1997-04-29 | 2000-05-17 | 艾利森电话股份有限公司 | Capacitors in integrated circuits |
| CN1319893A (en) * | 2000-03-31 | 2001-10-31 | 国际商业机器公司 | Electric capacitor structure and method for making same |
| US20080145997A1 (en) * | 2006-12-18 | 2008-06-19 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of forming a metal-insulator-metal capacitor |
| US20100079924A1 (en) * | 2008-09-30 | 2010-04-01 | Keating Steven J | Method of patterning a metal on a vertical sidewall of an excavated feature, method of forming an embedded MIM capacitor using same, and embedded memory device produced thereby |
-
2012
- 2012-05-23 CN CN2012101647490A patent/CN102709270A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1253661A (en) * | 1997-04-29 | 2000-05-17 | 艾利森电话股份有限公司 | Capacitors in integrated circuits |
| CN1319893A (en) * | 2000-03-31 | 2001-10-31 | 国际商业机器公司 | Electric capacitor structure and method for making same |
| US20080145997A1 (en) * | 2006-12-18 | 2008-06-19 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of forming a metal-insulator-metal capacitor |
| US20100079924A1 (en) * | 2008-09-30 | 2010-04-01 | Keating Steven J | Method of patterning a metal on a vertical sidewall of an excavated feature, method of forming an embedded MIM capacitor using same, and embedded memory device produced thereby |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103426728A (en) * | 2013-08-29 | 2013-12-04 | 上海宏力半导体制造有限公司 | Capacitor structure and manufacturing method thereof |
| CN103426728B (en) * | 2013-08-29 | 2017-06-09 | 上海华虹宏力半导体制造有限公司 | Capacitor arrangement and preparation method thereof |
| CN108538816A (en) * | 2018-02-07 | 2018-09-14 | 厦门市三安集成电路有限公司 | A kind of MIM capacitor and production method of silicon nitride-polyimides complex media |
| CN108538816B (en) * | 2018-02-07 | 2020-03-24 | 厦门市三安集成电路有限公司 | MIM capacitor of silicon nitride-polyimide composite medium and manufacturing method |
| CN110071096A (en) * | 2019-03-13 | 2019-07-30 | 福建省福联集成电路有限公司 | A kind of stacked capacitor and production method improving capacitance and pressure resistance |
| CN111128957A (en) * | 2019-12-26 | 2020-05-08 | 华虹半导体(无锡)有限公司 | MIM capacitor with embedded structure and manufacturing method thereof |
| CN111128957B (en) * | 2019-12-26 | 2021-11-09 | 华虹半导体(无锡)有限公司 | MIM capacitor with embedded structure and manufacturing method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101345231B (en) | Semiconductor chip, method of fabricating the same and stack package having the same | |
| US10332911B2 (en) | Integrated circuits (ICs) on a glass substrate | |
| US10950689B2 (en) | Semiconductor device with a through-substrate via hole having therein a capacitor and a through-substrate via conductor | |
| US8101494B2 (en) | Structure, design structure and method of manufacturing a structure having VIAS and high density capacitors | |
| KR101502663B1 (en) | Capacitor for interposers and methods of manufacture thereof | |
| US9437491B2 (en) | Method of forming chip with through silicon via electrode | |
| US10153285B2 (en) | Formation method of semiconductor device with embedded capacitor | |
| JP2004193602A (en) | Method for manufacturing metal-insulator-metal (mim) capacitor and metal register for subsequent process (beol) with copper | |
| CN104103495A (en) | Semiconductor device with MIM capacitor and formation method thereof | |
| CN105514092A (en) | Metal-insulator-metal capacitor and method for forming same | |
| CN102446886A (en) | 3D (three-dimensional) integrated circuit structure and forming method thereof | |
| US8629488B2 (en) | Method for manufacturing an energy storage device and structure therefor | |
| CN107424993A (en) | Isolation structure for the circuit of common substrate | |
| CN110858562B (en) | Method for manufacturing semiconductor element and semiconductor element manufactured by same | |
| CN102709270A (en) | MIM (Metal Insulator Metal) capacitor and forming method thereof | |
| CN103208415A (en) | Capacitor and forming method thereof | |
| US8645898B2 (en) | Structure and design structure for high-Q value inductor and method of manufacturing the same | |
| US8872289B2 (en) | Micro-electro-mechanical system (MEMS) structures and design structures | |
| JP2006229226A (en) | Semiconductor device with integrated circuit | |
| US20170084684A1 (en) | Metal-insulator-metal capacitor structure | |
| WO2018125239A1 (en) | Microelectronic devices having air gap structures integrated with interconnect for reduced parasitic capacitances | |
| CN100568500C (en) | The semiconductor structure of semiconductor structure manufacture method and its manufacturing | |
| US8372725B2 (en) | Structures and methods of forming pre fabricated deep trench capacitors for SOI substrates | |
| KR100954920B1 (en) | Inductor structure | |
| KR100955841B1 (en) | Fabrication method of a semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| ASS | Succession or assignment of patent right |
Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HONGLI SEMICONDUCTOR MANUFACTURE CO LTD, SHANGHAI Effective date: 20140409 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20140409 Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399 Applicant after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: Zuchongzhi road in Pudong Zhangjiang hi tech park Shanghai city Pudong New Area No. 1399 201203 Applicant before: Hongli Semiconductor Manufacture Co., Ltd., Shanghai |
|
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WD01 | Invention patent application deemed withdrawn after publication | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20121003 |