CN102709198A - Mold array process method for preventing periphery of substrate from being exposed - Google Patents
Mold array process method for preventing periphery of substrate from being exposed Download PDFInfo
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- CN102709198A CN102709198A CN2011100751416A CN201110075141A CN102709198A CN 102709198 A CN102709198 A CN 102709198A CN 2011100751416 A CN2011100751416 A CN 2011100751416A CN 201110075141 A CN201110075141 A CN 201110075141A CN 102709198 A CN102709198 A CN 102709198A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Microelectronics & Electronic Packaging (AREA)
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- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The invention discloses a mold array process method for preventing the periphery of a substrate from being exposed. The method is characterized by comprising usage processes of two packaging materials in the mold array process procedure, and comprises the following steps of: molding a first packaging material for sealing a chip onto a substrate strip to continuously cover a cutting channel between a substrate unit and a unit; and before a second packaging material is formed, forming at least two cutting grooves which penetrate through the substrate strip but do not penetrate through the first packaging material on the cutting channel in a pre-cutting mode and have a certain width to ensure that the substrate unit has the periphery which is exposed out of the cutting channel, and filling the second packaging material into the cutting grooves. Therefore, the periphery of the substrate unit which is cut in an individual separation mode is still coated by the second packaging material, so that the aim of preventing the periphery of the substrate from being exposed during mold array process is fulfilled.
Description
Technical field
The invention relates to the encapsulation manufacturing technology of semiconductor device, particularly relevant for a kind of mould envelope array processing method that prevents that substrate periphery from exposing.
Background technology
Tradition based on cost consideration and volume production demand, generally adopts mould envelope ARRAY PROCESSING (Mold Array Process, MAP) technology in semiconductor packaging.With the carrier of a substrate strip (Substrate Strip) as a plurality of chips; Substrate strip includes the base board unit that is arranged in a matrix more than two; After process is provided with semiconductor packages operations such as chip, electric connection; One forms area greater than the Cutting Road between matrix norm adhesive body continuous covered substrate unit and the base board unit, carries out the singulation cutting along Cutting Road again, just can make two above semiconductor packaging structures.
Fig. 1 is a kind of semiconductor packaging structure that utilizes the known window type ball grid array form that mould envelope ARRAY PROCESSING makes, and Fig. 2 seals employed substrate strip in the ARRAY PROCESSING for mould.As shown in Figure 1, known semiconductor packages structure 100 mainly comprises base board unit 113, chip 120, adhesive body 130.This chip 120 is arranged at the upper surface 111 of this base board unit 113.As when being the window type ball grid array form, this base board unit 113 has more the central slotted eye 117 that runs through upper surface 111 and lower surface 112, and two of active surface 121 that are positioned at this chip 120 with top electrode 122 in alignment with this central authorities' slotted eye 117.This chip 120 is electrically connected to this base board unit 113 through this central authorities' slotted eye 117 with these electrodes 122 by the bonding wire 150 that two above routings form commonly.And this adhesive body 130 be formed on the upper surface 111 of this base board unit 113 with this central authorities' slotted eye 117 in; To seal this chip 120 and these bonding wires 150; And this lower surface of this base board unit 113 can be provided with two above soldered balls 160, with the terminal that externally electrically connects as this semiconductor packaging structure 100.Yet according to present known mould envelope ARRAY PROCESSING technology; This adhesive body 130 can't cover the side 116 to this base board unit 113; Cause these base board unit 113 inner core layer and metallic circuits to expose inevitably, it is inner to make that aqueous vapor intrudes into encapsulation easily, causes production reliability not good.
As shown in Figure 2, above-mentioned base board unit 113 in known mould-seal array treating process for a plurality of integrally formed and be arranged in known substrate strip 110.Be formed with Cutting Road crisscross more than two 114 with periphery between the adjacent substrate unit 113.Cooperate and consult Fig. 1, at sticking crystalline substance and after electrically connecting, above-mentioned adhesive body 130 covers on these base board units 113 and these Cutting Roads 114 for the mould envelope forms also continuously.And the Cutting Road 114 between each base board unit 113 must be removed at the technology back segment, separates to reach singulation, so Cutting Road 114 positions of substrate strip 110 and the adhesive body 130 on these Cutting Roads 114 can not be present in the final encapsulating products.When cutting off this base board unit 113 according to these Cutting Roads 114; Can cut simultaneously and wear this adhesive body 130 and this substrate strip 110; Make this base board unit 113 have to trim in what this adhesive body 130 was cut the side to appear side 116, promptly the side 116 of this base board unit 113 can't be by these adhesive body 130 protections.Therefore, at the singulation after separating, the plating circuit and the core layer of the side 116 of this base board unit 113 can present the state of exposing, and cause moisture-proof relatively poor, and are vulnerable to the interference of extraneous foreign matter.In addition, cutting tool is pullled easily or is corrupted to the perimeter circuit that is positioned at this base board unit 113 in the singulation separation process, and causes follow-up harmful effect.
Summary of the invention
In view of this, main purpose of the present invention be to provide a kind of and can make that encapsulating products is anti-oxidant, moisture-resistant gas and resist the mould envelope array processing method that substrate periphery exposes that prevents of other environmental injury.
For achieving the above object, the present invention solves its technical problem and adopts following technical scheme to realize.The present invention discloses a kind of mould envelope array processing method that prevents that substrate periphery from exposing; At first; One substrate strip is provided, and this substrate strip has upper surface and opposing lower surface, and this substrate strip includes two above substrate unit; The size of each base board unit is formed with a Cutting Road corresponding to the semiconductor packaging structure between the adjacent substrate unit; Then, two above chips are set on these base board units; Afterwards, said chip is electrically connected to pairing these base board units; Afterwards, at upper surface mould envelope formation first encapsulating material of substrate strip, to cover these base board units and these Cutting Roads continuously; Afterwards; Precut step, it forms two cutting grooves that run through this substrate strip at least on these Cutting Roads, but does not run through this first encapsulating material; The width of each cutting groove is greater than the width of corresponding Cutting Road, so that these base board units have the periphery that is emerging in outside these Cutting Roads; Afterwards, in cutting groove, form second encapsulating material, to coat the periphery of these base board units; At last; Carry out the singulation separating step; Remove at this first encapsulating material on these Cutting Roads and second encapsulating material in these Cutting Roads with cutting mode; So that these base board unit singulation are separated into independently semiconductor packaging structure, and the periphery of these base board units is still coated by this second encapsulating material after cutting.
The present invention solves its technical problem and also can adopt following technical measures further to realize.
In aforesaid mould envelope array processing method; This substrate strip can be formed with central slotted eye in addition in each base board unit; In the step of these chips was set, the active surface of these chips can be pasted to this substrate strip, and the electrode exposition of these chips is in this central authorities' slotted eye.
In aforesaid mould envelope array processing method, in the step that forms this second encapsulating material, this second encapsulating material can more be formed in these central slotted eyes.
In aforesaid mould envelope array processing method, in said precut step, these central slotted eyes can be communicated with these cutting grooves by the groove of the lower surface that is formed on this substrate strip.
In aforesaid mould envelope array processing method, form in the step of this first encapsulating material in the mould envelope, this first encapsulating material can more be formed in these central slotted eyes.
In aforesaid mould envelope array processing method, the said step that chip is electrically connected to pairing base board unit can comprise with the routing mode and forms two above bonding wires, and these bonding wires are connected to these base board units via these central slotted eyes with these chips.
In aforesaid mould envelope array processing method, the said step that chip is electrically connected to pairing base board unit can comprise the electrode that is engaged to these chips with two above leads of this substrate strip through these central slotted eyes.
In aforesaid mould envelope array processing method, with before said singulation separating step, the step that can comprise in addition is after the step of said formation second encapsulating material: the lower surface in substrate strip forms two above soldered balls.
In aforesaid mould envelope array processing method, this first encapsulating material and this second encapsulating material cut the width that the gap width that removes can be same as these Cutting Roads.
In aforesaid mould envelope array processing method, with before said singulation separating step, the step that can comprise in addition is after the step of said formation second encapsulating material: carry out the back baking procedure, to solidify this first encapsulating material and this second encapsulating material.
Can find out that by above technical scheme the mould envelope array processing method that prevents that substrate periphery from exposing of the present invention has the following advantages and effect:
One, can be by after first apotype envelope, on Cutting Road, cutting cutting groove that formation runs through substrate strip in advance as a wherein technological means of the present invention; Wherein the width of cutting groove is greater than the width of corresponding Cutting Road; Be formed in the cutting groove with second encapsulating material again, to coat the periphery of base board unit.So when the singulation separating step; Only can cut Chuanfeng's package material; Can not switch to board structure, solve the problem that substrate side exposes in the known mould envelope array processing method, can avoid the metallic circuit and the core layer of base board unit periphery to expose; And then make encapsulating products reach anti-oxidant, moisture-resistant gas and resist the effect of other environmental injury, and promote the durability of semiconductor package product.
Two, can be by formation and therebetween the precut operation of two kinds of encapsulating materials in MAP technology as a wherein technological means of the present invention; In the singulation separating step of mould envelope ARRAY PROCESSING, can not switch to board structure, avoid the thick cutting stress of singulation separating step to cause internal wiring distortion or displacement in substrate.
Three, can be by formation and therebetween the precut operation of two kinds of encapsulating materials in MAP technology as a wherein technological means of the present invention, cooperate one solidify two kinds of encapsulating materials simultaneously back baking procedure, to simplify the MAP processing step.
Description of drawings
Fig. 1 is a kind of schematic cross-section that seals the semiconductor packaging structure of ARRAY PROCESSING manufacturing with known mould;
Fig. 2 is a kind of local schematic top plan view of substrate strip;
Fig. 3 A to Fig. 3 H seals the element cross-section sketch map in each step of array processing method for a kind of mould that prevents that substrate periphery from exposing according to first specific embodiment of the present invention;
Fig. 4 is the elevational schematic view according to the substrate strip of mould envelope array processing method after accomplishing precut step of first specific embodiment of the present invention;
Fig. 5 A to Fig. 5 H seals the element cross-section sketch map in each step of array processing method for the another kind according to second specific embodiment of the present invention prevents the mould that substrate periphery exposes;
Fig. 6 is the elevational schematic view according to the substrate strip in the substrate strip step is provided in the mould envelope array processing method of second specific embodiment of the present invention;
Fig. 7 is the elevational schematic view according to the substrate strip after accomplishing precut step in the mould envelope array processing method of second specific embodiment of the present invention.
Description of reference numerals
Embodiment
Below will cooperate appended accompanying drawing to specify embodiments of the invention; Yet it should be noted that these accompanying drawings are the sketch map of simplification, only basic framework of the present invention or implementation method are described with illustrative method; So only show element and the syntagmatic relevant with the present invention; The element that is shown among the figure is not that number, shape, the size implemented with reality are done equal proportion and drawn, and some dimension scale and other relative dimensions ratio or exaggerated or simplify processing are to provide clearer description.Actual number, shape and the dimension scale of implementing is a kind of optionally design, and detailed component placement maybe be more complicated.
According to first specific embodiment of the present invention, the schematic cross-section that a kind of mould envelope array processing method that prevents that substrate periphery from exposing is illustrated in element in each step of Fig. 3 A to Fig. 3 H and Fig. 4 accomplish the elevational schematic view that precuts the substrate strip after the step.This mould envelope array processing method that prevents that substrate periphery from exposing specifies as follows.
At first, shown in Fig. 3 A, a substrate strip 210 is provided.This substrate strip 210 has upper surface 211 and opposing lower surface 212.This upper surface 211 can supply the setting of sticking brilliant material and encapsulating material, and this lower surface 212 can supply to engage two above soldered balls, engages for outer surface.Usually this substrate strip 210 is printed circuit board (PCB) and is provided with the metallic circuit that single or double electrically conducts.This substrate strip 210 also can be flexible circuit film or ceramic circuit board.As shown in Figure 4, this substrate strip 210 includes two above substrate unit 213, is the chip carrier of semiconductor packaging structure inside.The size of each base board unit 213 is corresponding to semiconductor packaging structure 200 (shown in Fig. 3 H), and promptly the width of the base board unit 213 of Fig. 3 A is same as the width of the same cross-wise direction of Fig. 3 H semiconductor packaging structure 200.Between adjacent substrate unit 213, be formed with Cutting Road 214.These base board units 213 be arranged in this substrate strip 210, each base board unit 213 can become rectangle or square.When a large amount of production, these base board units 213 are integrally formed in this substrate strip 210 with integrating, and the side of this substrate strip 210 can be provided with registration holes (not drawing among the figure), and making can automation transmission and location in packaging technology.And these Cutting Roads 214 can comprise transverse cuts road and vertical Cutting Road, and are formed between the adjacent substrate unit 213, not as the internal base plate part of semiconductor packaging structure.
Then, shown in Fig. 3 B, two above chips 220 are set on these base board units 213, for example can utilize existing sticking brilliant operation to accomplish.And the material of these chips 220 can be silicon, GaAs or other semiconductor material.The active surface 221 of these chips 220 is formed with various integrated circuit component; DDR2 (Double Data Rate SDRAM II for example; The Double Data Rate synchronous DRAM), DRAM or non-voltile memories such as DDR3, DDR4; And these electrodes 222 are the external end points of chip internal connection integrated circuit, and these electrodes 222 are the weld pad of aluminium or copper material usually, or can be the conductive projection that protrudes in these active surfaces 221.These electrodes 222 can be arranged at the single side, two respective side of the active surface 221 of these chips 220, side or middle position all around.Usually chip 220 is arranged at the middle position in the counterpart substrate unit 213.In the present embodiment, 213 are equipped with chip 220 on each base board unit, but constrained ground not also can be applied to the encapsulation of multi-chip stack, on each base board unit 213, can fold and establish two above chips.Capable of using one two-sided PI (polyimides) adhesive tape, liquid epoxy glue, preparatory matrix, B rank glue (B-stage adhesive) or chip attaching material (Die Attach Material, DAM), so that these chips 220 are bonded on these base board units 213.In addition, the application examples of present embodiment utilization window type ball grid array encapsulation, the active surface 221 of these chips 220 is attached at the upper surface 211 of this substrate strip 210; And this substrate strip 210 can be formed with central slotted eye 217 in addition in each base board unit 213, and this central authorities' slotted eye 217 runs through this substrate strip 210 and is positioned at the middle position of each base board unit 213.In the present embodiment, these electrodes 222 are arranged evenly in the central authorities of these chip 220 active surfaces 221, and in alignment with these central slotted eyes 217.After the step that these chips 220 are set, two of these chips 220 are emerging in this central authorities' slotted eye 217 with top electrode 222.
Afterwards, shown in Fig. 3 C, chip 220 is electrically connected to corresponding base board unit 213.The step of these chips of described electric connection 220 and these base board units 213 can comprise with the routing mode and forms two above bonding wires 250, and these bonding wires 250 are connected to these base board unit 213 internal wirings via these central slotted eyes 217 with the electrode 222 of these chips 220.The formed metal fine of these bonding wire 250 routing technologies capable of using; Its material can be gold or adopts the metal material of similar high conductivity (for example copper or aluminium), can utilize these bonding wires 250 being connected as the signal transmission between these chips 220 to these base board units 213 and ground connection/power supply.Yet not limitedly; These chips 220 also can chip bonding (Flip Chip Bonding), pin engages the electrical interconnects that (Lead Bond) or other known electrical connected mode are accomplished these chips 220 and these base board units 213 except can routing electrically connecting.
Afterwards; Shown in Fig. 3 D; This upper surface 211 moulds envelope in this substrate strip 210 forms first encapsulating material 230; To cover these base board units 213 and these Cutting Roads 214 continuously, promptly the area coverage of this first encapsulating material 230 is equivalent to or greater than the matrix area of forming these base board units 213.Preferably, this first encapsulating material 230 more can cover these chips 220 fully, makes it not receive the pollution of environmental contaminants.The back side that manifests these chips 220 but constrained ground not, these chips 220 also can be naked crystalline form attitude is beneficial to heat radiation.Particularly, this first encapsulating material 230 can be epoxy mould envelope compound (Epoxy Molding Compound EMC), has insulating properties and thermosetting usually.This first encapsulating material 230 can or claim that the technology of pressing mold forms with transfer formation (Transfer Molding); Perhaps this first encapsulating material 230 also can use other known mould envelope technology to form for example compression molding envelope, the printing of using a template or spraying or the like.Preferably; Form in the step of this first encapsulating material 230 in the mould envelope; This first encapsulating material 230 can more be formed in these central slotted eyes 217; To seal these bonding wires 250,, just can not cause the pollution of these bonding wires 250 so the cutting chip can not fall in these central slotted eyes 217 in follow-up precut step.And this first encapsulating material 230 can protrude in this lower surface 212.
Like Fig. 3 E and shown in Figure 4, after this first encapsulating material 230 forms, carry out a precut step, it forms on these Cutting Roads 214 and runs through the cutting groove 215 of this substrate strip 210 more than two, but does not run through this first encapsulating material 230.Worn though this substrate strip 210 cuts, utilize this first encapsulating material 230 still can combine these chips 220 and these base board unit 213 unlikely loosing to leave.As shown in Figure 4 especially, after precut step, the width W 1 of each cutting groove 215 is greater than the width W 2 of corresponding Cutting Road 214, so that these base board units 213 have the periphery 216 that is emerging in outside these Cutting Roads 214.Particularly; These cutting grooves 215 are vertical or/and horizontal linear array along Cutting Road 214; But the width W 1 of cutting groove 215 should be greater than the width W 2 of corresponding Cutting Road 214; In other words, remove part except including the edge that Cutting Road 214 more comprises these base board units 213, make these peripheries 216 of these base board units 213 not overlapping with the form of bigger open slot with these Cutting Roads 214.In detail, the width of these cutting grooves 215 is about 1.2 times to 2 times of width of corresponding Cutting Road 214.Shown in Fig. 3 E, the depth of cut of these cutting grooves 215 should be enough to cut the thickness of wearing this substrate strip 210 but can not surpassing this first encapsulating material 230 for another example, and the cutting groove 215 of formation is irrigation canals and ditches (trench) shape.Generally speaking, the thickness of this substrate strip 210 is about 0.08mm to 0.3mm, and in one embodiment, the degree of depth of these cutting grooves 215 in fact can be identical with the thickness of this substrate strip 210.More detailed, these cutting grooves 215 can be processed by any method, for example are laser drill or machining.For instance, these cutting groove 215 drill bit capable of using apertures are cut toward these upper surface 211 directions by this lower surface 212, to form these cutting grooves 215 greater than the cutter of Cutting Road 214 width.It is diminishing trapezoidal that the cross sectional shape of these cutting grooves 215 can be rectangle, V-arrangement, shaped form, taper, infundibulate or bottom.
Afterwards, shown in Fig. 3 E and Fig. 3 F, in cutting groove 215, form second encapsulating material 240, with the periphery 216 that coats these base board units 213.Particularly, this second encapsulating material 240 fills up these cutting grooves 215 so that these peripheries 216 do not expose.In detail, the material of this second encapsulating material 240 can be same as this first encapsulating material 230, or is other insulating properties thermosetting resin inequality, the for example mobile underfill that is higher than this first encapsulating material.Except traditional mould envelope (or title shifts shaping) method forms, in different embodiment, or printing capable of using or this second encapsulating material 240 of some coating method formation.What deserves to be mentioned is, after the step that forms this second encapsulating material 240, can carry out a back baking procedure in addition,, make the stable and shaping of its material to solidify this first encapsulating material 230 and this second encapsulating material 240.Therefore, can be by formation and therebetween the precut operation of two kinds of encapsulating materials in MAP (mould envelope ARRAY PROCESSING) technology as a wherein technological means of the present invention, cooperate one to solidify baking procedure after two kinds of encapsulating materials simultaneously, to simplify the MAP processing step.
More specifically, shown in Fig. 3 G, after forming the step of this second encapsulating material 240 with the singulation separating step before, can form two above soldered balls 260 at this lower surface 212 of this substrate strip 210, be engaged to the printed circuit board (PCB) of outside for outer surface.These soldered balls 260 can be grid array to be arranged, and it is required with the semiconductor chip that meets Highgrade integration (Integration) to make the base board unit 213 of same units area can hold more I/O links (I/O Connection).Yet constrained ground not, in various embodiment, these soldered balls 260 are also replaceable to be tin cream, contact mat or contact pin.
At last; Shown in Fig. 3 G and Fig. 3 H; Remove at this first encapsulating material 230 and second encapsulating material 240 in these Cutting Roads 214 on these Cutting Roads 214 with cutting mode; Separating these base board units 213 with singulation is independent semiconductor packaging structure 200, and the periphery 216 of these base board units 213 is still coated by this second encapsulating material 240 after cutting.So when the singulation separating step; Only can cut and wear this second encapsulating material 240; Can not switch to this base board unit 213 structures, solve the problem that substrate side exposes in the known mould envelope array processing method, metallic circuit and the core layer that so can avoid being positioned at these base board unit 213 peripheries 216 expose; And then make encapsulating products reach anti-oxidant, moisture-resistant gas and resist the effect of other environmental injury, to promote the durability of semiconductor package product.In addition, in the singulation separating step of mould envelope ARRAY PROCESSING, can not switch to board structure, avoid the thick cutting stress of singulation separating step to cause internal wiring distortion or displacement in this substrate strip 210.
Particularly; Shown in Fig. 3 E; Because the width of these Cutting Roads 214 should be less than the width of these cutting grooves 215; The gap width S that removes when this first encapsulating material 230 and 240 cuttings of this second encapsulating material can be same as the width W 2 (shown in Fig. 3 G and Fig. 3 H) of these Cutting Roads 214; In the singulation separating step, just can guarantee can not switch to the both sides (being the periphery 216 of base board unit) of these cutting grooves 215, thus each independently in the semiconductor packaging structure this second encapsulating material 240 still can cover the periphery 216 of these base board units 213, metallic circuit and the core layer that can avoid being positioned at these base board units 213 peripheries 216 expose; And then make encapsulating products reach anti-oxidant, moisture-resistant gas and resist the effect of other environmental injury, to promote the durability of semiconductor package product.
Second specific embodiment of the present invention discloses the another kind of mould envelope array processing method that prevents that substrate periphery from exposing, the schematic cross-section of marginal data element in each step of Fig. 5 A to Fig. 5 H.Wherein want element to indicate with same-sign with the primary and secondary of the first embodiment identical function, thin portion no longer gives unnecessary details.
At first, like Fig. 5 A and shown in Figure 6, substrate strip 210 is provided.In the present embodiment, except the internal wiring structure, this substrate strip 210 can more comprise two above leads 319.These leads 319 can be the extension of these substrate strip 210 interior metal circuit layers or by outer additional unsettled lead (lead); Being generally the surface has the copper cash of electrodeposited coating; The metal forming of etching Copper Foil capable of using etc. or conductive foil form through electroplating again, so have flexibility.Before not electrically connecting, these leads 319 can be through these above-mentioned central slotted eyes 217 for soaring.
Then, shown in Fig. 5 B, two above chips 220 are set on these base board units 213, and these electrodes 222 of these chips 220 are emerging in this central authorities' slotted eye 217.Afterwards, shown in Fig. 5 C, electrically connect these chips 220 and these base board units 213, it is engaged to the electrode 222 of these chips 220 through these central slotted eyes 217 with these leads 319 of this substrate strip 210.Pin tool for stitching (ILB bonding head) interrupts prejudging a little of these leads 319 and makes these lead 319 pressings contact the electrode 222 to these chips 220 in capable of using, and reaches the electric connection of signal communicating with these chips 220.Engage the mode that electrically connects compared to routing, utilize the electric connection mode of lead 319 pressings contact, do not have bank so that signal path is able to shorten, and do not have the metal solder interface at bonding wire two ends, can be applicable to the high-frequency integrated circuit encapsulation.
Afterwards, shown in Fig. 5 D, this upper surface 211 moulds envelope formation first encapsulating material 230 in this substrate strip 210 to cover these base board units 213 and these Cutting Roads 214 continuously, more can cover these chips 220, makes it not receive the pollution of environmental contaminants.
Afterwards; Like Fig. 5 E and shown in Figure 7; Precut step, it forms on these Cutting Roads 214 and runs through the cutting groove 215 of this substrate strip 210 more than two, but does not run through this first encapsulating material 230; The width W 1 of each cutting groove 215 is greater than the width W 2 of corresponding Cutting Road 214, so that these base board units 213 have the periphery 216 that is emerging in outside these Cutting Roads 214.Particularly; As shown in Figure 7; These cutting grooves 215 be along Cutting Road 214 vertically or (with) horizontal linear array; But the width of cutting groove 215 is answered the width W 2 of W1 greater than corresponding Cutting Road 214, so that these peripheries of these base board units 213 216 are not positioned on these Cutting Roads 214, but has bigger opening.In the present embodiment, shown in Fig. 5 E, the degree of depth of these cutting grooves 215 can be identical with the thickness of this substrate strip 210, can not need cut to this first encapsulating material 230.The cross sectional shape of these cutting grooves 215 can be rectangle.In addition, as shown in Figure 7, preferably, in described precut step, these central slotted eyes 217 can be by the grooves 318 of this lower surface 212 that is formed on this substrate strip 210 and are communicated with these cutting grooves 215.These grooves 318 do not run through this substrate strip 210, and its depth of cut can be less than these cutting grooves 215.
Afterwards, shown in Fig. 5 E and Fig. 5 F, in these cutting grooves 215, form second encapsulating material 240, with the periphery 216 that coats these base board units 213.In this step; In first encapsulating material 230 is not inserted these central slotted eyes 217; This second encapsulating material 240 can more be formed in these central slotted eyes 217; The groove 318 that is communicated with these cutting grooves 215 preferably capable of using is guided to this second encapsulating material 240 in these central slotted eyes 217, so these grooves 318 also can be covered with this second encapsulating material 240, to seal these leads 319.In a concrete structure, the packed height of this second encapsulating material 240 can be no more than this lower surface 212 of this substrate strip 210.
Afterwards, shown in Fig. 5 G, after forming the step of this second encapsulating material 240 with the singulation separating step before, can form two soldered balls 260 at the lower surface 212 of this substrate strip 210, be engaged to the printed circuit board (PCB) of outside for outer surface.
At last; Shown in Fig. 5 G and Fig. 5 H; Remove at this first encapsulating material 230 and second encapsulating material 240 in these Cutting Roads 214 on these Cutting Roads 214 with cutting mode; Separate the semiconductor packaging structure 300 of these base board units 213 with singulation, and the periphery 216 of these base board units 213 is coated by this second encapsulating material 240 still after cutting for separating separately.Therefore, the present invention can avoid metallic circuit and the core layer of base board unit periphery to expose in mould envelope ARRAY PROCESSING, and then makes encapsulating products reach anti-oxidant, moisture-resistant gas and resist the effect of other environmental injury, with the durability of lifting semiconductor package product.
The above only is preferred embodiment of the present invention, is not the present invention is done any pro forma restriction; Though the present invention discloses as above with preferred embodiment; Yet be not that any people who is familiar with this technology is not in breaking away from technical scope of the present invention in order to qualification the present invention; Any simple modification of being done, equivalence change and modify, and all are covered by in the technical scope of the present invention.
Claims (10)
1. a mould that prevents that substrate periphery from exposing seals array processing method, it is characterized in that it comprises:
One substrate strip is provided, and this substrate strip has upper surface and opposing lower surface, and this substrate strip includes two above substrate unit, and the size of each base board unit is formed with Cutting Road corresponding to the semiconductor packaging structure between the adjacent substrate unit;
Two above chips are set on these base board units;
Said chip is electrically connected to pairing base board unit;
Upper surface mould envelope in said substrate strip forms first encapsulating material, to cover these base board units and these Cutting Roads continuously;
Precut step; On these Cutting Roads, form two cutting grooves that run through this substrate strip at least; But do not run through this first encapsulating material, the width of each cutting groove is greater than the width of corresponding Cutting Road, so that these base board units have the periphery that is emerging in outside these Cutting Roads;
In said cutting groove, form second encapsulating material, to coat the periphery of these base board units; And
The singulation separating step; Remove at said first encapsulating material on these Cutting Roads and second encapsulating material in these Cutting Roads with cutting mode; So that these base board unit singulation are separated into independently semiconductor packaging structure, and the periphery of these base board units is still coated by said second encapsulating material after cutting.
2. the mould envelope array processing method that prevents that substrate periphery from exposing according to claim 1; It is characterized in that; Said substrate strip is formed with central slotted eye in addition in each base board unit; In the step of chip was set, the active surface of these chips was pasted to said substrate strip, and the electrode exposition of said chip is in this central authorities' slotted eye.
3. the mould envelope array processing method that prevents that substrate periphery from exposing according to claim 2 is characterized in that in the step that forms said second encapsulating material, said second encapsulating material more is formed in the said central slotted eye.
4. the mould envelope array processing method that prevents that substrate periphery from exposing according to claim 3 is characterized in that, in said precut step, said central slotted eye is communicated with said cutting groove by the groove of the lower surface that is formed on said substrate strip.
5. the mould envelope array processing method that prevents that substrate periphery from exposing according to claim 2 is characterized in that form in the step of said first encapsulating material in the mould envelope, said first encapsulating material more is formed in the said central slotted eye.
6. according to claim 2,3, the 4 or 5 described mould envelope array processing methods that prevent that substrate periphery from exposing; It is characterized in that; The said step that chip is electrically connected to pairing base board unit comprises with the routing mode and forms two above bonding wires, and these bonding wires are connected to these base board units via these central slotted eyes with these chips.
7. according to claim 2,3, the 4 or 5 described mould envelope array processing methods that prevent that substrate periphery from exposing; It is characterized in that the said step that chip is electrically connected to pairing base board unit comprises the electrode that is engaged to these chips with two above leads of said substrate strip through these central slotted eyes.
8. according to claim 1,2,3, the 4 or 5 described mould envelope array processing methods that prevent that substrate periphery from exposing; It is characterized in that; With before said singulation separating step, the step that other comprises is after the step of said formation second encapsulating material: the lower surface in said substrate strip forms two above soldered balls.
9. according to claim 1,2,3, the 4 or 5 described mould envelope array processing methods that prevent that substrate periphery from exposing, it is characterized in that said first encapsulating material and second encapsulating material cut the width that the gap width that removes is same as these Cutting Roads.
10. according to claim 1,2,3, the 4 or 5 described mould envelope array processing methods that prevent that substrate periphery from exposing; It is characterized in that; After the step of said formation second encapsulating material with before said singulation separating step; The step that other comprises is: carry out the back baking procedure, to solidify said first encapsulating material and second encapsulating material.
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| CN2011100751416A CN102709198A (en) | 2011-03-28 | 2011-03-28 | Mold array process method for preventing periphery of substrate from being exposed |
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Cited By (1)
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| TWI823452B (en) * | 2022-06-30 | 2023-11-21 | 頎邦科技股份有限公司 | Semiconductor package and circuit board thereof |
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| US20090166891A1 (en) * | 2007-12-28 | 2009-07-02 | Walton Advanced Engineering Inc. | Cutting and molding in small windows to fabricate semiconductor packages |
| US20100219521A1 (en) * | 2009-02-27 | 2010-09-02 | Kuo-Yuan Lee | Window type semiconductor package |
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| CN1337065A (en) * | 1999-11-11 | 2002-02-20 | 卡西欧计算机株式会社 | Semiconductor device and method of mfg. the same |
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| US20090166891A1 (en) * | 2007-12-28 | 2009-07-02 | Walton Advanced Engineering Inc. | Cutting and molding in small windows to fabricate semiconductor packages |
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