CN102709158A - Method of improving warpage of silicon epitaxial wafer - Google Patents
Method of improving warpage of silicon epitaxial wafer Download PDFInfo
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- CN102709158A CN102709158A CN2012102029490A CN201210202949A CN102709158A CN 102709158 A CN102709158 A CN 102709158A CN 2012102029490 A CN2012102029490 A CN 2012102029490A CN 201210202949 A CN201210202949 A CN 201210202949A CN 102709158 A CN102709158 A CN 102709158A
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Abstract
The invention discloses a method of improving the warpage of a silicon epitaxial wafer, belonging to the technical field of a silicon epitaxial wafer. The method comprises the following steps of: (1) preparation of the silicon epitaxial wafer: preparing a new silicon epitaxial wafer or taking a silicon epitaxial wafer to be repaired; and (2) annealing: placing the prepared silicon epitaxial wafer into a reaction chamber, and keeping the temperature of 650-1050 DEG C for 10-30min; and cooling for 10-15min to the temperature less than or equal to 300 DEG C, and taking the silicon epitaxial wafer out of the reaction chamber. By adopting the method, the silicon epitaxial wafer with unacceptable warpage (WARP) can be annealed to be qualified. Moreover, the method is compatible with an extension process, the warpage of the silicon epitaxial wafer can be improved effectively, the accuracy and the passing rate of finished products can be increased greatly, waste can be changed into valuable objects, the cost is low, and the efficiency is high.
Description
Technical field
The present invention relates to the silicon epitaxial wafer technical field, relate in particular to a kind of method of improving the silicon epitaxial wafer angularity.
Technical field
The present invention relates to the silicon epitaxial wafer technical field, relate in particular to a kind of method of improving the silicon epitaxial wafer angularity.
Background technology
Silicon epitaxial wafer is a kind of semi-conducting material that is widely used in various semiconductor device and integrated circuit, is widely used in the products such as wind energy, solar energy, automobile, mobile phone, household electrical appliances.
The angularity of silicon epitaxial wafer (WARP) mainly is in high-temperature technology; The thermal stress that forms in the silicon epitaxial wafer makes silicon chip generation plastic deformation. in the automation equipment of very lagre scale integrated circuit (VLSIC) (VLSI) micron and sub-micron live width; Warpage has a strong impact on the accuracy of photoetching, even photoetching can't be carried out.Reduce the silicon warp degree and just mean and can further reduce live width, improve integrated level. improve circuit performance.
The method of control silicon epitaxial wafer angularity mainly is to realize that through the angularity (WARP) of controlling and screening backing material the shortcoming of this method is at present: the rate of finished products that 1) greatly reduces backing material; 2) backing material that has the polysilicon back of the body to seal to the back side, the angularity of substrate (WARP) numerical value and the size of delaying outward are not corresponding, and therefore this screening technique can not effectively be controlled the outer angularity of delaying (WARP); 3) externally delay because defective can't the doing over again or repair that angularity (WARP) causes.
Background technology
Silicon epitaxial wafer is a kind of semi-conducting material that is widely used in various semiconductor device and integrated circuit, is widely used in the products such as wind energy, solar energy, automobile, mobile phone, household electrical appliances.
The angularity of silicon epitaxial wafer (WARP) mainly is in high-temperature technology; The thermal stress that forms in the silicon epitaxial wafer makes silicon chip generation plastic deformation. in the automation equipment of very lagre scale integrated circuit (VLSIC) (VLSI) micron and sub-micron live width; Warpage has a strong impact on the accuracy of photoetching, even photoetching can't be carried out.Reduce the silicon warp degree and just mean and can further reduce live width, improve integrated level. improve circuit performance.
The method of control silicon epitaxial wafer angularity mainly is to realize that through the angularity (WARP) of controlling and screening backing material the shortcoming of this method is at present: the rate of finished products that 1) greatly reduces backing material; 2) backing material that has the polysilicon back of the body to seal to the back side, the angularity of substrate (WARP) numerical value and the size of delaying outward are not corresponding, and therefore this screening technique can not effectively be controlled the outer angularity of delaying (WARP); 3) externally delay because defective can't the doing over again or repair that angularity (WARP) causes.
Summary of the invention
The present invention provides a kind of method of improving the silicon epitaxial wafer angularity; Can make the underproof silicon epitaxial wafer of angularity (WARP) carry out becoming qualified product after the annealing in process, and can be compatible with epitaxy technique, the angularity of silicon epitaxial wafer effectively improved; The precision and the qualification rate of finished product have been improved greatly; Can turn waste into wealth, cost is low, and efficient is high.
The technical scheme that the present invention taked is:
A kind of method of improving the silicon epitaxial wafer angularity comprises the steps:
(1) prepared silicon epitaxial wafer: produce new silicon epitaxial wafer or get the silicon epitaxial wafer that needs reparation;
(2) annealing: the silicon epitaxial wafer of preparing is put into reative cell, at the 650-1050 ℃ of 10-30min that anneals down; Be cooled in 10-15 minute≤300 ℃, silicon epitaxial wafer is taken out reative cell.
The preparation method of the new silicon epitaxial wafer described in the step (1) is: with the silicon substrate film reative cell of packing into, be warming up to 900 ℃ with 10-15 minute, rose to 1020-1050 ℃, and carried out epitaxial growth in 8-12 minute.
Annealing temperature is 850-950 ℃ in the step (2).
The silicon epitaxial wafer of the need reparation described in the step (1) is the silicon epitaxial wafer of angularity greater than silicon epitaxial wafer thickness 1%.
High annealing is after workpiece is heated to uniform temperature and certain time, to make slow cooling, can eliminate the residual stress of material, and stable dimensions reduce distortion, so high annealing can be improved angularity to a certain extent.
Standard difference according to customer requirement confirms whether the angularity of silicon epitaxial wafers is qualified, generally requires angularity to be not more than silicon epitaxial wafer thickness 1%.
Adopt the beneficial effect that technique scheme produced to be:
1. can make the underproof silicon epitaxial wafer of angularity (WARP) carry out becoming qualified product after the annealing in process, can turn waste into wealth.
2. method of the present invention can be compatible with epitaxy technique, effectively improves the angularity of silicon epitaxial wafer, improved the precision and the qualification rate of finished product greatly, and cost is low, and efficient is high.
Summary of the invention
The present invention provides a kind of method of improving the silicon epitaxial wafer angularity; Can make the underproof silicon epitaxial wafer of angularity (WARP) carry out becoming qualified product after the annealing in process, and can be compatible with epitaxy technique, the angularity of silicon epitaxial wafer effectively improved; The precision and the qualification rate of finished product have been improved greatly; Can turn waste into wealth, cost is low, and efficient is high.
The technical scheme that the present invention taked is:
A kind of method of improving the silicon epitaxial wafer angularity comprises the steps:
(1) prepared silicon epitaxial wafer: produce new silicon epitaxial wafer or get the silicon epitaxial wafer that needs reparation;
(2) annealing: the silicon epitaxial wafer of preparing is put into reative cell, at the 650-1050 ℃ of 10-30min that anneals down; Be cooled in 10-15 minute≤300 ℃, silicon epitaxial wafer is taken out reative cell.
The preparation method of the new silicon epitaxial wafer described in the step (1) is: with the silicon substrate film reative cell of packing into, be warming up to 900 ℃ with 10-15 minute, rose to 1020-1050 ℃, and carried out epitaxial growth in 8-12 minute.
Annealing temperature is 850-950 ℃ in the step (2).
The silicon epitaxial wafer of the need reparation described in the step (1) is the silicon epitaxial wafer of angularity greater than silicon epitaxial wafer thickness 1%.
High annealing is after workpiece is heated to uniform temperature and certain time, to make slow cooling, can eliminate the residual stress of material, and stable dimensions reduce distortion, so high annealing can be improved angularity to a certain extent.
Standard difference according to customer requirement confirms whether the angularity of silicon epitaxial wafers is qualified, generally requires angularity to be not more than silicon epitaxial wafer thickness 1%.
Adopt the beneficial effect that technique scheme produced to be:
1. can make the underproof silicon epitaxial wafer of angularity (WARP) carry out becoming qualified product after the annealing in process, can turn waste into wealth.
2. method of the present invention can be compatible with epitaxy technique, effectively improves the angularity of silicon epitaxial wafer, improved the precision and the qualification rate of finished product greatly, and cost is low, and efficient is high.
Embodiment
Used silicon epitaxy equipment is PE3061D in following examples, and substrate is 8 inch 625 micron thick, polysilicon back of the body envelope, and epitaxial loayer 100-150 micron, BF representes the angularity of optimum face, 3P representes 3 angularity.
Embodiment 1
(1) gets the silicon epitaxial wafer that needs reparation;
(2) silicon epitaxial wafer of preparing is put into reative cell, be incubated 10min down at 650 ℃; With 10min be cooled to≤300 ℃, silicon epitaxial wafer is taken out reative cell.Angularity is improved situation such as table 1:
Table 1
Embodiment 2
(1) gets the silicon epitaxial wafer that needs reparation;
(2) annealing: the silicon epitaxial wafer of preparing is put into reative cell, be incubated 15min down at 850 ℃; With 12min be cooled to≤300 ℃, silicon epitaxial wafer is taken out reative cell.Angularity is improved situation such as table 2:
Table 2
Embodiment 3
(1) with the silicon substrate film reative cell of packing into, be warming up to 900 ℃ with 10 minutes, rose to 1050 ℃ in 12 minutes, carry out epitaxial growth, obtain silicon epitaxial wafer;
(2) annealing: silicon epitaxial wafer is stayed reative cell, is incubated 20min down at 1050 ℃; With 15min be cooled to≤300 ℃, silicon epitaxial wafer is taken out reative cell.Angularity is improved situation such as table 3:
Table 3
Embodiment 4
(1) with the silicon substrate film reative cell of packing into, be warming up to 900 ℃ with 15 minutes, rose to 1020 ℃ in 8 minutes, carry out epitaxial growth, obtain silicon epitaxial wafer;
(2) annealing: silicon epitaxial wafer is stayed reative cell, is incubated 30min down at 950 ℃; With 14min be cooled to≤300 ℃, silicon epitaxial wafer is taken out reative cell.Angularity is improved situation such as table 4:
Table 4
Claims (4)
1. a method of improving the silicon epitaxial wafer angularity is characterized in that comprising the steps:
(1) prepared silicon epitaxial wafer: produce new silicon epitaxial wafer or get the silicon epitaxial wafer that needs reparation;
(2) annealing: the silicon epitaxial wafer of preparing is put into reative cell, at the 650-1050 ℃ of 10-30min that anneals down; Be cooled in 10-15 minute≤300 ℃, silicon epitaxial wafer is taken out reative cell.
2. a kind of method of improving the silicon epitaxial wafer angularity according to claim 1; The preparation method that it is characterized in that the new silicon epitaxial wafer described in the step (1) is: with the silicon substrate film reative cell of packing into; Be warming up to 900 ℃ with 10-15 minute; Rise to 1020-1050 ℃ in 8-12 minute, carry out epitaxial growth.
3. a kind of method of improving the silicon epitaxial wafer angularity according to claim 1 is characterized in that annealing temperature is 850-950 ℃ in the step (2).
4. a kind of method of improving the silicon epitaxial wafer angularity according to claim 1, the silicon epitaxial wafer that it is characterized in that the need reparation described in the step (1) are the silicon epitaxial wafer of angularity greater than silicon epitaxial wafer thickness 1%.
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| CN2012102029490A CN102709158A (en) | 2012-06-19 | 2012-06-19 | Method of improving warpage of silicon epitaxial wafer |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105448654A (en) * | 2014-09-02 | 2016-03-30 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of semiconductor structure |
| CN110620040A (en) * | 2019-09-12 | 2019-12-27 | 长江存储科技有限责任公司 | Method for improving process stability in production |
| CN111681945A (en) * | 2020-05-11 | 2020-09-18 | 中环领先半导体材料有限公司 | Process for improving geometric parameters of large-diameter semiconductor silicon wafer by polycrystalline back seal |
Citations (4)
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| US20020094663A1 (en) * | 2001-01-18 | 2002-07-18 | Yong-Bum Kwon | Method of manufacturing an SOI (silicon on insulator ) wafer |
| CN1828970A (en) * | 2001-02-28 | 2006-09-06 | 株式会社半导体能源研究所 | Method of manufacturing semiconductor device |
| CN101165225A (en) * | 2007-08-28 | 2008-04-23 | 河北普兴电子科技股份有限公司 | IC sheet epitaxy technique |
| CN101183697A (en) * | 2007-12-10 | 2008-05-21 | 厦门大学 | Gallium nitride based LED epitaxial slice structure and method for preparing the same |
-
2012
- 2012-06-19 CN CN2012102029490A patent/CN102709158A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020094663A1 (en) * | 2001-01-18 | 2002-07-18 | Yong-Bum Kwon | Method of manufacturing an SOI (silicon on insulator ) wafer |
| CN1828970A (en) * | 2001-02-28 | 2006-09-06 | 株式会社半导体能源研究所 | Method of manufacturing semiconductor device |
| CN101165225A (en) * | 2007-08-28 | 2008-04-23 | 河北普兴电子科技股份有限公司 | IC sheet epitaxy technique |
| CN101183697A (en) * | 2007-12-10 | 2008-05-21 | 厦门大学 | Gallium nitride based LED epitaxial slice structure and method for preparing the same |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105448654A (en) * | 2014-09-02 | 2016-03-30 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of semiconductor structure |
| CN110620040A (en) * | 2019-09-12 | 2019-12-27 | 长江存储科技有限责任公司 | Method for improving process stability in production |
| CN111681945A (en) * | 2020-05-11 | 2020-09-18 | 中环领先半导体材料有限公司 | Process for improving geometric parameters of large-diameter semiconductor silicon wafer by polycrystalline back seal |
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Application publication date: 20121003 |