CN102708912B - For the page buffer architecture of program erase reading nanoscale resistive memory devices - Google Patents
For the page buffer architecture of program erase reading nanoscale resistive memory devices Download PDFInfo
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- 230000005055 memory storage Effects 0.000 claims abstract description 118
- 230000008859 change Effects 0.000 claims abstract description 10
- 238000000034 method Methods 0.000 claims description 21
- 238000010276 construction Methods 0.000 claims description 20
- 101150110009 SCN11A gene Proteins 0.000 description 7
- 102100033974 Sodium channel protein type 11 subunit alpha Human genes 0.000 description 7
- 238000012795 verification Methods 0.000 description 7
- 238000004891 communication Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- JPVYNHNXODAKFH-UHFFFAOYSA-N Cu2+ Chemical compound [Cu+2] JPVYNHNXODAKFH-UHFFFAOYSA-N 0.000 description 2
- 229910001431 copper ion Inorganic materials 0.000 description 2
- OMZSGWSJDCOLKM-UHFFFAOYSA-N copper(II) sulfide Chemical compound [S-2].[Cu+2] OMZSGWSJDCOLKM-UHFFFAOYSA-N 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 230000000717 retained effect Effects 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- QPLDLSVMHZLSFG-UHFFFAOYSA-N Copper oxide Chemical compound [Cu]=O QPLDLSVMHZLSFG-UHFFFAOYSA-N 0.000 description 1
- 239000005751 Copper oxide Substances 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 229910000431 copper oxide Inorganic materials 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0064—Verifying circuits or methods
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0069—Writing or programming circuits or methods
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0097—Erasing, e.g. resetting, circuits or methods
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
- G11C7/106—Data output latches
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
- G11C7/1069—I/O lines read out arrangements
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
- G11C7/1096—Write circuits, e.g. I/O line write drivers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0069—Writing or programming circuits or methods
- G11C2013/0076—Write operation performed depending on read result
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0069—Writing or programming circuits or methods
- G11C2013/0085—Write a page or sector of information simultaneously, e.g. a complete row or word line
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/22—Control and timing of internal memory operations
- G11C2207/2245—Memory devices with an internal cache buffer
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- Engineering & Computer Science (AREA)
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- Nanotechnology (AREA)
- Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Theoretical Computer Science (AREA)
- Crystallography & Structural Chemistry (AREA)
- Read Only Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
The invention discloses a kind of page buffer architecture for program erase reading nanoscale resistive memory devices, based on single order, there is provided high electric current in programming and erase feature, only to programme and to wipe this memory storage (30) that its state will change from its original state.
Description
The application is application number is 200680015533.0, and the applying date is on May 26th, 2006, and denomination of invention is the divisional application of the Chinese patent application of " for programming, wiping and the page buffer architecture of reading nanoscale resistive memory devices ".
Technical field
The present invention is about memory storage substantially, in detail, is operate about resistive memory devices.
Background technology
Fig. 1 shows the resistive memory devices 30 that one is known as ion motion resistive memory storage.Memory storage 30 comprises electrode 32 (such as copper), the copper sulfide layer 34 on this electrode 32, the active layer 36 of the such as copper oxide on layer 34 and the electrode 38 (such as titanium) on this active layer 36.Originally, suppose that memory storage 30 is not yet programmed, in order to program storage 30, by electrode 38 ground connection, and apply positive electricity and be pressed onto electrode 32, in order to do making current potential V
pg(" programming " current potential) applies cross-over connection (across) in memory storage 30 (referring to Fig. 2, memory storage electric current is to applying the figure being connected across the current potential of this memory storage 30) in forward (forward) direction of this memory storage 30 from higher to comparatively electronegative potential.This current potential enough causes copper ion be attracted towards electrode 38 from layer 34 and enter active layer 36 (A), to form conductive filament (filament), active layer 36 (and whole memory storage 30) is caused to be in (forward) low resistance or conduction state.After removing this current potential (B), the ion being attracted into active layer 36 during programming step is retained in this active layer 36, is held in conduction or low resistance state to make active layer 36 (with memory storage 30).
Be programmed in the read step of (conduction) state in memory storage 30 in it, current potential V
r(" reading " current potential) applies to be connected across memory storage 30 to comparatively electronegative potential in the forward direction of this memory storage 30 from higher.This current potential is less than applying and is connected across this memory storage 30 and is used for the current potential V of (referring to above-mentioned) of programming
pg.In this situation, memory storage 30 is by easy On current, and it represents that memory storage 30 is programmed state at it.
In order to wipe memory storage, applying positive electricity and being pressed onto electrode 38, and making electrode 32 keep ground connection, in order to do making current potential V
er(" erasing " current potential) applies to be connected across memory storage 30 to comparatively electronegative potential in oppositely (reverse) direction of this memory storage 30 from higher.This current potential enough causes copper ion be ostracised towards electrode 32 from active layer 36 and enter layer 34 (C), causes active layer 36 (and whole memory storage 30) at high resistance or essence non-conductive state.This state still maintains upon removal of such potential from the memory device 30.
Be wiped free of in the read step of (essence is non-conductive) state in memory storage 30 in it, current potential V
rforward direction again in this memory storage 30 applies to be connected across memory storage 30 from higher to comparatively electronegative potential, as mentioned above.Because active layer 34 (with memory storage 30) is in high resistance or the non-conductive state of essence, not conduct significant current incited somebody to action by memory storage 30, and it represents that memory storage 30 is wiped free of state at it.Resistance memory array generally comprises these a large amount of memory storages 30, and each memory storage 30 individually can be read, programmes and wipe.
To notice from above-mentioned and Fig. 2, and need relatively low electric current to carry out the state (wishing to apply low-voltage to avoid interference another state) of read storage device 30, and the electric current needing essence higher be programmed and erasing apparatus 30.Thus, the framework showing this kind high electric current is needed.
In addition, generally speaking, in existing flash array, be carry out two command method (two-commandapproach), wherein wipe the data of whole page based on the first order, then write data in array based on the second order.Can desirable to provide a kind of method, wherein based on single order, only wherein need to carry out wiping and programming from original state to the memory storage changing state in those, that is the memory storage that its state of energy will not change from original state is retained in this state and does not experience erasing or programming operation.
Therefore, required be a kind of in programme and the memory storage of erasing resistive memory devices time meet high current needs, use single order and only change the method for those wherein states of the memory storage of needs change state simultaneously.
Summary of the invention
One aspect of the present invention provides a kind of method to resistive memory devices executive routine, comprising: provide data message to data register; Data message from this data register is provided to latch, and wherein, this series of latches is in this data register; And by from this latch to data are write information relevant in this memory storage and are provided to write driver.
The present invention provides a kind of memory construction on the other hand, comprising: bit line; Be connected to the resistive memory devices of this bit line; Data register; For connecting the device of this bit line and this data register; Latch, is series at this data register; For connecting the device of this bit line and this latch; And for connecting the device of this data register and this latch.
Broadly, the present invention is a kind of method that resistive memory devices in resistive memory devices array carries out operating, this array is contained in the memory storage of different conditions, the method comprises: the expectation state judging each memory storage, judge the state of each memory storage, and only write data are different from expectation state memory storage to those states.
According to considering following detailed description, coordinating institute's accompanying drawings, preferably can understand the present invention.By following description, only by the explanation implementing optimal mode of the present invention, show and describe embodiments of the invention, will become for those who are familiar with this art and easily have a clear understanding of the present invention.As will be understood, the present invention can have other embodiment, and its some thin portions can do to modify and obvious each aspect changes, and does not depart from scope of the present invention completely.Therefore, each graphic be You Guan in itself the present invention be described and be not used for limiting the present invention with detailed description.
Accompanying drawing explanation
The novel feature of believed characteristic of the present invention is proposed in appended claims.But the best Implementation Modes of the present invention itself and this use when read, and its further object and advantage, will coordinate institute's accompanying drawings by the detailed description with reference to following illustrative embodiments and understand best, wherein:
Fig. 1 is the sectional view of above-mentioned memory storage;
Fig. 2 is the figure of the current vs voltage of the operating characteristic of the memory storage of key diagram 1;
Fig. 3 is the general remark of the circuit for implementing the present invention;
Fig. 4 is for illustrating the process flow diagram of step in this method; And
Fig. 5 to 15 is the circuit detailed maps of key diagram 3, for implementing the present invention together with the step of the method.
Primary clustering symbol description
30 resistive memory devices 30A memory storages
30
1, 30
2, 30
3, 30
4memory storage
32 electrode 34 copper sulfide layers
36 active layer 38 electrodes
40 page of 42 memory array
46 section 48 memory constructions
48
1, 48
2, 48
3, 48
4memory construction
50 circuit 52 drivers
54 logic 56 I/O ports
58 bit lines 60,62y decoder transistor
62
1, 62
2, 62
3, 62
4y decoder transistor
64 transistor 66 data registers
66
1, 66
2, 66
3, 66
4data register
68 sense latch 70,72,74 transistors, switch
72
1, 72
2, 72
3, 72
4transistor
80 sensing circuit 82,84,86,88,90 transistors
A, A1, A2, A3, A4 Node B, B1, B2, B3, B4 node
BL1, BL2, BL3, BL4 node C, C1, C2, C3, C4 node
SNS1, SNS2, SNS3, SNS4 node
Ver, Vpg, Vr current potential.
Embodiment
Now in detail with reference to the specific embodiment of the present invention, this embodiment illustrates the optimal mode being implemented performance that the present invention considers by inventor.
Fig. 3 illustrates the general type of the circuit for implementing the present invention.Show the part of the page 40 of memory array 42.The page 40 of memory array 42 comprises multiple memory construction 48.Circuit 50 (comprising write driver 52, circuit logic 54 and I/O port 56) will be operation associated with page 40 in the mode of following description.
Each memory construction 48 comprises bit line 58, and this bit line 58 can be connected to circuit 50 via y decoder transistor 60 and y decoder transistor 62.Each bit line 58 is connected to multiple memory storage 30 along its length, and each memory storage 30 is connected in series with access transistor 64.But in order to clear object, only show single memory storage 30 for be operatively connected to each bit line 58.Each memory construction 48 also comprises the data register 66 of connect with sense latch (senselatch) 68 (being connected by the transistor 70 being shown as switch (switch)), this data register 66 and sense latch 68 are connected in parallel with bit line 58, be connect bit line 58 and sense latch 68 with the transistor 72 being shown as switch, and the transistor 74 being shown as switch connect this bit line 58 and data register 66.
With reference to the wherein one of the memory construction 48 of Fig. 3, as centre memory construction 48 in this example, and the operation of circuit is described, although should recognize that respectively other memory construction 48 is operate in a similar manner.
At first, as mentioned above, memory storage 30 can be in high resistance (programming " 1 ") state or in low resistance (programming " 0 ") state.Also with reference to figure 4, the switch 70,72 not conducting (open) due to switch 74 conducting (closed), data are loaded on data register 66 from I/O port 56 via y decoder transistor 62 in the mode of byte.The expectation state of these data instruction memory storage 30A.Then switch 70 is switched on, and the data in data register 66 pour into (dumped) (whole page) to sense latch 68.Then, carry out erase verification step, in fact (ineffect) compares the data in sense latch 68 and the data in memory storage 30, to determine whether the erase step (whole page) needing to carry out memory storage 30.That is, such as, if memory storage 30 is being wiped free of state (logical one), and the expectation state of memory storage 30 is wiped free of state (logical one), then do not need and will not carry out erase step to memory storage 30.Similarly, if memory storage 30 is being programmed state (logical zero), and the expectation state of memory storage 30 is programmed state (logical zero), then will not carry out erase step.If memory storage 30 is being wiped free of state (logical one), and the expectation state of memory storage 30 is programmed state (logical zero), then will not carry out erase step (will carry out programming step, and will discuss after a while).Finally, if memory storage 30 is being programmed state (logical zero), and the expectation state of memory storage 30 is wiped free of state (logical one), then will carry out erase step.Switch 70, the 74 not conducting due to switch 72 conducting, the information of carrying out erase step about needs is provided to logic 54 from sense latch 68 via switch 72 with via y decoder transistor 62 and y decoder transistor 60, this logic 54 provides information to write driver 52 according to the state of sense latch 68, passes through in the memory storage 30 (vide supra) of desired situation to provide erasing electric current.Then, another erase verification step is carried out through memory storage 30 and the communication (communication) of sense latch 68, and whether the state representation of sense latch 68 has successfully carried out erase step.If erase step is desired and this erase verification step has represented and not yet reaches the state of being wiped free of, then repeat this erase step and carry out other erase verification step, until erase verification has represented erase step effectively.
Secondly, carry out program verification step, compare the data in sense latch 68 and the data in memory storage 30, to determine whether the programming step needing to carry out memory storage 30.That is, such as, if memory storage 30 is being wiped free of state (logical one), and the expectation state of memory storage 30 is wiped free of state (logical one), then do not need and will not carry out programming step to memory storage 30.Similarly, if memory storage 30 is being programmed state (logical zero), and the expectation state of memory storage 30 is programmed state (logical zero), then will not carry out programming step.If memory storage 30 is being wiped free of state (logical one), and the expectation state of memory storage 30 is programmed state (logical zero), then will carry out programming step.Finally, if memory storage 30 is being programmed state (logical zero), and the expectation state of memory storage 30 is wiped free of state (logical one), then will not carry out programming step.The information of carrying out programming step about needs is provided to logic 54 from sense latch 68 via switch 72 with via y decoder transistor 62 and y decoder transistor 60, this logic 54 provides information to write driver 52 according to the state of sense latch 68, the memory storage 30 (vide supra) passing through in desired situation to provide program current.Then, another program verification step is carried out through memory storage 30 and the communication of sense latch 68, and whether the state representation of sense latch 68 has successfully carried out programming step.If programming step is desired and this program verification step has represented and not yet reaches the state of being programmed, then repeat this programming step and carry out another program verification step, until program verification has represented programming step effectively.
Fig. 5 to 15 describes the circuit of Fig. 3 in detail.As shown in the figure, four memory constructions 48 are shown
1, 48
2, 48
3, 48
4although, will recognize and have these memory constructions of very big figure to be included in section 46.Each memory construction 48 comprises data register 66, sense latch 68 and transistor 70,72,74, entirely as mentioned above.In each memory construction 48, sensing circuit 80, comprises the transistor 82,84,86,88 of series connection, through transistor 90 with bit line 58 communication associated, and with sense latch 68 communication associated, as shown in the figure.
In this example, in order to this method is described, memory storage 30
1, 30
2, 30
3, 30
4be shown as respectively in low resistance (0), low resistance (0), high resistance (1), high resistance (1) state at first.Meanwhile, the expectation state of memory storage will be low resistance (0), high resistance (1), low resistance (0), high resistance (1) respectively.At first, because LDPB is high and because DUMP is low and RDPB is low, data bit (0101) is continuously via y decoder transistor 60 and Y decoder transistor 62
1, 62
2, 62
3, 62
4be provided to other data register 66
1, 66
2, 66
3, 66
4, to make data register 66
1, 66
2, 66
3, 66
4node C1, C2, C3, C4 system respectively at 0101 state (Fig. 5).Then (Fig. 6), make being input as high (DUMP is high) to transistor 70 simultaneously, with the sense latch making the information in each node C be provided to association, make the state of the node A of sense latch identical with the state of the node C of the data register associated.That is, node A1, A2, A3, A4 is respectively in 0101 state.Meanwhile, each Node B of sense latch will be the state at the node A in contrast to association, that is Node B 1, B2, B3, B4 will respectively in 1010 states.
Then, with reference to Fig. 7, carry out erase verification step, wherein BLPROT is low, SET be low and RDPB, DUMP and LDPB all for low.Due to y decoder transistor 62
1, 62
2, 62
3, 62
4conducting, drives and reads electric current by each memory storage 30
1, 30
2, 30
3, 30
4, and depend on its resistance, other Node B L1 individual, BL2, BL3, BL4 (and node SNS1, SNS2, SNS3, SNS4) will for high or low.In shownschematically special circumstances, because memory storage 30
1, 30
2low resistance, then Node B L1, BL2 and SNS1, SNS2 will be high, and because memory storage 30
3, 30
4high resistance, then Node B L3, BL4 and SNS3, SNS4 will for low.In memory construction 48
1in, due to SNS1 for high and SET are low, Node B 1 will remain on 1 state.In memory construction 48
2in, then due to SNS for high and SET are low, Node B 2 will remain on 0 state.In memory construction 48
3in, due to SNS be low and SNS is low, and Node B 3 will remain on 1 state.But, in memory construction 48
4in, due to SNS be low and SET is low, and Node B 4 will be forced to height, namely enter 1 state, force its node A4 to enter low or 0 state.
Then (Fig. 8), signal RDPB is driven to height, by transistor 72 conducting, and makes in memory construction 48
1, 48
2, 48
3, 48
4node A1, A2, A3, A4 information continuously with 0100 sequence (series) via y decoder transistor 62
1, 62
2, 62
3, 62
4be passed to logic 54.Logic 54 provides information to be the memory storage of 1 to write driver 52 with the state of the node A only wiping those and wherein associate.In this situation, this is only memory storage 30
2.Then (Fig. 9), due to only y decoder transistor 62
2conducting, high electric current is driven through memory storage 30 by write driver 52
2in suitable direction to provide this memory storage 30
2erasing.As shown in Figure 9, through this operation, memory storage 30
2state change to 1 (high resistance) from 0 (low resistance).Meanwhile, memory storage 30
1, 30
3, 30
4state remain unchanged, make memory storage 30
1, 30
2, 30
3, 30
4state be respectively 0111 now.
For completing this erasing program (Figure 10), carry out another erase verification step, wherein BLPROT is low, SET be low and RDPB, DUMP and LDPB all for low.Due to y decoder transistor 62
1, 62
2, 62
3, 62
4conducting, drives and reads electric current by each memory storage 30
1, 30
2, 30
3, 30
4, and depending on its resistance, individual other Node B L and SNS will for high or low.Because memory storage 30
1low resistance, then Node B L1 and node SNS1 will be high, and because memory storage 30
2, 30
3, 30
4high resistance, then Node B L2, BL3 and BL4 and node SNS2, SNS3 and SNS4 will for low.All node A will, in its low state, when providing this information to logic 54, confirm to have reached as desired erasing.
Through this program whole, because DUMP is low, node C1, C2, C3, C4 have remained on its initial set condition, that is, be respectively 0101 (Figure 11).Then, make input (DUMP) to transistor 70 for high simultaneously, and make the information in each node C be provided to the latches data of its association, the state of the node C of the data register of association is same as with the state of the node A making sense latch.That is, node A1, A2, A3, A4 is respectively in 1010 states.Meanwhile, sense latch 68
1, 68
2, 68
3, 68
4node B 1, B2, B3, B4 by each in the state of node A in contrast to association, that is Node B 1, B2, B3, B4 will respectively in 1010 states.
Then, with reference to Figure 12, carry out program verification step, wherein BLPROT is low, SET for high and RDPB, DUMP and LDPB are all for low.Due to y decoder transistor 62
1, 62
2, 62
3, 62
4conducting, drives and reads electric current by each memory storage 30
1, 30
2, 30
3, 30
4, and depend on its resistance, other Node B L1 individual, BL2, BL3, BL4 and SNS1, SNS2, SNS3, SNS4 will for high or low.In shownschematically special circumstances, because memory storage 30
1low resistance, then Node B L1 (node SNS1) will be high, and because memory storage 30
2, 30
3, 30
4high resistance, then Node B L2, BL3 and BL4 and node SNS2, SNS3 and SNS4 will for low.In memory storage 30
1in, due to SNS1 be high and SET is height, then Node B 1 will be urged to 0 state, then driving node A1 to 1 state.Meanwhile, Node B 2, B3, B4 will remain on its 010 state respectively.
Then (Figure 13 and 14), signal RDPB is driven to height, turn-on transistor 72
1, 72
2, 72
3, 72
4, make in the node A of each memory construction information continuously with 1101 sequences via Y decoder transistor 62
1, 62
2, 62
3, 62
4be passed to logic 54.Logic 54 provides information to be the memory storage of 0 to write driver with the state of those node A wherein associated that only programme.In this situation, this is only memory storage 30
3.Then, due to only Y decoder transistor 62
3conducting, high electric current is driven through memory storage 30 by write driver 52
3in suitable direction to provide this memory storage 30
3programming.As shown in Figure 14, through this operation, memory storage 30
3state change to 0 (low resistance) from 1 (high resistance).Meanwhile, memory storage 30
1, 30
2, 30
4state remain unchanged, and make memory storage 30
1, 30
2, 30
3, 30
4state be respectively 0101 now, the data that initially provide are provided.
Finally, for completing this program, carry out another program verification step (Figure 15), wherein BLPROT is low, SET for high and RDPB, DUMP and LDPB are all for low.Due to y decoder transistor 62
1, 62
2, 62
3, 62
4conducting, drives and reads electric current by each memory storage 30
1, 30
2, 30
3, 30
4, and depending on its resistance, individual other node SNS will for high or low.Because memory storage 30
1, 30
3low resistance, then Node B L1 and BL3 and node SNS1, SNS3 will be high, and because memory storage 30
2, 30
4high resistance, then Node B L2, BL4 and node SNS2 and SNS4 will for low.Node B 3 will be driven to low, and driving node A3 is high.All node A will, at its high state, when providing this information to logical circuit, confirm to have reached desired programming.
As mentioned above, as shown in Figure 4, whole program occurs in response to single order.This in contrast to prior art, wherein carries out two command method, that is, wherein according to the first order, wipe the data of whole page, then according to the second order, data are write in array.In addition, will see, erasing and programming are only carried out at those wherein to be needed to change the memory storage of state from original state, that is those do not need the memory storage changing its state from original state remain in this state and do not experience erasing or programming operation.Clearly, these methods increase the effect of programming and erasing memory storage widely and reduce power supply requirement.Moreover, this method provide for the high electric current of programming and erasing apparatus is required.
Although this method easily can be applied to the ion motion resistive memory storage of type described in above-mentioned prior art, but will recognize that this method can be applicable to the memory storage of wide variety, comprise electron exchange (switching) resistive memory devices.
In order to the object illustrated and describe, state bright on the embodiment proposing the present invention.But not for thinking the form describing the present invention completely or limit the invention to accurately disclose.In view of above-mentioned teaching, known other amendment or change be possible.
Select and described the embodiment of the present invention, to propose the explanation of the best to the principle of the present invention and its practical application, make the those skilled in the art of this skill can utilize the present invention in various specific embodiment therefrom, and when consider be suitable for specific service condition time and various amendments can be had.These all modifications and variations tie up to by the scope of appended the present invention that claims determined, and these claims tie up to justice, legal and just mandate under and according to the explanation of its breadth.
Claims (7)
1., to a method for resistive memory devices (30) executive routine, comprising:
There is provided data message to data register (66) via bit line (58), wherein, this data register (66) is connected to described bit line (58) via the first switch (74), and the data message in this data register (66) indicates the expectation state of memory storage (30);
Data message from this data register (66) is provided to latch (68) via second switch (70), wherein, this second switch (70) connects this latch (68) and this data register (66), and this latch (68) is connected to this bit line (58) via the 3rd switch (72);
Data message relatively in this latch (68) and the data message in this memory storage (30); And
When the data message in this latch (68) is different from the data message in this memory storage (30), will from this latch (68) to data are write information relevant in this memory storage (30) and are provided to write driver (52) via described bit line, data write in this memory storage (30) by this write driver (52).
2. the method to resistive memory devices (30) executive routine as claimed in claim 1, wherein, writing data by this write driver (52) makes the resistance of this memory storage (30) change to higher state from lower state.
3. the method to resistive memory devices (30) executive routine as claimed in claim 1, wherein, writing data by this write driver (52) makes the resistance of this memory storage (30) change to lower state from higher state.
4. the method to resistive memory devices (30) executive routine as claimed in claim 1, wherein, write the relevant information of data according to in this memory storage (30), data also be can't help this write driver (52) and are write in this memory storage (30).
5. the method to resistive memory devices (30) executive routine as claimed in claim 2, also comprises the higher-resistivity state of this memory storage of checking (30).
6. the method to resistive memory devices (30) executive routine as claimed in claim 3, also comprises the comparatively low resistance state of this memory storage of checking (30).
7. a memory construction, comprising:
Bit line (58);
Be connected to the resistive memory devices (30) of this bit line (58), this resistive memory devices (30) includes active layer (36), and wherein the resistance of this resistive memory devices (30) is corresponding to the ion be trapped in this active layer (36);
Data register (66);
First switch (74), connects this bit line (58) and this data register (66);
Latch (68), connects this data register (66);
Second switch (70), connects this data register (66) and this latch (68);
3rd switch (72), connects this bit line (58) and this latch (68);
Comparison module, compares the data in this latch (68) and the data in this memory storage (30); And
Be connected to the write driver (52) of this bit line (58).
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US11/139,227 | 2005-05-27 | ||
| US11/139,227 US7259983B2 (en) | 2005-05-27 | 2005-05-27 | Page buffer architecture for programming, erasing and reading nanoscale resistive memory devices |
| CNA2006800155330A CN101171642A (en) | 2005-05-27 | 2006-05-26 | Page buffer architecture for programming, erasing and reading nanoscale resistive memory devices |
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| Application Number | Title | Priority Date | Filing Date |
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| CNA2006800155330A Division CN101171642A (en) | 2005-05-27 | 2006-05-26 | Page buffer architecture for programming, erasing and reading nanoscale resistive memory devices |
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| CN102708912A CN102708912A (en) | 2012-10-03 |
| CN102708912B true CN102708912B (en) | 2016-03-16 |
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| CN201210105258.9A Expired - Fee Related CN102708912B (en) | 2005-05-27 | 2006-05-26 | For the page buffer architecture of program erase reading nanoscale resistive memory devices |
| CNA2006800155330A Pending CN101171642A (en) | 2005-05-27 | 2006-05-26 | Page buffer architecture for programming, erasing and reading nanoscale resistive memory devices |
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| CNA2006800155330A Pending CN101171642A (en) | 2005-05-27 | 2006-05-26 | Page buffer architecture for programming, erasing and reading nanoscale resistive memory devices |
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| US (1) | US7259983B2 (en) |
| EP (1) | EP1883929A1 (en) |
| JP (1) | JP4704460B2 (en) |
| KR (1) | KR20080022120A (en) |
| CN (2) | CN102708912B (en) |
| TW (1) | TW200703360A (en) |
| WO (1) | WO2006130438A1 (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7471556B2 (en) * | 2007-05-15 | 2008-12-30 | Super Talent Electronics, Inc. | Local bank write buffers for accelerating a phase-change memory |
| US7259983B2 (en) * | 2005-05-27 | 2007-08-21 | Spansion Llc | Page buffer architecture for programming, erasing and reading nanoscale resistive memory devices |
| US8077495B2 (en) * | 2006-12-05 | 2011-12-13 | Spansion Llc | Method of programming, erasing and repairing a memory device |
| US7474579B2 (en) * | 2006-12-20 | 2009-01-06 | Spansion Llc | Use of periodic refresh in medium retention memory arrays |
| JP5253784B2 (en) * | 2007-10-17 | 2013-07-31 | 株式会社東芝 | Nonvolatile semiconductor memory device |
| US8213243B2 (en) | 2009-12-15 | 2012-07-03 | Sandisk 3D Llc | Program cycle skip |
| JP5404683B2 (en) | 2011-03-23 | 2014-02-05 | 株式会社東芝 | Resistance change memory |
| CN102855928A (en) * | 2011-06-28 | 2013-01-02 | 中国科学院微电子研究所 | Electric resistance transformation memory array and storage operation method therefor |
| KR101959846B1 (en) * | 2012-03-02 | 2019-03-20 | 삼성전자주식회사 | Resistive memory device |
| US8947972B2 (en) | 2013-03-15 | 2015-02-03 | Sandisk 3D Llc | Dynamic address grouping for parallel programming in non-volatile memory |
| US8947944B2 (en) | 2013-03-15 | 2015-02-03 | Sandisk 3D Llc | Program cycle skip evaluation before write operations in non-volatile memory |
| US9711225B2 (en) | 2013-10-16 | 2017-07-18 | Sandisk Technologies Llc | Regrouping and skipping cycles in non-volatile memory |
| CN107209257B (en) | 2014-12-17 | 2021-07-27 | 文卡塔·古鲁帕萨德 | Linear frequency modulation traveling wave solution and spectrum |
| US9564215B2 (en) | 2015-02-11 | 2017-02-07 | Sandisk Technologies Llc | Independent sense amplifier addressing and quota sharing in non-volatile memory |
| CN112435697A (en) * | 2020-12-29 | 2021-03-02 | 深圳市芯天下技术有限公司 | High-reliability nonvolatile memory and memory cell array thereof |
| CN113409840A (en) * | 2021-06-30 | 2021-09-17 | 芯天下技术股份有限公司 | State register and write operation method, chip and device thereof |
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| DE10300521A1 (en) * | 2003-01-09 | 2004-07-22 | Siemens Ag | Organoresistive memory |
| US7259983B2 (en) * | 2005-05-27 | 2007-08-21 | Spansion Llc | Page buffer architecture for programming, erasing and reading nanoscale resistive memory devices |
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2005
- 2005-05-27 US US11/139,227 patent/US7259983B2/en active Active
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- 2006-05-26 CN CN201210105258.9A patent/CN102708912B/en not_active Expired - Fee Related
- 2006-05-26 EP EP06771228A patent/EP1883929A1/en not_active Withdrawn
- 2006-05-26 KR KR1020077030213A patent/KR20080022120A/en not_active Application Discontinuation
- 2006-05-26 JP JP2008513731A patent/JP4704460B2/en active Active
- 2006-05-26 WO PCT/US2006/020326 patent/WO2006130438A1/en active Application Filing
- 2006-05-26 CN CNA2006800155330A patent/CN101171642A/en active Pending
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| US6118703A (en) * | 1998-04-22 | 2000-09-12 | Nec Corporation | Nonvolatile storage device and control method therefor |
| CN1574094A (en) * | 2003-05-27 | 2005-02-02 | 索尼株式会社 | Memory device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2008542957A (en) | 2008-11-27 |
| JP4704460B2 (en) | 2011-06-15 |
| TW200703360A (en) | 2007-01-16 |
| WO2006130438A1 (en) | 2006-12-07 |
| KR20080022120A (en) | 2008-03-10 |
| US20060268595A1 (en) | 2006-11-30 |
| CN102708912A (en) | 2012-10-03 |
| EP1883929A1 (en) | 2008-02-06 |
| CN101171642A (en) | 2008-04-30 |
| US7259983B2 (en) | 2007-08-21 |
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