CN102693985B - A kind of programmable storage and manufacture method thereof - Google Patents
A kind of programmable storage and manufacture method thereof Download PDFInfo
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- CN102693985B CN102693985B CN201110073405.4A CN201110073405A CN102693985B CN 102693985 B CN102693985 B CN 102693985B CN 201110073405 A CN201110073405 A CN 201110073405A CN 102693985 B CN102693985 B CN 102693985B
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Abstract
The invention provides a kind of programmable storage and manufacture method thereof, described memory comprises CMOS tube and variable resistor; CMOS tube comprises silicon substrate, separator, source area, drain region, gate regions, the first electrode and the second electrode; Silicon substrate is positioned under separator, and source area and drain region are positioned at the upper both sides of silicon substrate; The downside of gate region in separator, the two ends of gate regions are connected with source area and drain region; First through hole of the built-in vertical direction in both sides of separator and the second through hole; First through hole lower end is connected with source area, the first electrode for being made up of metal material in the first through hole; Second through hole lower end is connected with drain region, and the first half in the second through hole is the second electrode be made up of metal material, and the latter half in the second through hole is the variable resistor be made up of resistive material.Memory of the present invention can realize programmable addressing operation, and the manufacture method of this memory can be compatible with existing CMOS technology processing procedure.
Description
Technical field
The present invention relates to semiconductor memory technologies field, particularly relate to a kind of programmable storage and manufacture method thereof.
Background technology
When flash memory (FlashMemory) is below 65nm manufacturing process, its memory technology will run into the restriction of such as process complexity, very formidable technical difficulty on the reduction scheduling theory of memory reliability.At present at semiconductor industry, people are by some novel memory devices as the object substituting flash storage in the future, and wherein the very promising technology of one is exactly resistance-variable storing device (RRAM, ResistiveRandomAccessmemory).The material for resistance-variable storing device of research both at home and abroad comprises now: Perovskite Phase PZT, Cu base oxide, W base oxide, amorphous silicon etc., all show these resistance-variable storing devices and can realize than existing flash storage read or write speed and better microtechnology ability more fast in report.And the material such as amorphous silicon, W base oxide wherein has the advantage can mating existing CMOS technology.
The resistance-variable storing device that the people such as the SungHyunJo of the University of Michigan of NANOLett report in 2008 manufacture with amorphous silicon (a-Si), demonstrate amorphous silicon and there is resistive characteristic, and the function of storage array can be used for, but this technology only achieves the checking of simpler array, the circuit functions such as addressing operation can not be realized.And because processing procedure is special, and fail to realize and the embedding completely of existing CMOS technology.Because the RRAM circuit of existing majority report is cross type circuit, namely bit line intersects with wordline, it crosspoint is memory cell, this circuit does not have special control unit for memory cell, so be difficult to realize the independent control operation to memory cell, therefore, existing RRAM circuit engineering is not easy to realize addressing operation.
In a word, the technical problem needing those skilled in the art urgently to solve is exactly: how can provide a kind of memory construction and manufacture method thereof, this memory can realize programmable addressing operation, and its manufacture method can be compatible with existing CMOS technology processing procedure.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of memory, can realize programmable addressing operation, and the manufacture method of this memory can be compatible with existing CMOS technology processing procedure.
In order to solve the problem, the invention discloses programmable storage, comprise: CMOS tube and variable resistor;
Described CMOS tube comprises: silicon substrate, separator, source area, drain region, gate regions, the first electrode and the second electrode; Wherein,
Described silicon substrate is positioned under separator, and described source area and drain region lay respectively at the both sides, top in silicon substrate; The downside of described gate region in separator, the two ends of gate regions are connected with source area and drain region respectively;
First through hole of the built-in vertical direction of both sides difference of separator and the second through hole; The lower end of described first through hole is connected with source area, the first electrode for being made up of metal material in the first through hole; The lower end of described second through hole is connected with drain region, and the first half in the second through hole is the second electrode be made up of metal material, and the latter half in the second through hole is the variable resistor be made up of resistive material.
Preferably, described resistive material is identical with the material forming gate regions.
Preferably, described resistive material is polysilicon.
Preferably, the upper end of described first electrode is provided with the first electrode wires, described first electrode wires ground connection; The upper end of described second electrode is provided with the second electrode wires, and described second electrode is connected with bit line; Described gate regions is connected with wordline.
Preferably, when the second electrode applying be greater than the positive voltage that the positive voltage of the first preset threshold value voltage or the second electrode apply and cancelling, variable-resistance resistance is less than normal value, and the store status of memory is " 1 "; When the second electrode applying be less than the negative voltage that the negative voltage of the second preset threshold value voltage or the second electrode apply and cancelling, variable-resistance resistance is greater than normal value, and the store status of memory is " 0 ".
Preferably, described silicon substrate comprises: the first doped silicon substrate and the second doped silicon substrate be positioned on the first doped silicon substrate; When the second doped silicon substrate is N-type doped silicon substrate, source area and drain region are P type doped region; When the second doped silicon substrate is P type doped silicon substrate, source area and drain region are N-type doped region.
Accordingly, the invention also discloses a kind of manufacture method of programmable storage, comprising:
Carry out the front road technique of CMOS tube, form the preparation CMOS tube with silicon substrate, separator, source area, drain region, gate regions, the first through hole and the second through hole;
At the upper surface deposition resistive material of preparation CMOS tube, make to fill resistive material completely in the first through hole, the second through hole;
Preparation CMOS tube is etched, makes the first through hole inside be entirely sky, the first half of the second through hole for empty, the latter half be resistive material;
In the upper surface deposit metallic material of preparation CMOS tube, make all to fill metal material in the first through hole, the first half in the second through hole fills metal material;
Carry out the postchannel process of CMOS tube, form programmable storage.
Preferably, described to preparation CMOS tube etch, comprising:
By planar etch, remove the resistive material of the first through hole, second through hole the first half filling;
The first half of the first through hole is made to retain the first half filling photoresist of empty state, the second through hole by photoengraving;
By anti-carving erosion, remove the resistive material in the first through hole, and the photoresist in removing the second through hole.
Preferably, described photoengraving comprises:
Photoresist is covered the upper surface of CMOS tube;
Mask plate be placed in the upper surface of CMOS tube and expose, wherein, the upper area of the first through hole is exposure region, and the upper area of the second through hole is blocked area;
Developer solution is acted on the upper surface of CMOS tube, remove the photoresist in the first through hole, retain the photoresist in the second through hole simultaneously.
Preferably, the postchannel process of described CMOS tube comprises:
Separator is prepared the first electrode wires and the second electrode wires;
Wherein, the first electrode wires is connected with the first electrode; Second electrode wires is connected with the second electrode.
Compared with prior art, the present invention has the following advantages:
It is symmetrical that first through hole of standard CMOS pipe and the interior material of filling of the second through hole form two electrodes.The present invention creatively embeds variable resistor in standard CMOS pipe inside, that is: in the first through hole, metal material is all filled to form the first electrode, the latter half in second through hole fills resistive material to form variable resistor, and the first half in the second through hole fills the metal material identical with in the first through hole to form the second electrode.Using variable resistor as memory cell (store status that variable-resistance resistance height is corresponding different), utilize CMOS tube as the controller of control store unit store status, then the memory proposed by the present invention can realize programmable addressing operation.
Further, forming variable-resistance resistive material can be identical with the material forming gate regions, it can be such as polysilicon, then due to the material of resistive material for using in existing CMOS technology, therefore, the manufacture of this programmable storage can be compatible with existing CMOS technology processing procedure, without the need to transforming existing CMOS technology production line.
Accordingly, the manufacture method of a kind of programmable storage that the present invention proposes, the manufacturing process realizing this memory is compatible with existing CMOS technology processing procedure completely, only need increase a photoetching process.After standard CMOS front road technique, manufacture memory cell, in CMOS tube, namely fill resistive material form variable resistor, and can be connected in standard CMOS postchannel process.
Accompanying drawing explanation
Fig. 1 is the internal structure schematic diagram of a kind of programmable storage embodiment of the present invention;
Fig. 2 is the equivalent circuit diagram of a kind of programmable storage embodiment of the present invention;
Fig. 3 is the flow chart of the manufacture method embodiment of a kind of programmable storage of the present invention;
Fig. 4 (a)-(h) is the manufacturing process schematic diagram of a kind of programmable storage of the present invention.
Embodiment
For enabling above-mentioned purpose of the present invention, feature and advantage become apparent more, and below in conjunction with the drawings and specific embodiments, the present invention is further detailed explanation.
With reference to Fig. 1, show the internal structure schematic diagram of a kind of programmable storage embodiment of the present invention, comprising: CMOS tube 11 and variable resistor 12;
Described CMOS tube 11 comprises: silicon substrate 111, separator 112, source area 113, drain region 114, gate regions 115, first electrode 116 and the second electrode 117; Wherein,
Described silicon substrate 111 is positioned under separator 112, and described source area 113 and drain region 114 lay respectively at the both sides, top in silicon substrate 111; Described gate regions 115 is positioned at the downside of separator 112, and the two ends of gate regions 115 are connected with source area 113 and drain region 114 respectively;
First through hole 118 and the second through hole 119 of the built-in vertical direction of both sides difference of separator 112; The lower end of described first through hole 118 is connected with source area 113, the first electrode 116 for being made up of metal material in the first through hole 118; The lower end of described second through hole 119 is connected with drain region 114, and the first half in the second through hole is be the variable resistor 12 be made up of resistive material by the latter half in the second electrode 117, second through hole that metal material is formed.
Further, the upper end of described first electrode 116 is provided with the first electrode wires (for conductive metal wire), described first electrode wires ground connection; The upper end of described second electrode 117 is provided with the second electrode wires (for conductive metal wire), and described second electrode is connected with bit line; Described gate regions 115 is connected with wordline.It should be noted that, in order to realize the first electrode 116 and source area 113, variable resistor 12 and the good contact of drain region 114, the first hearth electrode can also be set in the bottom of the first electrode 116, the first electrode 116 is connected with source area by the first hearth electrode; Second hearth electrode is set in the bottom of variable resistor 12, variable resistor 12 is connected with drain region 114 by the second hearth electrode.
Further, described silicon substrate comprises: the first doped silicon substrate and the second doped silicon substrate be positioned on the first doped silicon substrate; Concrete, the first doped silicon substrate is low-doped silicon substrate, the second doped silicon substrate is highly doped silicon substrate.When the second doped silicon substrate is N-type doped silicon substrate, source area and drain region are P type doped region; When the second doped silicon substrate is P type doped silicon substrate, source area and drain region are N-type doped region.Fig. 1 gives a kind of structure of the programmable storage be made up of P type metal-oxide-semiconductor, and wherein, the second doped silicon substrate is N-type doped silicon substrate, and source area and drain region are P type doped region.Structure and Fig. 1 of the programmable storage be made up of N-type metal-oxide-semiconductor are similar, can cross-reference, just doped region difference.
Accordingly, Fig. 2 is the equivalent circuit diagram of a kind of programmable storage embodiment of the present invention, and the programmable storage shown in Fig. 1 is equivalent to CMOS tube and the variable resistor of series connection, and wherein, one end that CMOS tube is connected with variable resistor is for draining d.
Programmable storage of the present invention realizes data storage function by variable-resistance change in resistance, therefore, can be referred to as resistance-variable storing device RRAM again.The variable resistor 12 of described programmable storage is equivalent to a memory cell, and described CMOS tube 11 is equivalent to the controller of the mode of operation of a control store unit.Variable-resistance material can be the versatile material in existing semiconductor technology.In one particular embodiment of the present invention, described resistive material is identical with the material forming gate regions.Due to the material of resistive material for using in existing CMOS technology, therefore, the manufacture of this programmable storage can be compatible with existing CMOS technology processing procedure, without the need to transforming existing CMOS technology production line.Such as, in a preferred embodiment of the invention, described resistive material is polysilicon.
Below, the memory function of the programmable storage described in the embodiment of the present invention is specifically described.
When adding enough positive voltage to the second electrode (electrode) 117, namely when pressurization is greater than the first preset threshold value voltage, the inside forming the resistive material of memory cell (being also variable resistor 12) in second through hole 119 will produce conductive path based on various mechanism, such as, the metal material forming the second electrode 117 moves to resistive material internal under electric field action, general, when the metal material of upper end moves to the bottom of variable resistor 12, trickle conductive filament path can be formed, the resistance of variable resistor 12 is less than normal value during non-making alive, the resistance of whole resistance-variable storing device reduces.Further, under the condition that additional malleation is cancelled, above-mentioned trickle conductive filament can't disappear, so under the path of whole resistance-variable storing device still remains on low resistance state in the power-off state.
Corresponding, if there is sufficiently high reversed electric field effect, when the negative pressure that applying one on the second electrode 117 is enough, namely when pressurization is less than the second preset threshold value voltage, the metal material forming the second electrode 117 will exit resistive material internal, and the fine conductive path of formation is disconnected, and the resistance of variable resistor 12 is greater than normal value during non-making alive, the resistance of whole resistance-variable storing device promotes, and the resistance of whole path has returned to high-impedance state.Further, under the condition that additional negative pressure is cancelled, high-impedance state also still can keep after a loss of power.
Utilize above-mentioned mechanism, just can realize one can the function of nonvolatile memory of overprogram, by the read-write operation of controller control store unit, the store status of memory is distinguished: when the positive voltage that the positive voltage the second electrode applying be greater than the first preset threshold value voltage or the second electrode apply is cancelled according to variable-resistance resistance height, during normal value when variable-resistance resistance is less than non-making alive, the store status of memory is " 1 "; When the second electrode applying be less than the negative voltage that the negative voltage of the second preset threshold value voltage or the second electrode apply and cancelling, during normal value when variable-resistance resistance is greater than non-making alive, the store status of memory is " 0 ".The programmable storage that the embodiment of the present invention proposes can realize the read-write operation of bit position level.
With reference to Fig. 3, show the flow chart of the manufacture method embodiment of a kind of programmable storage of the present invention, comprising:
Step 301, carries out the front road technique of CMOS tube, forms the preparation CMOS tube with silicon substrate, separator, source area, drain region, gate regions, the first through hole and the second through hole;
Preparation CMOS tube manufactured after premenstrual road technique is existing standard CMOS transistor structure, and can refer to Fig. 1, described silicon substrate is positioned under separator, and described source area and drain region lay respectively at the both sides, top in silicon substrate; The downside of described gate region in separator, the two ends of gate regions are connected with source area and drain region respectively; First through hole of the built-in vertical direction of both sides difference of separator and the second through hole; The lower end of described first through hole is connected with source area; The lower end of described second through hole is connected with drain region.
Step 302, at the upper surface deposition resistive material of preparation CMOS tube, makes to fill resistive material completely in the first through hole, the second through hole;
Resistive material can be the versatile material in existing semiconductor technology.In one particular embodiment of the present invention, described resistive material is identical with the material forming gate regions.Due to the material of resistive material for using in existing CMOS technology, therefore, the manufacture of this programmable storage can be compatible with existing CMOS technology processing procedure, without the need to transforming existing CMOS technology production line.Such as, in a preferred embodiment of the invention, described resistive material is polysilicon.
Step 303, etches preparation CMOS tube, makes the first through hole inside be entirely sky, and the first half of the second through hole is sky, the latter half is resistive material;
Described step 303 comprises following sub-step:
Planar etch sub-step 3031, by carrying out planar etch to resistive material, removes the resistive material of the first through hole, second through hole the first half filling;
Photoengraving sub-step 3032, by carrying out photoengraving to resistive material, makes the first half of the first through hole retain the first half filling photoresist of empty state, the second through hole;
Anti-carving erosion sub-step 3033, by anti-carving erosion to resistive material, removing the resistive material in the first through hole, and the photoresist in removing the second through hole.
Step 304, in the upper surface deposit metallic material of preparation CMOS tube, makes all to fill metal material in the first through hole, and the first half in the second through hole fills metal material;
First through hole of standard CMOS pipe and the interior material of filling of the second through hole are symmetrical, in embodiments of the present invention, need to embed variable resistor in CMOS tube inside, therefore, first through hole and the interior material of filling of the second through hole at the brilliant lock two ends of CMOS are asymmetric, need to ensure: all fill metal material in the first through hole to form the first electrode, the latter half in second through hole fills resistive material to form the variable resistor as memory cell, and the first half in the second through hole fills the metal material identical with in the first through hole to form the second electrode.
Step 305, carries out the postchannel process of CMOS tube, forms programmable storage.
Common, the postchannel process of described CMOS tube comprises: on separator, prepare the first electrode wires and the second electrode wires; Wherein, the first electrode wires is connected with the first electrode; Second electrode wires is connected with the second electrode.When using memory, can by the first electrode wires ground connection; Second electrode is connected with bit line; The gate regions of CMOS tube is connected with wordline.
With reference to Fig. 4, show the manufacturing process schematic diagram of a kind of programmable storage of the present invention.Below, contrast Fig. 4, be specifically described the manufacture method of described programmable storage, described method comprises the steps:
A1, carries out standard CMOS Guan Qian road technique, forms the preparation CMOS tube with silicon substrate, separator, source area, drain region, gate regions, the first through hole and the second through hole, as shown in Fig. 4 (a).
A2, by the upper surface deposition resistive material in preparation CMOS tube, makes to fill resistive material completely in the first through hole, the second through hole; As shown in Fig. 4 (b).
A3, by the planar etch of resistive material, removes the resistive material of the first through hole, second through hole the first half filling; As shown in Fig. 4 (c).
A4, covers the upper surface of CMOS tube by photoresist, described photoresist is light-sensitive material; As shown in Fig. 4 (d).
A5, exposes the upper surface of CMOS tube and develops;
Photo-etching processes is most important link in semiconductor technology, makes the circuitous pattern on mould (mask plate) copy to device surface by photo-etching processes, eventually passes through etching (development) and makes circuitous pattern be retained in device surface.Concrete steps are as follows: mask plate be placed in the upper surface of CMOS tube and expose, and wherein, the upper area of the first through hole is exposure region, and the upper area of the second through hole is blocked area.Light source is irradiated on device surface by mask plate, and the light-sensitive material of light irradiated region (i.e. exposure region) and light blocked area, due to light-struck different and produce different changes, has possessed different character.Further, developer solution is acted on the upper surface of CMOS tube, chemical treatment is done to the light-sensitive material of device surface, be removed with the aitiogenic light-sensitive material of developer solution (light-sensitive material of exposure region), be retained with the nonreactive light-sensitive material of developer solution (light-sensitive material of light blocked area), circuitous pattern then on mask plate is finally formed at device surface, finally can remove the photoresist in the first through hole, retain the photoresist in the second through hole, as shown in Fig. 4 (e) simultaneously.
A6, removes the resistive material in the first through hole; As shown in Fig. 4 (f).
A7, removes the photoresist of the first half in the second through hole, and in the second through hole, the latter half retains resistive material; As shown in Fig. 4 (g).
A8, in the upper surface deposit metallic material of preparation CMOS tube, all fills metal material by the first through hole, and the first half in the second through hole fills metal material; As shown in Fig. 4 (h).
A9, carries out the postchannel process of CMOS tube, finally forms programmable storage, can see Fig. 1.
The manufacture method of a kind of programmable storage that the embodiment of the present invention proposes, the manufacturing process realizing this memory is compatible with existing CMOS technology processing procedure completely, only need increase a photoetching process.After standard CMOS front road technique, manufacture memory cell, in CMOS tube, namely fill resistive material form variable resistor, and can be connected in standard CMOS postchannel process.
Each embodiment in this specification all adopts the mode of going forward one by one to describe, and what each embodiment stressed is the difference with other embodiments, between each embodiment identical similar part mutually see.
Above to a kind of programmable storage provided by the present invention and manufacture method thereof, be described in detail, apply specific case herein to set forth principle of the present invention and execution mode, the explanation of above embodiment just understands method of the present invention and core concept thereof for helping; Meanwhile, for one of ordinary skill in the art, according to thought of the present invention, all will change in specific embodiments and applications, in sum, this description should not be construed as limitation of the present invention.
Claims (7)
1. a programmable storage, is characterized in that, comprising: CMOS tube and variable resistor;
Described CMOS tube comprises: silicon substrate, separator, source area, drain region, gate regions, the first electrode and the second electrode; Wherein,
Described silicon substrate is positioned under separator, and described source area and drain region lay respectively at the both sides, top in silicon substrate; The downside of described gate region in separator, the two ends of gate regions are connected with source area and drain region respectively;
First through hole of the built-in vertical direction of both sides difference of separator and the second through hole; The lower end of described first through hole is connected with source area, the first electrode for being made up of metal material in the first through hole; The lower end of described second through hole is connected with drain region, and the first half in the second through hole is the second electrode be made up of metal material, and the latter half in the second through hole is the variable resistor be made up of resistive material; Wherein, described variable resistor embeds in described second through hole after described first through hole and the second through hole are formed; Described resistive material is identical with the material forming gate regions; Wherein, described resistive material is polysilicon.
2. memory as claimed in claim 1, is characterized in that,
The upper end of described first electrode is provided with the first electrode wires, described first electrode wires ground connection;
The upper end of described second electrode is provided with the second electrode wires, and described second electrode is connected with bit line;
Described gate regions is connected with wordline.
3. memory as claimed in claim 2, is characterized in that,
When the second electrode applying be greater than the positive voltage that the positive voltage of the first preset threshold value voltage or the second electrode apply and cancelling, variable-resistance resistance is less than normal value, and the store status of memory is " 1 ";
When the second electrode applying be less than the negative voltage that the negative voltage of the second preset threshold value voltage or the second electrode apply and cancelling, variable-resistance resistance is greater than normal value, and the store status of memory is " 0 ".
4. memory as claimed in claim 1, is characterized in that,
Described silicon substrate comprises: the first doped silicon substrate and the second doped silicon substrate be positioned on the first doped silicon substrate;
When the second doped silicon substrate is N-type doped silicon substrate, source area and drain region are P type doped region;
When the second doped silicon substrate is P type doped silicon substrate, source area and drain region are N-type doped region.
5. a manufacture method for programmable storage, is characterized in that, comprising:
Carry out the front road technique of CMOS tube, form the preparation CMOS tube with silicon substrate, separator, source area, drain region, gate regions, the first through hole and the second through hole;
At the upper surface deposition resistive material of preparation CMOS tube, make to fill resistive material completely in the first through hole, the second through hole;
Preparation CMOS tube is etched, makes the first through hole inside be entirely sky, the first half of the second through hole for empty, the latter half be resistive material; Specifically comprise: by planar etch, remove the resistive material of the first through hole, second through hole the first half filling; The first half of the first through hole is made to retain the first half filling photoresist of empty state, the second through hole by photoengraving; By anti-carving erosion, remove the resistive material in the first through hole, and the photoresist in removing the second through hole;
In the upper surface deposit metallic material of preparation CMOS tube, make all to fill metal material in the first through hole, the first half in the second through hole fills metal material;
Carry out the postchannel process of CMOS tube, form programmable storage.
6. method as claimed in claim 5, it is characterized in that, described photoengraving comprises:
Photoresist is covered the upper surface of CMOS tube;
Mask plate be placed in the upper surface of CMOS tube and expose, wherein, the upper area of the first through hole is exposure region, and the upper area of the second through hole is blocked area;
Developer solution is acted on the upper surface of CMOS tube, remove the photoresist in the first through hole, retain the photoresist in the second through hole simultaneously.
7. method as claimed in claim 5, it is characterized in that, the postchannel process of described CMOS tube comprises:
Separator is prepared the first electrode wires and the second electrode wires;
Wherein, the first electrode wires is connected with the first electrode; Second electrode wires is connected with the second electrode.
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| CN1949391A (en) * | 2005-10-13 | 2007-04-18 | 三星电子株式会社 | Semiconductor memory device having metal-insulator transition film resistor |
| CN101720508A (en) * | 2007-06-29 | 2010-06-02 | 桑迪士克3D公司 | Memory cell that employs a selectively grown reversible resistance-switching element and methods of forming the same |
| CN101946321A (en) * | 2008-02-12 | 2011-01-12 | 松下电器产业株式会社 | Nonvolatile semiconductor memory device and manufacture method thereof |
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| CN1949391A (en) * | 2005-10-13 | 2007-04-18 | 三星电子株式会社 | Semiconductor memory device having metal-insulator transition film resistor |
| CN101720508A (en) * | 2007-06-29 | 2010-06-02 | 桑迪士克3D公司 | Memory cell that employs a selectively grown reversible resistance-switching element and methods of forming the same |
| CN101946321A (en) * | 2008-02-12 | 2011-01-12 | 松下电器产业株式会社 | Nonvolatile semiconductor memory device and manufacture method thereof |
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