CN102693955A - Package carrier and method for manufacturing the same - Google Patents
Package carrier and method for manufacturing the same Download PDFInfo
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- CN102693955A CN102693955A CN2011101070775A CN201110107077A CN102693955A CN 102693955 A CN102693955 A CN 102693955A CN 2011101070775 A CN2011101070775 A CN 2011101070775A CN 201110107077 A CN201110107077 A CN 201110107077A CN 102693955 A CN102693955 A CN 102693955A
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- reinforced structure
- circuit layer
- layer reinforced
- carrier plate
- insulating barrier
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 20
- 238000000034 method Methods 0.000 title claims abstract description 20
- 230000008569 process Effects 0.000 claims abstract description 18
- 239000000463 material Substances 0.000 claims abstract description 17
- 238000000059 patterning Methods 0.000 claims abstract description 9
- 230000004888 barrier function Effects 0.000 claims description 58
- 229910052751 metal Inorganic materials 0.000 claims description 26
- 239000002184 metal Substances 0.000 claims description 26
- 238000013459 approach Methods 0.000 claims description 17
- 230000015572 biosynthetic process Effects 0.000 claims description 14
- 230000008878 coupling Effects 0.000 claims description 12
- 238000010168 coupling process Methods 0.000 claims description 12
- 238000005859 coupling reaction Methods 0.000 claims description 12
- 150000002739 metals Chemical class 0.000 claims 2
- 238000004806 packaging method and process Methods 0.000 abstract description 3
- 238000005516 engineering process Methods 0.000 description 21
- 229920002120 photoresistant polymer Polymers 0.000 description 11
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 10
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 9
- 238000005538 encapsulation Methods 0.000 description 9
- 229910052718 tin Inorganic materials 0.000 description 9
- 239000011135 tin Substances 0.000 description 9
- 239000013078 crystal Substances 0.000 description 8
- 239000011133 lead Substances 0.000 description 6
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 5
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 5
- 229910045601 alloy Inorganic materials 0.000 description 5
- 239000000956 alloy Substances 0.000 description 5
- 229910052782 aluminium Inorganic materials 0.000 description 5
- 239000004411 aluminium Substances 0.000 description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 5
- 239000011651 chromium Substances 0.000 description 5
- 229910052804 chromium Inorganic materials 0.000 description 5
- 238000013461 design Methods 0.000 description 5
- 238000011161 development Methods 0.000 description 5
- 238000005553 drilling Methods 0.000 description 5
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 5
- 229910052737 gold Inorganic materials 0.000 description 5
- 239000010931 gold Substances 0.000 description 5
- 229910052759 nickel Inorganic materials 0.000 description 5
- 238000007639 printing Methods 0.000 description 5
- 229910052709 silver Inorganic materials 0.000 description 5
- 239000004332 silver Substances 0.000 description 5
- 238000012546 transfer Methods 0.000 description 5
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 5
- 229910052721 tungsten Inorganic materials 0.000 description 5
- 239000010937 tungsten Substances 0.000 description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- 239000004642 Polyimide Substances 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 238000005234 chemical deposition Methods 0.000 description 4
- 239000011248 coating agent Substances 0.000 description 4
- 238000000576 coating method Methods 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 4
- 239000010949 copper Substances 0.000 description 4
- 238000007747 plating Methods 0.000 description 4
- 229920001721 polyimide Polymers 0.000 description 4
- -1 polytetrafluoroethylene Polymers 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 239000004721 Polyphenylene oxide Substances 0.000 description 3
- 239000004743 Polypropylene Substances 0.000 description 3
- 239000006071 cream Substances 0.000 description 3
- 238000009713 electroplating Methods 0.000 description 3
- 239000011440 grout Substances 0.000 description 3
- 229920001343 polytetrafluoroethylene Polymers 0.000 description 3
- 238000003825 pressing Methods 0.000 description 3
- 229920005989 resin Polymers 0.000 description 3
- 239000011347 resin Substances 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000007772 electroless plating Methods 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
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- 238000005240 physical vapour deposition Methods 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 238000006116 polymerization reaction Methods 0.000 description 2
- 229920006380 polyphenylene oxide Polymers 0.000 description 2
- 229920001155 polypropylene Polymers 0.000 description 2
- 239000004810 polytetrafluoroethylene Substances 0.000 description 2
- 229910000831 Steel Inorganic materials 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000005253 cladding Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
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- 239000011810 insulating material Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000006911 nucleation Effects 0.000 description 1
- 238000010899 nucleation Methods 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- HGTDVVTWYKXXMI-UHFFFAOYSA-N pyrrole-2,5-dione;triazine Chemical compound C1=CN=NN=C1.O=C1NC(=O)C=C1 HGTDVVTWYKXXMI-UHFFFAOYSA-N 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
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Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15172—Fan-out arrangement of the internal vias
- H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P80/00—Climate change mitigation technologies for sector-wide applications
- Y02P80/30—Reducing waste in manufacturing processes; Calculations of released waste quantities
Abstract
The invention provides a package carrier and a manufacturing method thereof. The first circuit build-up structure is arranged on the first surface and comprises an insulating layer and a first patterning circuit layer. And the second circuit layer-adding structure is arranged on the second surface and comprises an insulating layer and a second patterned circuit layer. The third line layer-adding structures are arranged on the first line layer-adding structures, each third line layer-adding structure comprises an insulating layer and a third patterned line layer, the minimum distance between the third patterned line layers is smaller than the minimum distance between the second patterned line layers, and the insulating layers of the first line layer-adding structures, the second line layer-adding structures and each third line layer-adding structure are made of the same material. The packaging carrier plate and the manufacturing method thereof can save the process cost, reduce the yield loss of the packaging ball mounting and reduce the thickness of the packaged finished product.
Description
Technical field
The present invention relates to a kind of encapsulating carrier plate and manufacturing approach thereof, relate in particular to a kind of encapsulating carrier plate and manufacturing approach thereof with asymmetric layer reinforced structure.
Background technology
In integrated circuit (IC) encapsulation technology, (flip chip, FC) support plate has the functions such as electric connection, entity support and heat radiation that provide between electronic product chip and printed circuit board (PCB) (PCB) to flip-chip.Known flip-chip support plate technology is that substrate is increased layer process through machine drilling, grout, image transfer and insulation; Repeat the dual side build-up layers step and weld green lacquer coating to resist in the back for several times; Again via paste solder printing, reflow and cutting technique; Final known flip-chip (flip chip, FC) support plate that form with symmetrical layer reinforced structure.
Because the BGA spacing (BGA pitch) of electronic product requires day by day accurate, so also wide and thin space (fine pitch) development of the wires design of flip-chip support plate towards fine rule.Yet, the wires design requirement that surface mounting technology (SMT) technological ability of printed circuit board (PCB) now (PCB) but can't mate the flip-chip support plate.So existing development switching support plate (interposer), by the rewiring design with the flip-chip support plate convert standard printed circuit board (PCB) ball distance than fine-pitch to through the support plate (interposer) of transferring, in order to follow-up surface mount process.But the use of switching support plate (interposer) can produce problems such as the technology cost rises, packaging yield descends, the increase of encapsulation finished product thickness.
In this technical field, a kind of encapsulating carrier plate of needs is arranged, to improve above-mentioned shortcoming.
Summary of the invention
In order to overcome the shortcoming that prior art exists, in view of this, one embodiment of the invention provides a kind of encapsulating carrier plate, comprises a core board, and it has a second surface of a first surface and above-mentioned relatively first surface.One first circuit layer reinforced structure is arranged on the above-mentioned first surface, and the wherein above-mentioned first circuit layer reinforced structure comprises an insulating barrier and one first patterned line layer.One second circuit layer reinforced structure is located on the above-mentioned second surface, and the above-mentioned second circuit layer reinforced structure comprises an insulating barrier and one second patterned line layer.A plurality of tertiary circuit layer reinforced structures; Be arranged on the above-mentioned first circuit layer reinforced structure; Wherein each tertiary circuit layer reinforced structure comprises an insulating barrier and one the 3rd patterned line layer; Wherein the minimum spacing of above-mentioned the 3rd patterned line layer of each more above-mentioned tertiary circuit layer reinforced structure is less than the minimum spacing of above-mentioned second patterned line layer, and the above-mentioned insulating barrier of the wherein above-mentioned first circuit layer reinforced structure, the above-mentioned second circuit layer reinforced structure and each more above-mentioned tertiary circuit layer reinforced structure is identical material.
Another embodiment of the present invention provides a kind of manufacturing approach of encapsulating carrier plate, and comprising provides a core board, and it has a second surface of a first surface and above-mentioned relatively first surface.Respectively at forming one first circuit layer reinforced structure and one second circuit layer reinforced structure on above-mentioned first surface and the above-mentioned second surface, the wherein above-mentioned second circuit layer reinforced structure comprises one second line layer of an insulating barrier and the above-mentioned insulating barrier of comprehensive covering.Only on the above-mentioned first circuit layer reinforced structure, form a plurality of tertiary circuit layer reinforced structures.Above-mentioned second line layer of the above-mentioned second circuit layer reinforced structure of patterning.
In encapsulating carrier plate provided by the invention and the manufacturing approach thereof; Encapsulating carrier plate is integrated integrated circuit board and keyset; So that same encapsulating carrier plate not homonymy meet IC chip thin space (finepitch) and printed circuit board (PCB) respectively ball apart from (ball pitch) demand, it can directly be engaged with IC chip and printed circuit board (PCB), can save the technology cost; And reduce encapsulation and plant the yield loss of ball, and can reduce encapsulation back finished product thickness.
Description of drawings
Fig. 1～Fig. 5 is the process section of the encapsulating carrier plate of one embodiment of the invention.
Fig. 6 is the encapsulating carrier plate of one embodiment of the invention combines formation with IC chip an encapsulating structure sketch map.
[main description of reference numerals]
200～core board;
203～grout resin;
212～first surface;
214～second surface;
220a, 220b～internal layer circuit layer;
230～via;
240a～first circuit the layer reinforced structure;
240b～second circuit the layer reinforced structure;
242a, 242b, 252,262,272～insulating barrier;
244a, 244c, 254,264,274～patterned line layer;
244b～line layer;
246a, 246b, 256,266,276～conductive blind hole;
250,260,270～tertiary circuit layer reinforced structure;
284a, 284b～anti-weldering insulating barrier;
286a, 286b～opening;
288a, 288b～coat of metal;
290,302～prewelding metal coupling;
292～primer;
300～IC chip;
500～encapsulating carrier plate
P1, P2～minimum spacing
T1, T2～thickness.
Embodiment
Below specify and be accompanied by the example of description of drawings with each embodiment, as reference frame of the present invention.In accompanying drawing or specification description, similar or identical part is all used identical Reference numeral.And in the accompanying drawings, the shape of embodiment or thickness can enlarge, and to simplify or convenient the sign.Moreover; The part of each element will be it should be noted that element not shown or that describe to describe explanation respectively in the accompanying drawing; For having the form that the technical staff knew of general knowledge in the affiliated technical field; In addition, certain embodiments is merely the ad hoc fashion that open the present invention uses, and it is not in order to limit the present invention.
Fig. 1～Fig. 5 is the process section of the encapsulating carrier plate 500 of one embodiment of the invention.The encapsulating carrier plate of the embodiment of the invention is the encapsulating carrier plate with asymmetric layer reinforced structure; Wherein encapsulating carrier plate is integrated integrated circuit board and keyset; So that same encapsulating carrier plate not homonymy meet IC chip thin space (fine pitch) and printed circuit board (PCB) respectively ball apart from (ball pitch) demand, it can directly be engaged with IC chip and printed circuit board (PCB), can save the technology cost; And reduce encapsulation and plant the yield loss of ball, and can reduce encapsulation back finished product thickness.In addition; The line layer that above-mentioned encapsulating carrier plate meets a side of printed circuit board ball distance is comprehensive covering core board and not being patterned when the single face of a side that meets the IC chip thin space increases layer process, and the stress inequality causes the crooked problem of plate face when increasing layer process to avoid carrying out single face.
Please refer to Fig. 1, a core board 200 is provided, it has a first surface 212 and a relative second surface 214.Then, physical technologies such as machine drilling capable of using or laser drill, first surface 212 or the second surface 214 from core board 200 removes part core board 200 materials respectively, in core board 200, to form the via 230 that runs through core board 200.
Then; The modes such as physical vapor deposition (PVD) of coating capable of using (coating), chemical vapor deposition (CVD), for example sputter (sputtering); Compliance forms an inculating crystal layer (seed layer) (figure does not show) on core board 200, and covers the madial wall of first surface 212, second surface 214 and via 230.In an embodiment of the present invention, inculating crystal layer is a skim, and its material can comprise nickel, gold, tin, lead, copper, aluminium, silver, chromium, tungsten, silicon or its combination or above-mentioned alloy.Above-mentioned inculating crystal layer is convenient to metal level nucleation and the growth above that so as to utilizing plating mode to form.Then, plating mode capable of using, compliance forms an electroplated metal layer on inculating crystal layer, and covers the madial wall of first surface 212, second surface 214 and via 230.In an embodiment of the present invention, the material of first electroplated metal layer can be same as above-mentioned inculating crystal layer.Afterwards, form the grout resin 203 that fills up via 230.
Then; Image transfer capable of using; Promptly via the step that covers photoresist, development (developing), etching (etching) and striping (striping); Remove part first electroplated metal layer and part inculating crystal layer,, can be considered internal layer circuit layer 220a and 220b again on the first surface of core board 200 212 and second surface 214, to form patterned electricity metal cladding 220a and 220b.
Then, increase layer process, form one first circuit layer reinforced structure 240a and one second circuit layer reinforced structure 240b respectively on the first surface of core board 200 212 and the second surface 214.The circuit layer reinforced structure of equal number is set on the first surface 212 of core board 200 and the second surface 214 in an embodiment of the present invention, symmetrically.The first circuit layer reinforced structure 240a can comprise an insulating barrier 242a who covers internal layer circuit layer 220a, be formed on the insulating barrier 242a patterned line layer 244a with pass in insulating barrier 242a and in order to the patterned line layer 244a that electrically connects different layers and the conductive blind hole 246a of internal layer circuit layer 220a.And the second circuit layer reinforced structure 240b also can comprise the insulating barrier 242b of covering internal layer circuit layer 220b and pass in insulating barrier 242b and in order to the patterned line layer 244b of electric connection different layers and the conductive blind hole 246b of internal layer circuit layer 220b.It should be noted that in this step, be formed at the line layer 244b comprehensive covering insulating barrier 242b on the insulating barrier 242b and be not patterned.
In an embodiment of the present invention; The generation type of the first circuit layer reinforced structure 240a and one second circuit layer reinforced structure 240b can comprise utilizes process for pressing, attaches insulating barrier 242a and the insulating barrier 242b with identical material respectively on the first surface 212 of core board 200 and the second surface 214.Afterwards, laser drill capable of using (laser drilling) technology is respectively at forming a plurality of blind holes among insulating barrier 242a and the insulating barrier 242b, to reserve the position of follow-up formation conductive blind hole 246a and 246b.Then; Utilize image transfer; Promptly via the step that covers photoresist, exposure and development (developing); On the surface of insulating barrier 242a, form patterning photoresist layer (scheming not shown); But in this step, on the surface of insulating barrier 242b, do not form patterning photoresist layer; Utilize modes such as electroplating (known technology that forms plating of inculating crystal layer is so figure is not shown), chemical deposition or electroless plating again, respectively at not being patterned the line layer 244b that forms conductive blind hole 246a and 246b, patterned line layer 244a and comprehensive covering insulating barrier 242b surface on photoresist layer dielectric layer covered 242a and the insulating barrier 242b simultaneously.In an embodiment of the present invention, the material of conductive blind hole 246a and 246b, patterned line layer 244a and line layer 244b can comprise nickel, gold, tin, lead, copper, aluminium, silver, chromium, tungsten, silicon or its combination or above-mentioned alloy.
In an embodiment of the present invention; Insulating barrier 242a is identical material with insulating barrier 242b; For example be epoxy resin (epoxy resin), two Maleimide-triazine resin (bismaleimidetriacine; BT), polyimides (polyimide), ABF film (ajinomoto build-up film), polyphenylene oxide (poly phenylene oxide, PPE) or polytetrafluoroethylene (polytetrafluorethylene, PTFE).
Then; Please refer to Fig. 2; Carry out single face and increase layer process; Only on the first circuit layer reinforced structure 240a structure, form a plurality of tertiary circuit layer reinforced structures, for example the tertiary circuit layer reinforced structure 250,260 and 270, and make the minimum spacing P1 of the patterned line layer of the tertiary circuit layer reinforced structure 270 that is positioned at outermost layer (apart from the furthest of core board 200) equal the pad minimum spacing of an IC chip.In an embodiment of the present invention, the tertiary circuit layer reinforced structure quantity and unrestricted is set, and according to client's design and decide.In an embodiment of the present invention; Tertiary circuit layer reinforced structure 250,260 and 270 generation type are similar to the generation type of the first circuit layer reinforced structure 240a and the second circuit layer reinforced structure 240b; And when the single face that forms tertiary circuit layer reinforced structure 250,260 and 270 increases layer process, can use the for example line layer 244b of the mask layer 282 comprehensive covering second circuit layer reinforced structure 240b of polymerization dry film photoresist.For instance, the generation type of tertiary circuit layer reinforced structure 250 can comprise utilizes process for pressing, goes up in the first circuit layer reinforced structure 240a of core board 200 and attaches insulating barrier 252.Afterwards, laser drill capable of using (laser drilling) technology is respectively at forming a plurality of blind holes in the insulating barrier 252, to reserve the position of follow-up formation conductive blind hole 256.Then; Utilize image transfer; Promptly, on the surface of insulating barrier 252, form patterning photoresist layer (figure does not show), utilize again and electroplate (the known technology that forms plating of inculating crystal layer via the step that covers photoresist, exposure and development (developing); So figure shows), modes such as chemical deposition or electroless plating, form conductive blind hole 256 and patterned line layer 254 on the photoresist layer dielectric layer covered 252 in being patterned.Afterwards; Repeat above-mentioned technology again; On tertiary circuit layer reinforced structure 250, form tertiary circuit layer reinforced structure 260 and 270 in regular turn; Wherein tertiary circuit layer reinforced structure 260 comprises an insulating barrier 262 of covering tertiary circuit layer reinforced structure 250 and passes in insulating barrier 262 and in order to the patterned line layer 264 of electric connection different layers and the conductive blind hole 266 of patterned line layer 254, and wherein tertiary circuit layer reinforced structure 270 comprises an insulating barrier 272 that covers tertiary circuit layer reinforced structure 260 and passes in insulating barrier 272 and in order to the patterned line layer 274 of electric connection different layers and the conductive blind hole 276 of patterned line layer 264.In an embodiment of the present invention, the thickness T 2 of line layer 244b can equal the thickness T 1 of patterned line layer 254,264 and 274.Perhaps, in another embodiment of the present invention, the thickness T 2 of line layer 244b can be greater than the thickness T 1 of patterned line layer 254,264 and 274, so that the second circuit layer reinforced structure 240b has higher mechanical strength.It should be noted that; Be not patterned owing to line layer 244b comprehensive covering insulating barrier 242b; So no matter the thickness T 2 of line layer 244b is equal to or greater than the thickness T 1 of patterned line layer 254,264 and 274; All can avoid follow-up and increase layer process and form tertiary circuit layer reinforced structure 250,260 and at 270 o'clock carrying out single face, the stress inequality causes the crooked problem of plate face.In an embodiment of the present invention; Tertiary circuit layer reinforced structure 250,260 and 270 conductive blind hole 256,266 and 276, patterned line layer 254,264 and 274 material can comprise nickel, gold, tin, lead, copper, aluminium, silver, chromium, tungsten, silicon or its combination or above-mentioned alloy, and tertiary circuit layer reinforced structure 250,260 can have identical material with 270 insulating barrier 252,262 with insulating barrier 242a and insulating barrier 242b with 272.
It should be noted that; Can design the minimum spacing and the minimum feature of the patterned line layer in the tertiary circuit layer reinforced structure 250,260 and 270 that makes from the inside to the outside and dwindle gradually, so that be positioned at the pad minimum spacing that the minimum spacing P1 of patterned line layer 274 of the tertiary circuit layer reinforced structure 270 of outermost layer (apart from the furthest of the first surface 212 of core board 200) equals an IC chip.In addition; It should be noted that; In an embodiment of the present invention, owing to the conductive blind hole of the first circuit layer reinforced structure 240a and tertiary circuit layer reinforced structure 250～270 and line layer are not to form as electroplating guiding path by via 230, so have a conductive blind hole in the first circuit layer reinforced structure 240a and the tertiary circuit layer reinforced structure 250～270 at least; For example be positioned at the conductive blind hole 246a, 256,266 and 276 in centre position, can not electrically connect with via 230.
Afterwards; Please refer to Fig. 3; The single face that meets a side of IC chip thin space in formation increases layer process (comprising the first circuit layer reinforced structure 240a and tertiary circuit layer reinforced structure 250,260 and 270) afterwards, forms the second patterned line layer 244c that meets the printed circuit board ball distance again.As shown in Figure 3, on tertiary circuit layer reinforced structure 250,260 and 270, comprehensive formation is the mask layer 280 of polymerization dry film photoresist or photoresist for example.Then, make public and (developing) step of developing, the mask layer 282 that patterning is as shown in Figure 2 is to form the mask pattern 282a of cover part line layer 244b as shown in Figure 2.Then, carry out an etch process, remove the line layer 244b that not masked pattern 282a covers.At last, striping (striping) step be can carry out, mask layer 280 and mask pattern 282a removed, to form patterned line layer 244c shown in Figure 4.The minimum spacing P2 of patterned line layer 244c that it should be noted that second surface 214 tops of core board 200 meets the printed circuit board ball distance, and less than the minimum spacing P1 of the patterned line layer 274 of tertiary circuit layer reinforced structure 270.In addition; It should be noted that; In an embodiment of the present invention, owing to the conductive blind hole of the second circuit layer reinforced structure 240b and line layer are not to form as electroplating guiding path by via 230, so have a conductive blind hole at least among the second circuit layer reinforced structure 240b; For example be positioned at the conductive blind hole 246b in centre position, can not electrically connect with via 230.
Then; Please refer to Fig. 5; Coating capable of using, print, paste, mode such as pressing, go up respectively at the tertiary circuit layer reinforced structure 270 and the second circuit layer reinforced structure 240b and to form anti-weldering insulating barrier 284a and 284b and open loop technologies such as laser drill capable of using (laser drilling), plasma etching or image transfer; Form a plurality of opening 286a and 286b respectively at selectivity among anti-weldering insulating barrier 284a and the 284b, and expose partially patterned line layer 274 and 244c.In an embodiment of the present invention; Anti-weldering insulating barrier 284a and 284b can comprise the for example anti-welding material of green lacquer; Or can be and comprise polyimides (polyimide), ABF film (ajinomoto build-up film) or polypropylene (polypropylene; PP) insulating material, it can protect conductive blind hole 246b under it, 276 and patterned line layer 244c, 274 not oxidized or short circuits each other.In addition, pass anti-weldering insulating barrier 284a and the opening 286a of 284b and the formation position that 286b can provide follow-up prewelding metal coupling.Then, chemical deposition capable of using and electrochemical means are respectively at the patterned line layer that comes out from opening 286a and 286b bottom surface 274 and 244c formation coat of metal 288a and 288b.In an embodiment of the present invention; The material of coat of metal 288a and 288b can comprise nickel, gold, tin, lead, aluminium, silver, chromium, tungsten, palladium or its combination or above-mentioned alloy, and it can increase the adhesion of prewelding metal coupling and the patterned line layer 274 and the 244c of follow-up formation.Then; Alternative is utilized chemical deposition, steel plate printing, little modes such as ball technology or plated metal of planting; Go up formation prewelding metal coupling 290 in the coat of metal 288a of a side that meets the IC chip thin space, so that the usefulness of ic core chip bonding to be provided.In an embodiment of the present invention, the material of prewelding metal coupling 290 can comprise nickel, gold, tin, lead, copper, aluminium, silver, chromium, tungsten, silicon or its combination or above-mentioned alloy.Through after the above-mentioned technology, form the encapsulating carrier plate 500 of one embodiment of the invention.
Fig. 6 is the encapsulating carrier plate 500 of one embodiment of the invention combines the encapsulating structure of formation with IC chip 300 a sketch map.As shown in Figure 6, routing capable of using, lead frame are fitted or mode such as flip-chip, an IC chip 300 are engaged to the prewelding metal coupling 290 of a side that meets the IC chip thin space of encapsulating carrier plate 500.In an embodiment of the present invention, can be provided with a primer 292 between IC chip 300 and the anti-weldering insulating barrier 284a.Then, alternative is set up the printing stencil with open loop on the anti-weldering insulating barrier 284b of a side that meets the printed circuit board ball distance of encapsulating carrier plate 500, wherein the position of the position rough alignment opening 286b of above-mentioned open loop.Afterwards, tin cream is scraped or clamp-oned in the open loop of printing stencil, the coat of metal 288b surface and the opening 286b that are positioned at the printing stencil open loop are all covered by tin cream.Utilize the reflow mode again, make on the coat of metal 288b surface with opening 286b in the tin cream fusion be a spheroid, in opening 286b, to form the prewelding metal coupling 302 of tin ball (solder ball) for example or pad (solder paste).In an embodiment of the present invention, prewelding metal coupling 302 can have identical material with prewelding metal coupling 290.Through after the above-mentioned technology, the encapsulating carrier plate 500 that forms one embodiment of the invention combines the encapsulating structure of formation with IC chip 300.Can more above-mentioned encapsulating structure be guaranteed non-defective unit via testing electrical property at last, so that the encapsulating structure that combines with printed circuit board (PCB) as directly to be provided.
The embodiment of the invention provides a kind of encapsulating carrier plate and manufacturing approach thereof.The encapsulating carrier plate of the embodiment of the invention is the encapsulating carrier plate with asymmetric layer reinforced structure; It utilizes single face to increase layer technology; With the IC chip support plate line layout of known technology on switching support plate (interposer); Be fit to combine IC chip thin space (fine pitch) demand with a side that reaches encapsulating carrier plate, and the opposite side of encapsulating carrier plate provides the ball that is fit to combine printed circuit board (PCB) (PCB) apart from (ball pitch) demand.Because the encapsulating carrier plate of the embodiment of the invention is designed to an integrated support plate with IC chip (IC) support plate and switching support plate (interposer), plant ball and yield loss cost so can save encapsulation.In addition, the encapsulating carrier plate of the embodiment of the invention, its surface can be designed has prewelding metal coupling or routing golden finger.Therefore, after itself and IC chip encapsulated, surface mounting technology capable of using (SMT) directly was engaged on the printed circuit board (PCB), can save to build up encapsulation (POP) technology and associated materials, and can reduce encapsulation back finished product thickness.Moreover; The encapsulating carrier plate of the embodiment of the invention is carrying out before single face increases layer process; Since be used to combine printed circuit board (PCB) (PCB) the support plate side the comprehensive formation of line layer and be not patterned, so can avoid carrying out single face when increasing layer process, the stress inequality causes the crooked problem of plate face.
Though the present invention with embodiment openly as above; Right its is not in order to limit the present invention; Any technical staff with general knowledge; Do not breaking away from the spirit and scope of the present invention, when can doing a little change and retouching, so protection scope of the present invention is when being as the criterion with the appended scope that claim was defined.
Claims (18)
1. encapsulating carrier plate comprises:
One core board, it has a second surface of a first surface and relative this first surface;
One first circuit layer reinforced structure is arranged on this first surface, and wherein this first circuit layer reinforced structure comprises an insulating barrier and one first patterned line layer;
One second circuit layer reinforced structure is located on this second surface, and this second circuit layer reinforced structure comprises an insulating barrier and one second patterned line layer; And
A plurality of tertiary circuit layer reinforced structures; Be arranged on this first circuit layer reinforced structure; Wherein each said a plurality of tertiary circuit layer reinforced structure comprises an insulating barrier and one first patterned line layer; Wherein the minimum spacing of the 3rd patterned line layer of each said a plurality of tertiary circuit layer reinforced structure is less than the minimum spacing of this second patterned line layer
And wherein this insulating barrier of this first circuit layer reinforced structure, this second circuit layer reinforced structure and each said a plurality of tertiary circuit layer reinforced structure is identical material.
2. encapsulating carrier plate as claimed in claim 1; Wherein this first circuit layer reinforced structure, this second circuit layer reinforced structure and each said a plurality of tertiary circuit layer reinforced structure also comprise a conductive blind hole, pass this insulating barrier of this first circuit layer reinforced structure, this second circuit layer reinforced structure and each said a plurality of tertiary circuit layer reinforced structure.
3. encapsulating carrier plate as claimed in claim 1, wherein the thickness of this second patterned line layer is greater than the thickness of the 3rd patterned line layer of each said a plurality of tertiary circuit layer reinforced structure.
4. encapsulating carrier plate as claimed in claim 2; Also comprise a via; Pass this core board, and said a plurality of conductive blind holes of at least one this first circuit layer reinforced structure, this second circuit layer reinforced structure or said a plurality of tertiary circuit layer reinforced structures do not electrically connect with this via.
5. encapsulating carrier plate as claimed in claim 2 also comprises a plurality of prewelding metal couplings, on the 3rd patterned line layer that is arranged at outermost this tertiary circuit layer reinforced structure respectively and this second patterned line layer of this second circuit layer reinforced structure.
6. encapsulating carrier plate as claimed in claim 1, the minimum spacing that wherein is positioned at the 3rd patterned line layer of outermost this tertiary circuit layer reinforced structure equals the pad minimum spacing of an IC chip.
7. encapsulating carrier plate as claimed in claim 1, the minimum spacing that wherein is positioned at this second patterned line layer of this second circuit layer reinforced structure equals the pad minimum spacing of a printed circuit board (PCB).
8. the manufacturing approach of an encapsulating carrier plate comprises the following steps:
One core board is provided, and it has a second surface of a first surface and relative this first surface;
Respectively at forming one first circuit layer reinforced structure and one second circuit layer reinforced structure on this first surface and this second surface, wherein this second circuit layer reinforced structure comprises one second line layer of an insulating barrier and comprehensive this insulating barrier of covering;
Only on this first circuit layer reinforced structure, form a plurality of tertiary circuit layer reinforced structures; And
This second line layer of this second circuit layer reinforced structure of patterning.
9. the manufacturing approach of encapsulating carrier plate as claimed in claim 8 wherein forms said a plurality of tertiary circuit layer reinforced structure and also is included in comprehensive formation one first mask layer on this second circuit layer reinforced structure before.
10. the manufacturing approach of encapsulating carrier plate as claimed in claim 9, wherein this second line layer of this second circuit layer reinforced structure of patterning comprises:
Comprehensive formation one second mask layer on said a plurality of tertiary circuit layer reinforced structures;
This first mask layer of patterning is to form one first mask pattern of this second line layer of cover part;
Carry out an etch process, remove this second line layer that is not covered, to form one second patterned line layer by this first mask pattern; And
Remove this first mask pattern and this second mask layer.
11. the manufacturing approach of encapsulating carrier plate as claimed in claim 8; Wherein this first circuit layer reinforced structure comprises one first patterned line layer that covers an insulating barrier and a conductive blind hole that passes an insulating barrier, and wherein each said a plurality of tertiary circuit layer reinforced structure comprises one the 3rd patterned line layer that covers an insulating barrier and a conductive blind hole that passes this insulating barrier.
12. the manufacturing approach of encapsulating carrier plate as claimed in claim 11 also comprises:
Respectively at forming one first anti-weldering insulating barrier and one second anti-weldering insulating barrier on outermost this tertiary circuit layer reinforced structure with on this second circuit layer reinforced structure, with the 3rd patterned line layer that exposes outermost this tertiary circuit layer reinforced structure respectively and this second patterned line layer of this second circuit layer reinforced structure with a plurality of openings;
This second patterned line layer in the 3rd patterned line layer that exposes outermost this tertiary circuit layer reinforced structure from said a plurality of openings and this second circuit layer reinforced structure forms a plurality of coat of metals; And
Respectively at forming the prewelding metal coupling on said a plurality of coat of metals.
13. the manufacturing approach of encapsulating carrier plate as claimed in claim 11, wherein the minimum spacing of the 3rd patterned line layer of each said a plurality of tertiary circuit layer reinforced structure is less than the minimum spacing of this second patterned line layer.
14. the manufacturing approach of encapsulating carrier plate as claimed in claim 11, wherein the thickness of this second line layer is greater than the thickness of the 3rd patterned line layer of each said a plurality of tertiary circuit layer reinforced structure.
15. the manufacturing approach of encapsulating carrier plate as claimed in claim 11, wherein this insulating barrier of this insulating barrier of this insulating barrier of this first circuit layer reinforced structure, this second circuit layer reinforced structure and each said a plurality of tertiary circuit layer reinforced structure is identical material.
16. the manufacturing approach of encapsulating carrier plate as claimed in claim 11; Also comprise a via; Pass this core board, and said a plurality of conductive blind holes of at least one this first circuit layer reinforced structure, this second circuit layer reinforced structure or said a plurality of tertiary circuit layer reinforced structures do not electrically connect with this via.
17. the manufacturing approach of encapsulating carrier plate as claimed in claim 8, the minimum spacing that wherein is positioned at the 3rd patterned line layer of outermost this tertiary circuit layer reinforced structure equals the pad minimum spacing of an IC chip.
18. the manufacturing approach of encapsulating carrier plate as claimed in claim 9, the minimum spacing that wherein is positioned at this second patterned line layer of this second circuit layer reinforced structure equals the pad minimum spacing of a printed circuit board (PCB).
Applications Claiming Priority (2)
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|---|---|---|---|
| TW100109666 | 2011-03-22 | ||
| TW100109666A TWI455268B (en) | 2011-03-22 | 2011-03-22 | Package substrate and method for fabricating the same |
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| CN102693955A true CN102693955A (en) | 2012-09-26 |
| CN102693955B CN102693955B (en) | 2014-11-05 |
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| CN201110107077.5A Active CN102693955B (en) | 2011-03-22 | 2011-04-22 | Package carrier and method for manufacturing the same |
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| CN (1) | CN102693955B (en) |
| TW (1) | TWI455268B (en) |
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| CN105575936A (en) * | 2014-10-30 | 2016-05-11 | 英飞凌科技股份有限公司 | Circuit carrier, method for producing circuit carrier, and method for producing and operating circuit arrangement |
| CN107785332A (en) * | 2016-08-24 | 2018-03-09 | 南亚科技股份有限公司 | Semiconductor structure |
| CN108811302A (en) * | 2017-04-27 | 2018-11-13 | 三星电机株式会社 | Printed circuit board |
| US10256180B2 (en) | 2014-06-24 | 2019-04-09 | Ibis Innotech Inc. | Package structure and manufacturing method of package structure |
| CN110035599A (en) * | 2018-01-11 | 2019-07-19 | 南亚电路板股份有限公司 | Board structure of circuit and its manufacturing method |
| CN114096059A (en) * | 2020-08-25 | 2022-02-25 | 宏恒胜电子科技（淮安）有限公司 | Circuit board and manufacturing method thereof |
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| TWI669993B (en) * | 2017-03-10 | 2019-08-21 | 興訊科技股份有限公司 | Electronic chip module for double-sided mounting parts |
| TWI687140B (en) * | 2017-03-10 | 2020-03-01 | 興訊科技股份有限公司 | Method for forming electronic chip module with attached double-sided mounting parts |
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| CN114096059B (en) * | 2020-08-25 | 2023-10-10 | 宏恒胜电子科技（淮安）有限公司 | Circuit board and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| TW201240045A (en) | 2012-10-01 |
| CN102693955B (en) | 2014-11-05 |
| TWI455268B (en) | 2014-10-01 |
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