CN102693197B - Method for calculating minimum unit of read strobe enable fine tuning register of memory controller - Google Patents
Method for calculating minimum unit of read strobe enable fine tuning register of memory controller Download PDFInfo
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Abstract
Aiming to realize configuration of a read strobe enable register, the invention discloses a method for calculating a minimum unit of a read strobe enable fine tuning register of a memory controller. A fundamental theory utilized by the calculating method of the invention is that the memory controller sends out postponing time of a read command, wherein the postponing time equals latest opportunity postponing time of the corresponding memory controller read strobe enable. The method of the invention comprises the steps of: calculating configurable maximum values of the read strobe enable fine tuning register under conditions of different clock signal postponing values firstly, then adopting the theory for calculation to a final result. According to the invention, some DDR3 memory controllers that have not been given a specific value of a minimum unit of a read strobe enable fine tuning register are enabled to finish the configuration of read strobe enable opportunity.
Description
Technical field
The present invention relates to the Memory Controller Hub field of computing machine, especially the minimum unit computing method of the enable fine setting register of DDR3 Memory Controller Hub read gate.
Background technology
In Double Data Rate 2 (DDR2), on memory modules, clock signal (Clock), address signal, command signal and control signal adopt T-shaped cabling mode.In printing board PCB design, strictly isometric between data group and data group.In read operation, after Memory Controller Hub sends read command, each memory chip on main memory access can be arrived simultaneously; Each memory chip receives read command, sends data strobe signal after the same time of interval, and the data strobe signal that finally each memory chip sends can arrive Memory Controller Hub simultaneously.Like this, enable for the read gate of each data group opportunity just can be configured to identical value by Memory Controller Hub.Therefore, in the register design of the Memory Controller Hub of DDR2, usually only have an enable coarse adjustment register of read gate, and there is no the enable fine setting register of read gate, and all data groups of unified configuration.
In Double Data Rate 3 (DDR3), on memory modules, clock signal, address signal, command signal and control signal adopt and leap bus (Fly-By Bus) cabling mode.The design of this cabling mode, in read operation, after Memory Controller Hub sends read command, on same main memory access each memory chip receive the time point of read command may be different.The memory chip leaping the first process of bus cabling receives read command at first, and this memory chip can send data at first; In like manner, last memory chip of process finally receives read command, and this memory chip finally can send data.That is, the memory chip that each data group in read operation on same passage is corresponding, the data sent may can reach Memory Controller Hub at different time points respectively.Therefore Memory Controller Hub must arrange read gate enable register to separately each data group, and the read gate enable register of DDR3 is made up of jointly read gate enable coarse adjustment register and the enable fine setting register of read gate usually.
In DDR3, Memory Controller Hub, to the configuration of the read gate enable register of individual data group, is carry out coarse adjustment by the enable coarse adjustment register of read gate, then finely tunes the enable fine setting register of read gate and jointly completes.The usual stride of coarse adjustment is comparatively large, the minimum unit (T of the enable coarse adjustment register of read gate
g0), be generally 1/2 clock period or 1/4 clock period; Finely tune usual stride less, the minimum unit (T of the enable fine setting register of read gate
f0), be generally 1/64 clock period or 1/128 clock period.In Memory Controller Hub register design, the maximal value that read gate enable fine setting register can be arranged is generally equal to the minimum unit value of the enable coarse adjustment register of read gate.Like this, the value of read gate enable register can arbitrary disposition.
Memory Controller Hub is to the configuration of the read gate enable register of individual data group, and way current is in the industry, by the value of read gate enable register by a very large value, to reduce the minimum unit (T of the enable fine setting register of read gate at every turn
f0) stride, one by one reduce do experiment, be tested to very little value always.The value write into this data group reads out correct in decision condition, adds up the read gate enable register maximal value and minimum value that satisfy condition, using the arithmetic mean of maximal value and minimum value as this data group read gate enable register end value.But in some DDR3 Memory Controller Hub, the minimum unit (T of the enable coarse adjustment register of read gate
g0) be known, but the minimum unit (T of the enable fine setting register of read gate
f0) be unknown, namely in Memory Controller Hub relevant documentation and the minimum unit (T of the enable fine setting register of undeclared read gate
f0) concrete size, only illustrate that this minimum unit is a set time length value and has nothing to do with the clock period, what this made read gate enable opportunity is configured as difficulty.
Summary of the invention
In order to solve the problem, for the DDR3 Memory Controller Hub of minimum unit the unknown of the enable fine setting register of read gate, the invention provides the minimum unit computing method of the enable fine setting register of a kind of Memory Controller Hub read gate, to complete the configuration to read gate enable register.The principle that the present invention utilizes is the time that Memory Controller Hub sends read command postponement, equals the time of the enable postponement on opportunity the latest of correspondence memory controller read gate.
The inventive method mainly comprises the steps:
(1) from the data group of Stochastic choice in passage, be used for testing;
(2) value that enable for read gate coarse adjustment register stores is set to (CL+1) * T
cK, wherein CL is that column selection leads to time delay, T
cKfor the clock period;
(3) delay register of the clock signal used by the memory chip at this data group place is set to 0, and the delay register minimum unit value of clock signal is T
c0;
(4) when the delay value of calculating clock signal is set to 0, the configurable maximal value 0 of value that read gate enable fine setting register stores
mAX, the value maximal value that now read gate enable register stores is (CL+1) * T
cK+ 0
mAX* T
f0, wherein T
f0for the minimum unit of the enable fine setting register of read gate;
(5) delay register of the clock signal used by the memory chip at this data group place is set to N;
(6) when the delay value of calculating clock signal is set to N, the configurable maximal value N of value that read gate enable fine setting register stores
mAX, the value maximal value that now read gate enable register stores is (CL+1) * T
cK+ N
mAX* T
f0;
(7), when establishing the delay register of clock signal to become N from 0, Memory Controller Hub sends the time retardation T of read command
d, i.e. T
d=N*T
c0, Memory Controller Hub read gate enable opportunity the latest also can corresponding postponement T
d, then have:
T
D＝{(CL+1)*T
CK+N
MAX*T
F0}-{(CL+1)*T
CK+0
MAX*T
F0}＝T
F0*(N
MAX-0
MAX)；
Therefore N*T is obtained
c0=T
f0* (N
mAX-0
mAX);
Thus T
f0=N*T
c0/ (N
mAX-0
mAX).
Further, the configurable maximal value 0 of value of described read gate enable fine setting register storage
mAXwith N
mAXcomputing method be:
(1) value that enable for read gate corresponding for this data group fine setting register stores is set to 0;
(2) write operation is sent;
(3) value that read operation goes to read just to have write into is sent again;
(4) check that whether read out this data group respective value correct;
(5) value itself that the enable fine setting register of read gate stores the value that enable for read gate corresponding for this data group fine setting register stores increased one by one, increases 1 at every turn, until can be arranged and effective maximal value M; The value of often establishing an enable fine setting register of read gate to store, performs step (2) to (4);
(6) with meet this data group respective value write into read out again correct in condition, the configurable maximal value of value that the read gate enable fine setting register obtaining this data group stores.
Further, the value of described N should meet N
mAXbe less than M.
The present invention, by the calculating to read gate enable fine setting register minimum unit, makes some DDR3 Memory Controller Hub directly not providing this minimum unit occurrence also can complete the configuration on read gate enable opportunity, and makes configuration result more accurate.
Accompanying drawing explanation
Fig. 1 is the computing method schematic flow sheet of the minimum unit of the enable fine setting register of read gate.
Fig. 2 is the computing method schematic flow sheet of read gate enable fine setting register maximal value.
Embodiment
Below in conjunction with drawings and Examples, the present invention is described in further detail.
The ultimate principle of the inventive method application is that Memory Controller Hub early sends read command to memory modules, and the data read out from memory chip early will arrive Memory Controller Hub; Memory Controller Hub sends read command to memory modules evening, and the data read out from memory chip will arrive Memory Controller Hub evening.In the inventive method, utilize Memory Controller Hub to send the time of read command postponement, equal the time of the enable postponement on opportunity the latest of correspondence memory controller read gate, also equal the time of the enable postponement on opportunity the earliest of correspondence memory controller read gate.Here, the opportunity the latest that read gate is enable, the maximal value of corresponding read gate enable register; The opportunity the earliest that read gate is enable, the minimum value of corresponding read gate enable register.The inventive method, utilizes Memory Controller Hub to send the time of read command postponement, equals the time of the enable postponement on opportunity the latest of correspondence memory controller read gate.Suppose time retardation T Memory Controller Hub being sent read command
d, the data that so memory chip sends will postpone T
darrive Memory Controller Hub, correspondence memory controller read gate enable opportunity the latest also can corresponding postponement T
d.
As shown in Figure 1, in order to try to achieve the minimum unit of the enable fine setting register of Memory Controller Hub read gate, the inventive method step is as follows:
(1) from the data group of Stochastic choice in passage, be used for testing;
(2) value that enable for read gate coarse adjustment register stores is set to (CL+1) * T
cK, wherein CL is that column selection leads to time delay (CAS Latency), T
cKfor the clock period;
(3) delay register of the clock signal used by the memory chip at this data group place is set to 0, and the delay register minimum unit of clock signal (Clock) is T
c0;
(4), according to the computing method of read gate enable fine setting register maximal value, when the delay value obtaining clock signal (Clock) is set to 0, the configurable maximal value of value that read gate enable fine setting register stores is 0
mAX, now read gate enable register maximal value is (CL+1) * T
cK+ 0
mAX* T
f0;
(5) delay register of the clock signal (Clock) used by the memory chip at this data group place is set to N;
(6), according to the computing method of read gate enable fine setting register maximal value, when the delay value obtaining clock signal (Clock) is set to N, the configurable maximal value of value that read gate enable fine setting register stores is N
mAX, the value maximal value that now read gate enable register stores is (CL+1) * T
cK+ N
mAX* T
f0;
(7) minimum unit (T of the enable fine setting register of read gate is calculated
f0) size, according to the ultimate principle of the inventive method, suppose time retardation T Memory Controller Hub being sent read command
d, the data that so memory chip sends will postpone T
darrive Memory Controller Hub, correspondence memory controller read gate enable opportunity the latest also can corresponding postponement T
d;
A the delay register of () clock signal (Clock) becomes N from 0, according to register description, the minimum unit value of the delay register of clock signal (Clock) is T
c0if so Memory Controller Hub sends the time retardation T of read command
d, i.e. T
d=N*T
c0, correspondence memory controller read gate enable opportunity the latest also can corresponding postponement T
d, then have:
T
D＝{(CL+1)*T
CK+N
MAX*T
F0}-{(CL+1)*T
CK+0
MAX*T
F0}＝T
F0*(N
MAX-0
MAX)；
B () therefore obtains N*T
c0=T
f0* (N
mAX-0
mAX);
(c) so, the minimum unit T of the enable fine setting register of read gate
f0for:
T
F0＝N*T
C0/(N
MAX-0
MAX)。
When the inventive method selects data group to be used for testing in step (1), be not strict with, random selecting data group can carry out correlation test.
In step (2), enable for read gate coarse adjustment register is set to (CL+1) * T
cKreason be that the starting point that read gate calculates enable opportunity sends read command signal.According to the definition of solid state technology association (JEDEC), when Memory Controller Hub read gate is enable, confidential being selected in reads to prepare in (Read Preamble) process.That is, the maximal value of read gate enable register, corresponding time point is exactly the time that data-signal (DQ) arrives Memory Controller Hub.The following describes and send read command from Memory Controller Hub and arrive the process of Memory Controller Hub to data-signal: first the read command that sends of Memory Controller Hub is through chip time delay (comprising Memory Controller Hub and memory chip internal delay time), and arrives memory chip after the time delay of printed circuit board (PCB) cabling; Memory chip is at CL*T
cKsend data-signal afterwards, data-signal arrives Memory Controller Hub again after the time delay of chip time delay (comprising Memory Controller Hub and memory chip internal delay time) and printed circuit board traces.Comprehensive above factor, is set to (CL+1) * T by enable for read gate coarse adjustment register
cKcertainly in actual debug process, if the enable coarse adjustment register of this read gate is arranged down, in the process of read gate enable fine setting register maximum value calculation, occur that all values all can not meet this data group respective value and write into when reading out correct again, then need to consider corresponding for enable for the read gate coarse adjustment register value minimum unit tuning up or turn down a coarse adjustment register.
Fig. 2 shows after the enable coarse adjustment register of read gate sets, the maximal value defining method of the enable fine setting register of read gate.As shown in Figure 2, concrete steps are as follows:
(1) value that enable for read gate corresponding for this data group fine setting register stores is set to 0;
(2) write operation is sent;
(3) value that read operation goes to read just to have write into is sent again;
(4) check that whether read out this data group respective value correct;
(5) value that enable for read gate corresponding for this data group fine setting register stores is increased one by one, increase 1 at every turn, until M value (M value is that the value itself that the enable fine setting register of read gate stores can be arranged and effective maximal value); The value of often establishing an enable fine setting register of read gate to store, performs step (2) to (4);
(6) with meet this data group respective value write into read out again correct in condition, the configurable maximal value of value that the read gate enable fine setting register finally obtaining this data group stores.
In the present invention, N
mAXwith 0
mAXare all the enable fine setting register of read gate maximal values under certain specified conditions, and should meet between M value: 0≤0
mAX< N
mAX< M; Wherein, N
mAXcan not M be equaled, work as N
mAXwhen equaling M, illustrate that meeting with the enable fine setting register of read gate itself can be arranged and effective maximum value boundary, now N
mAXinvalid.
In addition, N also should will meet N when value
mAX< M, and N value had better not be too little, otherwise larger error can be caused.
Claims (3)
1. minimum unit computing method for the enable fine setting register of Memory Controller Hub read gate, comprise the steps:
(1) from the data group of Stochastic choice in passage, be used for testing;
(2) value that enable for read gate coarse adjustment register stores is set to (CL+1) * T
cK, wherein CL is that column selection leads to time delay, T
cKfor the clock period;
(3) delay register of the clock signal used by the memory chip at this data group place is set to 0, and the delay register minimum unit value of clock signal is T
c0;
(4) when the delay value of calculating clock signal is set to 0, the configurable maximal value 0 of value that read gate enable fine setting register stores
mAX, the value maximal value that now read gate enable register stores is (CL+1) * T
cK+ 0
mAX* T
f0, wherein T
f0for the minimum unit of the enable fine setting register of read gate;
(5) delay register of the clock signal used by the memory chip at this data group place is set to N;
(6) when the delay value of calculating clock signal is set to N, the configurable maximal value N of value that read gate enable fine setting register stores
mAX, the value maximal value that now read gate enable register stores is (CL+1) * T
cK+ N
mAX* T
f0;
(7), when establishing the delay register of clock signal to become N from 0, Memory Controller Hub sends the time retardation T of read command
d, i.e. T
d=N*T
c0, Memory Controller Hub read gate enable opportunity the latest also can corresponding postponement T
d, then have:
T
D＝{(CL+1)*T
CK+N
MAX*T
F0}-{(CL+1)*T
CK+0
MAX*T
F0}＝T
F0*(N
MAX-0
MAX)；
Therefore N*T is obtained
c0=T
f0* (N
mAX-0
mAX);
Thus T
f0=N*T
c0/ (N
mAX-0
mAX).
2. method according to claim 1, is characterized in that the configurable maximal value 0 of value that described read gate enable fine setting register stores
mAXwith N
mAXcomputing method be:
(1) value that enable for read gate corresponding for this data group fine setting register stores is set to 0;
(2) write operation is sent;
(3) value that read operation goes to read just to have write into is sent again;
(4) check that whether read out this data group respective value correct;
(5) value itself that the enable fine setting register of read gate stores the value that enable for read gate corresponding for this data group fine setting register stores increased one by one, increases 1 at every turn, until can be arranged and effective maximal value M; The value of often establishing an enable fine setting register of read gate to store, performs step (2) to (4);
(6) with meet this data group respective value write into read out again correct in condition, the configurable maximal value of value that the read gate enable fine setting register obtaining this data group stores.
3. method according to claim 2, is characterized in that the value of described N should meet N
mAXbe less than M.
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| JP5160856B2 (en) * | 2007-10-24 | 2013-03-13 | ルネサスエレクトロニクス株式会社 | DDR memory controller and semiconductor device |
| JP2010122842A (en) * | 2008-11-19 | 2010-06-03 | Nec Electronics Corp | Delay adjustment device, semiconductor device and delay adjustment method |
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| US7042799B2 (en) * | 2003-12-30 | 2006-05-09 | Hynix Semiconductor Inc. | Write circuit of double data rate synchronous DRAM |
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