CN102683205A - Method for manufacturing semiconductor built-in stress nanowire and semiconductor device - Google Patents
Method for manufacturing semiconductor built-in stress nanowire and semiconductor device Download PDFInfo
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Abstract
The invention provides a method for manufacturing a built-in stress nanowire and a semiconductor device and a nanowire field effect transistor (NWFET) semiconductor device manufactured by using the method. The method uses a gate-last process (Gate-last), the lateral face of an NWFET area is protected through an amorphous carbon layer when a grid electrode area is etched, the reverse stress direction borne by the nanowire (NW) of the grid electrode area is in the horizontal direction at the time so that problems in the United States US2011/0104860A1 are effectively solved, namely the problem that reverse built-in stress of the semiconductor nanowire is not in the horizontal direction is avoided, disposition which possibly occurs on the middle portion of the semiconductor nanowire is avoided, and even the breaking problem can be solved.
Description
Technical field
The present invention relates to a kind of production technology of semiconductor device, relate in particular to method of building the stress nano wire in a kind of making the and the method for making the NWFET semiconductor device.
Background technology
Current; It is very general in advanced semiconductor device is made, to introduce strain engineering; For the channel direction crystal orientation is the MOSFET of < 110 >, when channel direction has tensile stress, can effectively increase the current driving ability of NMOSFET; And when channel direction has compression, can effectively increase the current driving ability of PMOSFET.
As a same reason; For state-of-the-art semiconductor nanowires field-effect transistor (Nanowire Field Effect Transistor; NWFET), if introduce strain engineering, also will increase the current driving ability of NWFET greatly in its nanowire length direction (being channel direction).In IEDM2010 meeting paper " Understanding of Short-Channel Mobility in Tri-Gate Nanowire MOSFETs and Enhanced Stress Memorization Technique for Performance Improvement ", reported (employing stress memory technique after to introducing stress engineering among < 110>crystal orientation NW-FET like people such as Masumi Saitoh; SMT), current driving ability has increased 58%.
U.S. Pat 2011/0104860 A1 discloses and has built stressed semiconductor nano wire preparation method in a kind of; It is based on the Semiconductor substrate with oxygen buried layer (like the SOI substrate); After the semiconductor nanowires preparation is accomplished; Deposition one deck strain film layer (compressive strain thin layer or tensile strain thin layer) is like the strain silicon nitride layer.In the final if desired semiconductor nanowires along its length (being the NWFET channel direction) have tensile stress; Then deposit the thin layer that one deck has compressive strain earlier; After follow-up strain film etching with area of grid; Because the contraction of the strain film of both sides source and drain areas makes the semiconductor nanowires of area of grid (being channel region) have tensile stress.After grid technology was accomplished, the tensile stress of this semiconductor nanowires length direction (being the NWFET channel direction) just was fixed in the semiconductor nanowires, after follow-up compressive strain thin layer is removed this tensile stress was disappeared.
In the final if desired semiconductor nanowires along its length (being the NWFET channel direction) have compression; Then deposit the thin layer that one deck has tensile strain earlier; After follow-up strain film etching with area of grid; Because the tension force effect of the strain film of both sides source and drain areas makes the semiconductor nanowires of area of grid (being channel region) have compression.After grid technology was accomplished, the compression of this semiconductor nanowires length direction (being the NWFET channel direction) just was fixed in the semiconductor nanowires, after follow-up tensile strain thin layer is removed this compression was disappeared.
First kind of situation of following surface analysis, (being the NWFET channel direction) tensile stress situation along its length in the promptly final semiconductor nanowires:
Shown in figure 15; The semiconductor nanowires 32C of this structure links to each other with 32B with semiconductor liner (Pad) 32A; And semiconductor liner 32A links to each other with 22B with dielectric base 22A with 32B, has a step to be in its prepared process, is wrapped in that compressive strain film on the semiconductor nanowires is etched away and only keeps and be wrapped in the compressive strain film on semiconductor liner 32A and the 32B; At this moment; Receive both sides shrinkage stress effect, the suffered power of semiconductor nanowires 32C is not in the horizontal direction in fact, but as the reverse tensile stress of the downward certain angle of level that marks among the figure.When semiconductor nanowires was enough thin, this not in the horizontal direction reverse tensile stress may cause the semiconductor nanowires middle part to misplace, even ruptures.
Second kind of situation of following surface analysis, (being the NWFET channel direction) compression situation along its length in the promptly final semiconductor nanowires:
Shown in figure 16; The semiconductor nanowires 32C of this structure links to each other with 32B with semiconductor liner (Pad) 32A; And semiconductor liner 32A links to each other with 22B with dielectric base 22A with 32B, has a step to be in its prepared process, is wrapped in that tensile strain film on the semiconductor nanowires is etched away and only keeps and be wrapped in the tensile strain film on semiconductor liner 32A and the 32B; At this moment; Receive both sides tensile stress effect, the suffered power of semiconductor nanowires 32C is not in the horizontal direction in fact, but as the make progress reverse compression of certain angle of the level that marks among the figure.When semiconductor nanowires was enough thin, this not in the horizontal direction reverse compression may cause the semiconductor nanowires middle part to misplace, even ruptures.
Summary of the invention
To be solved by this invention is that semiconductor nanowires is built not in the horizontal direction problem of stress in reverse in the prior art (like US2011/0104860A1).
The purpose of this invention is to provide the semiconductor device that the method for building the stress nano wire in a kind of making the, a kind of methods of making semiconductor devices and said method are made; Can avoid semiconductor nanowires to build not in the horizontal direction problem of stress in reverse; Thereby avoided that the semiconductor nanowires middle part is contingent to misplace, even breakage problem.
First purpose of the present invention provides a kind of method of building the stress nano wire in the semiconductor of making, and step comprises:
Next, promptly can be used for preparing grid, and process semiconductor device.
Second purpose of the present invention provides a kind of method of the NWFET of making semiconductor device, and step comprises:
Step 8, the nanowire surface deposition grid oxide layer exposing in the gate regions deposition of gate material, forms grid;
The 3rd aspect of the present invention provides the NMFET semiconductor device that a kind of said method is made.
In the foregoing of the present invention, said silicon substrate can be any soi wafer.Wherein, oxygen buried layer thickness is preferably 10 ~ 1000nm, and top-layer semiconductor thickness is preferably 10 ~ 200nm.
" comprising foreign ion in the top-layer semiconductor " according to the invention can be to realize that through ion injection or the original foreign ion that comprises of top-layer semiconductor it is as follow-up NWFET channel doping ion.
In the foregoing of the present invention, the semiconductor nanowires cross sectional shape can be circular, oval, the shape of horizontal or vertical runway.
In the foregoing of the present invention, said strain film can be any material that the art technology any known can be used, and is preferably silicon nitride.
Wherein, said strain film can be the compression film, has tensile stress to satisfy follow-up nanowire length direction (NWFET channel direction).
Wherein, said strain film can be the tensile stress film, has compression to satisfy follow-up nanowire length direction (NWFET channel direction).
In the foregoing of the present invention, said grid oxide layer material can be an available material arbitrarily well known by persons skilled in the art, like silicon dioxide, SiON, Si
3N
4, high κ material or above-mentioned substance combination in any.
In the foregoing of the present invention, said high κ material can be HfO
2, ZrO
2, La
2O
3, Al
2O
3, TiO
2, SrTiO
3, LaAlO
3, Y
2O
3, HfO
xN
y, ZrO
xN
y, La
2OxNy, Al
2O
xN
y, TiOxNy, SrTiO
xN
y, LaAlO
xN
y, Y
2O
xN
yA kind of or combination in any.
In the foregoing of the present invention, said grid material can be any Available Material well known by persons skilled in the art, like polysilicon, unformed silicon, the combination of metal or above-mentioned substance.
Said method of the present invention, and the NWFET semiconductor device of said method making adopt back grid technique (Gate-last), when carrying out the area of grid etching, and the existing SiO in side, NWFET zone
2Layer protection; At this moment the reversal of stress direction that receives of the NW of area of grid is a horizontal direction; Thereby efficiently solve the problem that occurs among the U.S. Pat 2011/0104860A1; Promptly avoided semiconductor nanowires to build not in the horizontal direction problem of stress in reverse, thereby avoided that the semiconductor nanowires middle part is contingent misplaces, even breakage problem.
Description of drawings
Fig. 1 ~ Figure 13 makes semiconductor nanowires and semiconductor device schematic flow sheet for the present invention, wherein:
Fig. 1 is the Semiconductor substrate structural representation;
Fig. 2 A is that etching prepares the regional generalized section of semiconductor nanowires field-effect transistor (NWFET);
Fig. 2 B is that etching prepares the regional schematic top plan view of semiconductor nanowires field-effect transistor (NWFET);
Fig. 3 is that etching is removed cross-sectional view behind the part oxygen buried layer in the step 3;
Fig. 4 is preparation semiconductor nanowires cross-sectional view;
Fig. 5 is a deposit strained film cross-sectional view in the step 5;
Fig. 6 fills the amorphous carbon cross-sectional view in the step 6;
Fig. 7 A is the gate regions cross-sectional view;
Fig. 7 B is a gate regions plan structure sketch map;
Fig. 8 is a grid oxygen process section;
Fig. 9 A is a cross section view after the deposition of gate material in the step 8;
Fig. 9 B removes cross section view behind the unnecessary grid material in the step 8;
Figure 10 removes cross section view behind residual A C layer and the strain film in the step 9;
Figure 11 is preparation side wall cross section view;
Figure 12 is a metallic silicon alloy technique cross section view;
The semiconductor device cross section view of Figure 13 for preparing after the contact hole technology;
Figure 14 is the nano wire cross sectional shape, and wherein Figure 14 A is circular, and Figure 14 B is run-track shaped for laterally, and Figure 14 C is run-track shaped for vertically;
Figure 15 is (being the NWFET channel direction) tensile stress situation along its length in the semiconductor nanowires in the prior art;
Figure 16 is (being the NWFET channel direction) compression situation along its length in the semiconductor nanowires in the prior art.
Embodiment
As shown in Figure 1, the Semiconductor substrate with oxygen buried layer is provided, preferably, substrate is a soi wafer, comprises oxygen buried layer 1 and top-layer semiconductor 2 (silicon layer).
Preferably, oxygen buried layer thickness is 10nm ~ 1000nm, and top-layer semiconductor thickness is 10nm ~ 200nm.
The original foreign ion that comprises in the top-layer semiconductor 2 is as the channel doping ion of follow-up NWFET.
Shown in Fig. 2 A and Fig. 2 B; On top-layer semiconductor 2, confirm semiconductor nanowires field-effect transistor (Nanowire FET; NWFET) preparation zone; On the preparation zone of said semiconductor nanowires field-effect transistor, cover PR mask 3, top-layer semiconductor 2 is carried out photoetching, the top-layer semiconductor 2 that is coated with PR mask 3 forms the preparation zone of semiconductor nanowires field-effect transistor; The two ends, preparation zone of said semiconductor nanowires field-effect transistor are respectively source region liner 31 and drain region liner 32, and are middle for connecting the nanowire region 30 of source region liner 31 and drain region liner 32.
Said photoetching is etched to oxygen buried layer 1 always, and etching removes part oxygen buried layer 1, makes the projecting oxygen buried layer upper surface of preparation zone oxygen buried layer upper surface of semiconductor nanowires field-effect transistor.
As shown in Figure 3; Remove the PR mask, wet etching is removed the part oxygen buried layer 1 of nanowire region 30 belows then, makes top-layer semiconductor 2 below nanowire region 30, have cavity layer 10; But should be understood that source region liner 31 should link to each other with oxygen buried layer with drain region liner 32.
Remove the surperficial oxide layer of top-layer semiconductor through thermal oxidation technology and wet method, prepare semiconductor nanowires 20, as shown in Figure 4.
Different according to semiconductor nanowires zone etching width and thickness, the cross section of semiconductor nanowires 20 can be circular (Figure 14 A), laterally runway (Figure 14 B) or vertical runway shapes such as (Figure 14 C).
With reference to Fig. 5; On nano wire 20 surfaces, source region liner 31 surfaces, drain region liner 32 surfaces and oxygen buried layer 1 upper surface deposit strained film 4 (like silicon nitride); Wherein, have tensile stress, then deposit the compressive strain film like the follow-up semiconductor nanowires length direction of needs (NWFET channel direction); Have compression like the follow-up semiconductor nanowires length direction of needs (NWFET channel direction), then deposit the tensile strain film.
With reference to Fig. 6, deposition amorphous carbon layer (AC layer) 5 makes the cavity layer 10 of top-layer semiconductor (nano wire 20) below filled by amorphous carbon.Employing has the amorphous carbon of high etching selection ratio and high absorptive as the Dummy separator in the grid technique of back, is beneficial to gate trench profile control; And agraphitic carbon ashing easily after the back grid technique is accomplished is beneficial to profile control.But be noted that: begin AC layer ashing (Ashing) processing to the back from this step; All during this time strip technologies are all used wet strip; And not using dry strip, i.e. ashing is till guaranteeing that the AC layer remains into the presedimentary cineration step of spacer medium.
Next, preparation grid, and further preparation NWFET semiconductor device.
As shown in Figure 1, the Semiconductor substrate with oxygen buried layer is provided, preferably, substrate is a soi wafer, comprises oxygen buried layer 1 and top-layer semiconductor 2 (silicon layer).
Preferably, oxygen buried layer thickness is 10nm ~ 1000nm, and top-layer semiconductor thickness is 10nm ~ 200nm.
Inject through ion in the top-layer semiconductor 2, make it comprise foreign ion, as the channel doping ion of follow-up NWFET.
On top-layer semiconductor 2, confirm semiconductor nanowires field-effect transistor (Nanowire FET; NWFET) preparation zone; On the preparation zone of said semiconductor nanowires field-effect transistor, cover hard mask; Top-layer semiconductor 2 is carried out etching; The top-layer semiconductor 2 that is coated with hard mask forms the preparation zone of semiconductor nanowires field-effect transistor, and the two ends, preparation zone of said semiconductor nanowires field-effect transistor are respectively source region liner 31 and drain region liner 32, and is middle for connecting the nanowire region 30 of source region liner 31 and drain region liner 32.
Said etching technics is etched to oxygen buried layer 1 always, and etching removes part oxygen buried layer 1, makes the projecting oxygen buried layer upper surface of preparation zone oxygen buried layer upper surface of semiconductor nanowires field-effect transistor.
As shown in Figure 3; Remove hard mask, wet etching is removed the part oxygen buried layer 1 of nanowire region 30 belows then, makes top-layer semiconductor 2 below nanowire region 30, have cavity layer 10; But should be understood that source region liner 31 should link to each other with oxygen buried layer with drain region liner 32.
Remove the surperficial oxide layer of top-layer semiconductor through thermal oxidation technology and wet method, prepare semiconductor nanowires 20, as shown in Figure 4.
Different according to semiconductor nanowires zone etching width and thickness, the cross section of semiconductor nanowires 20 can be circular (Figure 14 A), laterally runway (Figure 14 B) or vertical runway shapes such as (Figure 14 C).
With reference to Fig. 5; On nano wire 20 surfaces, source region liner 31 surfaces, drain region liner 32 surfaces and oxygen buried layer 1 upper surface deposit strained film 4 (like silicon nitride); Wherein, have tensile stress, then deposit the compressive strain film like the follow-up semiconductor nanowires length direction of needs (NWFET channel direction); Have compression like the follow-up semiconductor nanowires length direction of needs (NWFET channel direction), then deposit the tensile strain film.
With reference to Fig. 6, deposition amorphous carbon layer (AC layer) 5 makes the cavity layer 10 of top-layer semiconductor (nano wire 20) below filled by amorphous carbon.But be noted that: begin AC layer ashing (Ashing) processing to the back from this step; All during this time strip technologies are all used wet strip; And not using dry strip, i.e. ashing is till guaranteeing that the AC layer remains into the presedimentary cineration step of spacer medium.
Confirm gate regions; Those skilled in the art can learn that gate regions can be to stride across nano wire 20, shown in Fig. 7 A, 7B; (can adopt PR mask through chemical wet etching; Also can adopt Hard mask) technology comes out the area of grid etching of NWFET, the strain film layer in this zone etched away, and etch into till the oxygen buried layer always.At this moment, if former strain film layer is the compressive strain characteristic, because the contraction of Pad areal strain thin layer is leaked in the source, the NW of area of grid just has tensile stress; And if former strain film layer is the tensile strain characteristic, because the tension force effect of Pad areal strain thin layer is leaked in the source, the NW of area of grid just has compression.Simultaneously, can know, because the existing SiO in side, NWFET zone by profile
2Layer protection, at this moment the reversal of stress direction that receives of the NW of area of grid is a horizontal direction, thereby efficiently solves the problem of U.S. Pat 2011/0104860A1.
Step 8
Carry out grid oxygen technology, form grid oxide layer 61, can prepare SiO through depositing operation at the nano wire outer surface
2Perhaps SiON or Si
3N
4The grid oxide layer of perhaps high κ material or its combination, wherein, high κ material can be HfO
2, ZrO
2, La
2O
3, Al
2O
3, TiO
2, SrTiO
3, LaAlO
3, Y
2O
3, HfO
xN
y, ZrO
xN
y, La
2O
xN
y, Al
2O
xN
y, TiO
xN
y, SrTiO
xN
y, LaAlO
xN
y, Y
2O
xN
yA kind of or the combination.As shown in Figure 8.The existence of AC layer is noted that: owing to can not adopt thermal oxidation technology to prepare grid oxide layer.
In gate regions deposition of gate material 62, shown in Fig. 9 A, grid material can be polysilicon, amorphous silicon, metal or its combination then.
Remove unnecessary grid material and remove, form grid 6, shown in Fig. 9 B.
With reference to Figure 10, remove AC layer (because AC can totally and not can have influence on other part with its ashing as the Dummy separator that adopts in the grid technique of back) through cineration technics (Ashing); The rewetting method is removed remaining strain film layer; At this moment because grid oxide layer technology and grid technology are accomplished, the stress in the semiconductor nanowires is retained in semiconductor nanowires length direction (being the NWFET channel direction) and can disappear because of the removal of strain film layer.
Deposit the grid curb wall layer then, the autoregistration etching prepares grid curb wall 7, and is shown in figure 11, and carries out the source-drain area injection technology.
At last, with reference to Figure 12, carry out metallic silicon alloy technique (Silicide) in the grid both sides, preparation contact hole 9 above grid, source region and drain region is drawn NWFET source, leakage, grid, thereby obtained the NWFET semiconductor device then, and is shown in figure 13.
More than specific embodiment of the present invention is described in detail, but it is just as example, the present invention is not restricted to the specific embodiment of above description.To those skilled in the art, any equivalent modifications that the present invention is carried out with substitute also all among category of the present invention.Therefore, not breaking away from impartial conversion and the modification of being done under the spirit and scope of the present invention, all should contain within the scope of the invention.
Claims (8)
1. make the method for building the stress nano wire in the semiconductor for one kind, it is characterized in that step comprises:
Step 1 provides Semiconductor substrate, and said Semiconductor substrate comprises the oxygen buried layer of the semiconductor layer that is positioned at top layer and top-layer semiconductor below, contains foreign ion in the top-layer semiconductor;
Step 2; In the top layer semiconductor, confirm semiconductor nanowires field-effect transistor preparation zone; Prepare said semiconductor nanowires field-effect transistor zone through etching; Be etched to oxygen buried layer, and etching removal part oxygen buried layer, make the oxygen buried layer upper surface of etch areas be lower than semiconductor nanowires field-effect transistor zone oxygen buried layer upper surface; Said semiconductor nanowires field-effect transistor zone comprises the source leakage liner at two ends, and the nano wire region that connects two ends;
Step 3 is removed the part oxygen buried layer of nano wire region below, and nano wire region is separated with oxygen buried layer;
Step 4 prepares semiconductor nanowires in nano wire region;
Step 5, top layer semiconductor surface and oxygen buried layer surface deposition strain film;
Step 6, deposition amorphous carbon makes in the space between top-layer semiconductor and the oxygen buried layer and fills amorphous carbon.
2. method according to claim 1 is characterized in that, in the said silicon substrate, oxygen buried layer thickness is 10 ~ 1000nm, and top-layer semiconductor thickness is 10 ~ 200nm.
3. method according to claim 1 is characterized in that, said strain film can be the compression film.
4. method according to claim 1 is characterized in that, said strain film can be the tensile stress film.
5. method of making the NMFET semiconductor device is characterized in that step comprises:
Step 1 provides Semiconductor substrate, and said Semiconductor substrate comprises the oxygen buried layer of the semiconductor layer that is positioned at top layer and top-layer semiconductor below, contains foreign ion in the top-layer semiconductor;
Step 2; In the top layer semiconductor, confirm semiconductor nanowires field-effect transistor preparation zone; Prepare said semiconductor nanowires field-effect transistor zone through etching; Be etched to oxygen buried layer, and etching removal part oxygen buried layer, make the oxygen buried layer upper surface of etch areas be lower than semiconductor nanowires field-effect transistor zone oxygen buried layer upper surface; Said semiconductor nanowires field-effect transistor zone comprises the source leakage liner at two ends, and the nano wire region that connects two ends;
Step 3 is removed the part oxygen buried layer of nano wire region below, is that nano wire region is separated with oxygen buried layer;
Step 4 prepares semiconductor nanowires in nano wire region;
Step 5, top layer semiconductor surface and oxygen buried layer surface deposition strain film;
Step 6, deposition amorphous carbon makes in the space between top-layer semiconductor and the oxygen buried layer and fills amorphous carbon;
Step 7 is confirmed gate regions, and the strain film of etching removal gate regions, is etched to oxygen buried layer, exposes the nano wire of gate regions;
Step 8, the nanowire surface deposition grid oxide layer exposing then in the gate regions deposition of gate material, forms grid;
Step 9 is removed amorphous carbon layer and remaining strain film, and the deposition side wall carries out the source then and leaks injection technology, metallic silicon alloy technique in the grid both sides; Above source region, drain region and grid, carry out the contact hole manufacture craft at last, grid, source electrode, drain electrode are drawn, the preparation semiconductor device.
6. method according to claim 5 is characterized in that, said grid oxide layer material is selected from silicon dioxide, SiON, Si
3N
4, high κ material or above-mentioned substance combination in any.
7. method according to claim 5 is characterized in that, said grid material is selected from polysilicon, unformed silicon, the combination in any of metal or above-mentioned substance.
8. NWFET semiconductor device of making like the said method of claim 5.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2016137030A1 (en) * | 2015-02-24 | 2016-09-01 | Korea Advanced Institute Of Science And Technology | Method for enhancing performance of plasma-wave transistor |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1427437A (en) * | 2001-12-18 | 2003-07-02 | 三星Sdi株式会社 | Floating structure for forming substrate, floating gate electrode and method of field-emission device |
| CN101339968A (en) * | 2007-07-03 | 2009-01-07 | 三星电子株式会社 | Luminous device and method of manufacturing the same |
| CN101859770A (en) * | 2009-04-03 | 2010-10-13 | 国际商业机器公司 | Semiconductor structure and forming method thereof |
| CN102354669A (en) * | 2011-10-25 | 2012-02-15 | 上海华力微电子有限公司 | Production method of silicon nano-wire device |
-
2012
- 2012-05-04 CN CN201210136002.4A patent/CN102683205B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1427437A (en) * | 2001-12-18 | 2003-07-02 | 三星Sdi株式会社 | Floating structure for forming substrate, floating gate electrode and method of field-emission device |
| CN101339968A (en) * | 2007-07-03 | 2009-01-07 | 三星电子株式会社 | Luminous device and method of manufacturing the same |
| CN101859770A (en) * | 2009-04-03 | 2010-10-13 | 国际商业机器公司 | Semiconductor structure and forming method thereof |
| CN102354669A (en) * | 2011-10-25 | 2012-02-15 | 上海华力微电子有限公司 | Production method of silicon nano-wire device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2016137030A1 (en) * | 2015-02-24 | 2016-09-01 | Korea Advanced Institute Of Science And Technology | Method for enhancing performance of plasma-wave transistor |
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