CN102682179A - Method for designing light emitting diode (LED) chip model of graphical substrate - Google Patents
Method for designing light emitting diode (LED) chip model of graphical substrate Download PDFInfo
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- CN102682179A CN102682179A CN2012101699368A CN201210169936A CN102682179A CN 102682179 A CN102682179 A CN 102682179A CN 2012101699368 A CN2012101699368 A CN 2012101699368A CN 201210169936 A CN201210169936 A CN 201210169936A CN 102682179 A CN102682179 A CN 102682179A
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Abstract
The invention discloses a method for designing a light emitting diode (LED) chip model of a graphical substrate. Establishment of the LED chip model is realized by using Solidworks software, ray tracing of the LED chip model is realized by using TracePro software, and the optimal LED chip model is obtained by analyzing data and optimizing pattern parameters. The method has the advantages that the luminous flux of each surface of an LED can be intuitively and clearly obtained by software simulation, complicated physical mathematical analysis is eliminated, micro adjustment of parameters is supported, influence of all parameters of various patterns on the light emergence efficiency of the LED can be systematically researched, detection of a finished product is not required, zero-cost optimization is realized, the light emergence efficiency of the LED which is prepared by various materials can be simulated as required, and a new idea is provided for searching a preferable LED epitaxial structure or a substrate material.
Description
Technical field
The present invention relates to the led chip Model Design, particularly a kind of led chip Model Design method of patterned substrate.
Background technology
Light emitting diode (LED) is as a kind of novel solid lighting source, has energy-saving and environmental protection, longevity and outstanding feature such as colorful, all has widely in fields such as exterior lighting, commercial lighting and decorative engineerings and uses.But the application cost of present stage LED is higher, and luminescence efficiency is lower, these factors all greatly limitations LED develop to the direction of high-efficient energy-saving environment friendly.To the problem that improves LED efficient, the patterned substrate technology is widely used in the middle of the research and making of led chip as a kind of effective solution just gradually.For other solutions that early propose; Like surface coarsening, photonic crystal technology etc.; Patterned substrate can directly change the travel path of light in substrate effectively, under the prerequisite that guarantees good epitaxial crystal quality, improves the external quantum efficiency of LED greatly, embodies better technical advantage.And as the deciding factor that directly influences light path, the design and optimization of parameters such as the pattern of pattern and size is a patterned substrate Study on Technology emphasis.
Yet; The patterned substrate technology that grows up does not at present have too much stressing aspect design, although the types of patterns that has been employed is various, like long strip type; Tapered; Circular platform type, dome-type etc., but the not systematization of prioritization scheme of every kind of design of patterns and pattern parameter, this makes patterned substrate LED fail to have given play to best work efficiency.Present most of patterned substrate design of patterns all is on the practical experience basis, to optimize to form; This kind method for designing need be carried out repeatedly contrast verification; Just can obtain comparatively desirable pattern parameter, can make so undoubtedly design process become the difficulty and make slow progress.
In addition; The parameter setting of pattern also can be optimized by the physical theory and the mathematical model of optical propagation; Promptly utilize optical theory such as reflection, refraction, light absorption principle etc. earlier, design the travel path of light on substrate, utilize mathematical model to simulate the pattern and the size of underlay pattern again.Although it is theoretical that this method has possessed Base Design, computation process is too complicated, and design process need ignore more actual influence factor, and the conclusion that therefore draws is under-represented.
This shows that the patterned substrate design of patterns is still immature, method for designing is not systematization as yet, and this setting to pattern parameter causes very big inconvenience, and big limitations the raising of patterned substrate LED luminescence efficiency.Therefore, a kind of system is proposed, workable LED patterned substrate design of patterns method becomes the key of this technology.
SolidWorks software is a three-dimensional CAD software commonly used.It provides the control of a whole set of complete dynamic interface and mouse drag, its explorer be unique one with the similar cad file manager of Windows resource device.Powerful, be easy to learn and use and technological innovation is the three big characteristics of SolidWorks, it can provide different design proposal, reduce wrong in the design process and improve the quality of products, and is simple to operation.
TracePro software is a light simulation softward that generally is used for illuminator, optical analysis, radiometric analysis and photometric analysis.It can imitate all types of display systems (from back light system; To preceding light, light pipe, optical fiber, display panel and LCD optical projection system); Can carry out graphic presentation, visualized operation, and the database of 3D solid model is provided, possess the ability that dealing with complicated geometry is arranged; Millions of light of definable and tracking are analyzed light effectively and accurately.
Summary of the invention
For the above-mentioned shortcoming and deficiency that overcomes prior art; The object of the present invention is to provide a kind of system, the led chip Model Design method of patterned substrate easily, the light efficiency of led chip model that is designed and actual LED extension chip has the good goodness of fit.
The object of the invention is realized through following technical scheme:
A kind of led chip Model Design method of patterned substrate may further comprise the steps:
(1) substrate of structure led chip model: adopt the modeling function of Solidworks software to construct the substrate that is rectangular-shaped;
(2) on substrate, make up pattern: adopt Solidworks software; Geometric parameter according to the elementary cell of underlay pattern is set up basic body; According to the geometric parameter of basic cell array the basic body solid matter is distributed in the upper surface of substrate, obtains having the substrate model of pattern;
(3) epitaxial loayer of structure led chip model: the modeling function that adopts TracePro software to carry makes up N-epitaxial loayer, quantum well layer, P-epitaxial loayer successively; Said N-epitaxial loayer, quantum well layer, P-epitaxial loayer all are rectangular-shaped;
(4) make up target surface: the modeling function that adopts TracePro software to carry is made six target surfaces, and said six target surfaces place upper and lower, the front, rear, left and right side of led chip model respectively; The long limit of the corresponding led chip model of wherein forward and backward target surface; The minor face of the corresponding led chip model of left and right target surface;
(5) on N-epitaxial loayer and face that substrate contacts, make up and the corresponding pattern of underlay pattern: step (2) is made the file that underlay pattern builds up transform the SAT file; Import in the TracePro software; Utilize the difference of TracePro software to subtract function; Click earlier the N-epitaxial loayer, click substrate again, the corresponding pattern of pattern of structure and substrate on N-epitaxial loayer and face that substrate contact;
(6) set the material and the optical property parameter of material of substrate, N-epitaxial loayer, MQW quantum well layer, the P-epitaxial loayer of led chip model respectively;
(7) set quantum well laminar surface light source: a surface source of light attribute respectively is set at the quantum well layer upper and lower surfaces; The rink corner is distributed as the luminous field pattern of Lambertian; The emission form is a luminous flux; It is 5000a.u. that the light number is at least 10 luminous fluxes, and total light number is 3000, and minimum light number is 10;
(8) light extraction efficiency of analysis led chip model: utilize the system that clears off of TracePro software, the led chip model is carried out ray tracing, obtain the luminous flux data of top, bottom, side respectively;
(9) collect record data;
(10) optimize pattern parameter, said pattern parameter comprises the geometric parameter of elementary cell and the geometric parameter of basic cell array;
(11) confirm the led chip model.
Step (2) is distributed in the upper surface of substrate with the basic body solid matter, is specially: through the filling of the Solidworks software function of arranging the basic body solid matter is distributed in the upper surface of substrate, arrangement mode is that rectanglar arrangement or hexagonal are arranged.
The said optical property parameter of step (6) comprises refractive index, temperature setting, absorptivity, extinction coefficient, is directed against the wavelength of light.
The light extraction efficiency of the said analysis substrate of step (8) led chip: utilize the system that clears off of TracePro software, the led chip model is carried out ray tracing, obtain the luminous flux data of top, bottom, side respectively, be specially:
Utilize the system that clears off of TracePro software; The led chip model is carried out ray tracing; Obtain the luminous flux data of each face from the radiometric analysis figure that utilizes TracePro software to obtain; Wherein the luminous flux data at led chip model top is obtained from the surface 0 radiometric analysis figure of last target surface; The luminous flux data of bottom is obtained from the surface 0 radiometric analysis figure of following target surface, and the ambient light flux data is obtained from the surface 2 radiometric analysis figure of forward and backward target surface and the surface 3 radiometric analysis figure of left and right target surface respectively.
Step (6) is said sets the material and the optical property parameter of material of substrate, N-epitaxial loayer, quantum well layer, the P-epitaxial loayer of led chip respectively, is specially:
Adopt curve fitting method or the direct mode of importing to set the material and the optical property parameter of the material of the substrate of led chip, N-epitaxial loayer, quantum well layer, P-epitaxial loayer respectively.
The said optimization pattern parameter of step (10) is specially:
When selected pattern parameter was optimized, this pattern parameter was pressed increasing or decreasing rule value in selected numerical range, and other pattern parameter remains unchanged; For each value of optimised pattern parameter, repeating step (1) ~ (9) obtain the luminous flux data of led chip model, and corresponding pattern parameter value was the optimal value of this pattern parameter when optical property was optimum.
Compared with prior art, the present invention has the following advantages and beneficial effect:
(1) integrated use software of the present invention utilizes Solidworks software to realize the foundation of led chip model, utilizes TracePro software to realize led chip model ray tracing, has enlarged the range of application of underlay pattern design.
(2) the small adjustment of support parameter of the present invention, the various parameters of the various patterns of ability systematic study need not finished product to detect performance to the influence of LED light extraction efficiency, realize zero cost optimization.
(3) the present invention avoids loaded down with trivial details physical mathematics analysis, and simple and clear topotype is drawn up the luminous flux of each face of LED, and principle is simple, is convenient to promote.
(4) the present invention can adopt equivalent amplifying method, when improving the computer arithmetic capability, has reduced the wrong light number that clears off in the process, and analog result is more reliable.
(5) the present invention can simulate the light extraction efficiency of the LED of various material preparations as required, for seeking better LED epitaxial structure or backing material new approaches is provided.
Description of drawings
Fig. 1 is the process flow diagram of the led chip Model Design method of patterned substrate of the present invention.
Fig. 2 is basic body (triangular cone) synoptic diagram that embodiment 1 adopts.
Fig. 3 is the arrangement mode synoptic diagram of the basic body (triangular cone) of embodiment 1 employing.
Fig. 4 is the inclination angle changing trend diagram of the luminous flux of the led chip model among the embodiment 1 with just triangular cone.
Fig. 5 is elementary cell (semi-round ball) the arrangement mode synoptic diagram that embodiment 2 adopts.
Fig. 6 is the changing trend diagram of the luminous flux of the led chip model among the embodiment 2 with the spacing of adjacent hemispherical pattern.
Embodiment
Below in conjunction with embodiment and accompanying drawing, the present invention is done to specify further, but embodiment of the present invention is not limited thereto.
As shown in Figure 1, the led chip Model Design method of the patterned substrate of present embodiment may further comprise the steps:
(1) substrate of structure led chip model: adopt the modeling function of Solidworks software to construct substrate, substrate dimension is 600mm * 250mm * 100mm, is rectangular-shaped.
(2) on substrate, make up pattern: adopt Solidworks software; Geometric parameter according to the elementary cell of underlay pattern is set up basic body; According to the geometric parameter of basic cell array through the filling of the Solidworks software function of arranging; The basic body solid matter is distributed in the upper surface of substrate, obtains having the substrate model of pattern;
The basic body that present embodiment adopts is a just triangular cone pattern as shown in Figure 2, and geometric parameter comprises length of side l, height h, inclination angle a.Wherein length of side l is the length of side of bottom surface equilateral triangle; Height h is the distance of triangular pyramid summit triangle center to the bottom surface; Inclination angle a is the leg-of-mutton angle in cone side and bottom surface.
The geometric parameter of basic cell array comprises the space D of adjacent triangular pyramid in the present embodiment
1', the edge space D
1, length of side l, the space D of adjacent triangular pyramid
1' be 12mm, back gauge D
1Be 9.4mm, the length of side is 3mm, and arrangement mode adopts rectanglar arrangement as shown in Figure 3.
(3) epitaxial loayer of structure led chip model: the modeling function that adopts TracePro software to carry makes up N-epitaxial loayer, MQW quantum well layer, P-epitaxial loayer successively; The N-epitaxial loayer is of a size of 600mm * 250mm * 4mm, and the MQW quantum well layer is of a size of 600mm * 250mm * 50 μ m, and the P-epitaxial loayer is of a size of 600mm * 250mm * 3mm, all is rectangular-shaped.
(4) make up target surface: the modeling function that adopts TracePro software to carry is made six target surfaces, and said six target surfaces place upper and lower, the front, rear, left and right side of led chip model respectively; Upper and lower target surface is of a size of 600mm * 250mm * 3mm, and forward and backward target surface is of a size of 600mm * 104.41mm * 3mm, and left and right target surface is of a size of 250mm * 104.41mm * 3mm; The long limit of the corresponding led chip model of wherein forward and backward target surface; The minor face of the corresponding led chip model of left and right target surface.
(5) on N-epitaxial loayer and face that substrate contacts, make up and the corresponding pattern of underlay pattern: step (2) is made the file that underlay pattern builds up transform the SAT file; Import in the TracePro software; Utilize the difference of TracePro software to subtract function; Click earlier the N-epitaxial loayer, click substrate again, the corresponding pattern of pattern of structure and substrate on N-epitaxial loayer and face that substrate contact.
(6) directly import the material and the optical property parameter of material of substrate, N-epitaxial loayer, MQW quantum well layer, the P-epitaxial loayer of led chip model;
The material of substrate is selected sapphire for use in the present embodiment, and refractive index is set to 1.67; N-epitaxial loayer, MQW quantum well layer, P-epitaxial loayer are selected the GaN material for use, and refractive index is set to 2.45, four all to the light of 450nm, and temperature is set to 300K, do not consider to absorb the factor with extinction coefficient.
(7) set MQW quantum well layer surface source of light: a surface source of light attribute respectively is set at the quantum well layer upper and lower surfaces; The rink corner is distributed as the luminous field pattern of Lambertian; The emission form is a luminous flux, and the light number is at least 10, and luminous flux is 5000a.u.; Total light number is 3000, and minimum light number is 10.
(8) light extraction efficiency of analysis led chip model: the system that clears off that utilizes TracePro software; The led chip model is carried out ray tracing; Obtain the luminous flux data of top, bottom, side respectively; Be specially: the system that clears off that utilizes TracePro software; The led chip model is carried out ray tracing, obtain the luminous flux data of each face from the radiometric analysis figure that utilizes TracePro software to obtain, wherein the luminous flux data at led chip model top is obtained from the surface 0 radiometric analysis figure of last target surface; The luminous flux data of bottom is obtained from the surface 0 radiometric analysis figure of following target surface, and the ambient light flux data is obtained from the surface 2 radiometric analysis figure of forward and backward target surface (the long limit of chip relatively) and the surface 3 radiometric analysis figure of left and right target surface (minor face of chip relatively) respectively.
(9) collect record data;
(10) optimize pattern parameter: said pattern parameter comprises the geometric parameter of elementary cell and the geometric parameter of basic cell array; When selected pattern parameter was optimized, this pattern parameter was pressed increasing or decreasing rule value in selected numerical range, and other pattern parameter remains unchanged; For each value of optimised pattern parameter, repeating step (1) ~ (9) acquire the luminous flux data of led chip model, and corresponding pattern parameter value was the optimal value of this pattern parameter when optical property was optimum;
All pattern parameters are optimized, obtain the optimal value of all pattern parameters;
With the Inclination Angle Optimization is example; Pattern parameter is in order to method is definite down: one group of bottom surface length of side is made as 6mm, and the gradient with 5 ° increases progressively from 20 ° to 60 ° at the inclination angle, and one group of bottom surface length of side is made as 3mm; Gradient with 5 ° increases progressively from 45 ° to 75 ° at the inclination angle, highly all utilizes the geometric relationship formula to calculate; For each value at inclination angle, after repeating step (1) ~ (9) are simulated and obtained data, data are imported the Origin mapping software draw out broken line graph (seeing accompanying drawing 4).Can find out that by Fig. 4 in the time of 65 ° at the inclination angle, optical property is optimum, so the optimal value at inclination angle is 65 °.The optimal value deterministic process of other parameter and inclination angle similar.
(11) according to confirming the led chip model.
Physical dimension in the present embodiment all adopts equivalent amplifying method, size is expanded as actual value 1000 times.
Embodiment 2
Present embodiment is except that following characteristics, and all the other characteristics are all identical or similar with embodiment 1.
As shown in Figure 5, the basic body that adopts in the step (2) is a semisphere, and the geometric parameter of elementary cell is the radius d of hemisphere, and the geometric parameter of basic cell array comprises adjacent interhemispheric space D
2' and the edge space D
2, arrangement mode adopts hexagonal as shown in Figure 5 to arrange.
Adopt curve fitting method to set the material and the optical property parameter of the material of the substrate of led chip model, N-epitaxial loayer, MQW quantum well layer, P-epitaxial loayer in the step (6).
Optimize pattern parameter in the step (10): said pattern parameter comprises the geometric parameter of elementary cell and the geometric parameter of basic cell array; When selected pattern parameter was optimized, this pattern parameter was pressed increasing or decreasing rule value in selected numerical range, and other pattern parameter remains unchanged; For each value of optimised pattern parameter, repeating step (1) ~ (9) obtain the luminous flux data of led chip model, and corresponding pattern parameter value was the optimal value of this pattern parameter when optical property was optimum;
All pattern parameters are optimized, obtain the optimal value of all pattern parameters;
With the edge spacing is example, and pattern parameter is in order to method is definite down: the hemisphere radius is made as 2.8mm, and marginal edge increases progressively apart from the scope of gradient from 0.1mm to 3.5mm with 0.1mm; After repeating step (1) ~ (9) are simulated and obtained data, data are imported the Origin mapping software draw out broken line graph (seeing accompanying drawing 6).Can find out by Fig. 6, the increase of top and the intermarginal distance of bottom light flux lagging edge and reducing, the ambient light flux then the intermarginal distance of lagging edge increase and increase, can in conjunction with processing technology, rationally select the optimal value of edge spacing for use according to this variation tendency in the actual production.For the packed LED chip that mainly utilizes the top light flux, can take the edge spacing is the half sphere pattern (the edge spacing of input is owing to adopting equivalent amplifying method, so be 0.2mm) of 0.2 μ m.The optimal value deterministic process of other parameter and edge spacing similar.
The foregoing description is a preferred implementation of the present invention; But embodiment of the present invention is not limited by the examples; Other any do not deviate from change, the modification done under spirit of the present invention and the principle, substitutes, combination, simplify; All should be the substitute mode of equivalence, be included within protection scope of the present invention.
Claims (6)
1. the led chip Model Design method of a patterned substrate is characterized in that, may further comprise the steps:
(1) substrate of structure led chip model: adopt the modeling function of Solidworks software to construct the substrate that is rectangular-shaped;
(2) on substrate, make up pattern: adopt Solidworks software; Geometric parameter according to the elementary cell of underlay pattern is set up basic body; According to the geometric parameter of basic cell array the basic body solid matter is distributed in the upper surface of substrate, obtains having the substrate model of pattern;
(3) epitaxial loayer of structure led chip model: the modeling function that adopts TracePro software to carry makes up N-epitaxial loayer, quantum well layer, P-epitaxial loayer successively; Said N-epitaxial loayer, quantum well layer, P-epitaxial loayer all are rectangular-shaped;
(4) make up target surface: the modeling function that adopts TracePro software to carry is made six target surfaces, and said six target surfaces place upper and lower, the front, rear, left and right side of led chip model respectively; The long limit of the corresponding led chip model of wherein forward and backward target surface; The minor face of the corresponding led chip model of left and right target surface;
(5) on N-epitaxial loayer and face that substrate contacts, make up and the corresponding pattern of underlay pattern: step (2) is made the file that underlay pattern builds up transform the SAT file; Import in the TracePro software; Utilize the difference of TracePro software to subtract function; Click earlier the N-epitaxial loayer, click substrate again, the corresponding pattern of pattern of structure and substrate on N-epitaxial loayer and face that substrate contact;
(6) set the material and the optical property parameter of material of substrate, N-epitaxial loayer, MQW quantum well layer, the P-epitaxial loayer of led chip model respectively;
(7) set quantum well laminar surface light source: a surface source of light attribute respectively is set at the quantum well layer upper and lower surfaces; The rink corner is distributed as the luminous field pattern of Lambertian; The emission form is a luminous flux; It is 5000a.u. that the light number is at least 10 luminous fluxes, and total light number is 3000, and minimum light number is 10;
(8) light extraction efficiency of analysis led chip model: utilize the system that clears off of TracePro software, the led chip model is carried out ray tracing, obtain the luminous flux data of top, bottom, side respectively;
(9) collect record data;
(10) optimize pattern parameter, said pattern parameter comprises the geometric parameter of elementary cell and the geometric parameter of basic cell array;
(11) confirm the led chip model.
2. the led chip Model Design method of patterned substrate according to claim 1; It is characterized in that; Step (2) is distributed in the basic body solid matter upper surface of substrate; Be specially: through the filling of the Solidworks software function of arranging the basic body solid matter is distributed in the upper surface of substrate, arrangement mode is that rectanglar arrangement or hexagonal are arranged.
3. the led chip Model Design method of patterned substrate according to claim 1 is characterized in that, the said optical property parameter of step (6) comprises refractive index, temperature setting, absorptivity, extinction coefficient, is directed against the wavelength of light.
4. the led chip Model Design method of patterned substrate according to claim 1; It is characterized in that; The light extraction efficiency of the said analysis substrate of step (8) led chip: the system that clears off that utilizes TracePro software; The led chip model is carried out ray tracing, obtains the luminous flux data of top, bottom, side respectively, be specially:
Utilize the system that clears off of TracePro software; The led chip model is carried out ray tracing; Obtain the luminous flux data of each face from the radiometric analysis figure that utilizes TracePro software to obtain; Wherein the luminous flux data at led chip model top is obtained from the surface 0 radiometric analysis figure of last target surface; The luminous flux data of bottom is obtained from the surface 0 radiometric analysis figure of following target surface, and the ambient light flux data is obtained from the surface 2 radiometric analysis figure of forward and backward target surface and the surface 3 radiometric analysis figure of left and right target surface respectively.
5. the led chip Model Design method of patterned substrate according to claim 1; It is characterized in that; Step (6) is said sets the material and the optical property parameter of material of substrate, N-epitaxial loayer, quantum well layer, the P-epitaxial loayer of led chip respectively, is specially:
Adopt curve fitting method or the direct mode of importing to set the material and the optical property parameter of the material of the substrate of led chip, N-epitaxial loayer, quantum well layer, P-epitaxial loayer respectively.
6. the led chip Model Design method of patterned substrate according to claim 1 is characterized in that, the said optimization pattern parameter of step (10) is specially:
When selected pattern parameter was optimized, this pattern parameter was pressed increasing or decreasing rule value in selected numerical range, and other pattern parameter remains unchanged; For each value of optimised pattern parameter, repeating step (1) ~ (9) obtain the luminous flux data of led chip model, and corresponding pattern parameter value was the optimal value of this pattern parameter when optical property was optimum.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103022302A (en) * | 2012-12-15 | 2013-04-03 | 华南理工大学 | Patterned substrate of pattern improved LED chip and LED chip containing the same |
| CN103035792A (en) * | 2012-12-15 | 2013-04-10 | 华南理工大学 | Optimized light-emitting diode (LED) chip patterned substrate and LED chip |
| CN107808029A (en) * | 2017-09-18 | 2018-03-16 | 华南理工大学 | A kind of analysis method of efficiently light emitting diode (LED) chip with vertical structure n-electrode pattern |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1874012A (en) * | 2005-06-03 | 2006-12-06 | 北京大学 | High-luminance chip of luminescent tube in GaN base, and preparation method |
| CN102157629A (en) * | 2010-12-24 | 2011-08-17 | 长治虹源科技晶体有限公司 | Method for manufacturing graphical sapphire substrate |
| CN102280534A (en) * | 2011-07-06 | 2011-12-14 | 上海蓝光科技有限公司 | Method for preprocessing sapphire substrate to improve LED (light-emitting diode) luminous efficiency |
-
2012
- 2012-05-28 CN CN201210169936.8A patent/CN102682179B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1874012A (en) * | 2005-06-03 | 2006-12-06 | 北京大学 | High-luminance chip of luminescent tube in GaN base, and preparation method |
| CN102157629A (en) * | 2010-12-24 | 2011-08-17 | 长治虹源科技晶体有限公司 | Method for manufacturing graphical sapphire substrate |
| CN102280534A (en) * | 2011-07-06 | 2011-12-14 | 上海蓝光科技有限公司 | Method for preprocessing sapphire substrate to improve LED (light-emitting diode) luminous efficiency |
Non-Patent Citations (1)
| Title |
|---|
| ZHITING LIN,HUI YANG,GUOQIANG LI: "Simulation of highly efficient InGaN-based LEDs with hemispherical patterned sapphire substrates", 《2012 SYMPOSIUM ON PHOTONICS AND OPTOELECTRONICS》 * |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103022302A (en) * | 2012-12-15 | 2013-04-03 | 华南理工大学 | Patterned substrate of pattern improved LED chip and LED chip containing the same |
| CN103035792A (en) * | 2012-12-15 | 2013-04-10 | 华南理工大学 | Optimized light-emitting diode (LED) chip patterned substrate and LED chip |
| CN107808029A (en) * | 2017-09-18 | 2018-03-16 | 华南理工大学 | A kind of analysis method of efficiently light emitting diode (LED) chip with vertical structure n-electrode pattern |
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