CN102681583A - High-precision band-gap reference circuit - Google Patents

Abstract

The invention relates to the field of integrated circuits and aims to reduce influence of offset voltages as much as possible. The technical scheme adopted in the invention is as follows: a high-precision band-gap reference circuit comprises PMOS (P-channel Metal Oxide Semiconductor) tubes P1, P2, P3 and P4, NMOS ((N-channel Metal Oxide Semiconductor) tubes N1 and N2, triodes Q1 and Q2 and ten coms switches, wherein two branch circuits N1 and N2 are connected with a point C and a point D in turn and are also connected with a point A and a point B in turn; or Q1 and Q2 are connected with P1 and P2 in turn. The technical scheme of the invention is mainly applied to the design and the manufacture of the high-precision band-gap reference circuit.

Description

The high precision band-gap reference circuit

Technical field

The present invention relates to integrated circuit fields, relate in particular to the design of the band-gap reference circuit of high precision, low imbalance, specifically, relate to the high precision band-gap reference circuit.

Background technology

Fig. 1 is traditional band-gap reference circuit, and wherein empty frame inside is an amplifier, because Q2 pipe composes in parallel by 8 identical pipes, the electric current that flows through each pipe is total 1/8, then, ${\mathrm{\&Lambda;\; V}}_{\mathrm{BE}}=V_{\mathrm{BE}1}-{\mathrm{<figure-callout\; id="2"\; label="V\; BE"\; filenames="HDA00001692722300012.png"\; state="\{\{state\}\}">V</figure-callout>}}_{\mathrm{BE}}=V_T\mathrm{Ln}\frac{I}{I_{S1}}-V_T\mathrm{Ln}\frac{\mathrm{<figure-callout\; id="2"\; label="I\; NI\; S"\; filenames="HDA00001692722300012.png"\; state="\{\{state\}\}">I</figure-callout>}}{{\mathrm{NI}}_S}=V_T\mathrm{Ln}n$ N=8 wherein.Therefore, reference voltage $V_{\mathrm{Ref}}={\mathrm{<figure-callout\; id="2"\; label="V\; BE"\; filenames="HDA00001692722300012.png"\; state="\{\{state\}\}">V</figure-callout>}}_{\mathrm{BE}}+{2\mathrm{IR}}_s=V_{\mathrm{BE}1}+\frac{{2V}_T\mathrm{Ln}n}{R_n}{R}_s.$ VBE1 has negative temperature coefficient, $V_T=\frac{\mathrm{KT}}{q},$ Have positive temperature coefficient (PTC),

For with the irrelevant amount of temperature coefficient,

Design draws $\frac{{\&PartialD;V}_{\mathrm{Ref}}}{\&PartialD;T}=\frac{{\&PartialD;V}_{\mathrm{BE}1}}{\&PartialD;T}+\frac{{2\mathrm{KR}}_s}{{\mathrm{QR}}_n}\mathrm{Ln}n=0$ Promptly obtain temperature independent reference voltage V _Ref, V _Ref≈ V _BE1+ 17.2V _T≈ 1.23V.

But when the paired metal-oxide-semiconductor in the circuit can not well matched, can produce an offset voltage, thereby need find a scheme to eliminate this offset voltage.

Summary of the invention

The present invention is intended to overcome the deficiency of prior art, reduces the influence of offset voltage as far as possible, for achieving the above object; The technical scheme that the present invention takes is; The high precision band-gap reference circuit, by PMOS pipe P1, P2, P3, P4, NMOS pipe N1, N2; Triode Q1, Q2 form; It is characterized in that the grid of PMOS pipe P1, P2 links to each other, the source electrode of PMOS pipe P1, P2 connects power supply; The drain electrode of PMOS pipe P1 connects the input end of two cmos switches; The output terminal of two cmos switches that the drain electrode of PMOS pipe P1 connects is connected to C point, D point respectively separately, and the negative, positive clock end that is connected to the cmos switch that C order with the drain electrode connection of PMOS pipe P1 and output terminal is corresponding connection pulse signal X2, pulse signal X2 inversion signal respectively, is connected to the corresponding connection pulse signal X2 of positive and negative clock end difference, the pulse signal X2 inversion signal of the cmos switch that D orders with drain electrode connection and output terminal that PMOS manages P1; The output terminal of two cmos switches that the drain electrode of PMOS pipe P2 connects is connected to C point, D point respectively separately; The positive and negative clock end that is connected to the cmos switch that C order with the drain electrode connection of PMOS pipe P2 and output terminal is corresponding connection pulse signal X2, pulse signal X2 inversion signal respectively, and the negative, positive clock end that is connected to the cmos switch that D orders with drain electrode connection and output terminal that PMOS manages P2 is distinguished corresponding connection pulse signal X2, pulse signal X2 inversion signal; Triode Q1, Q2 base stage link to each other and are connected to the C point, and the emitter of triode Q1 is connected to the emitter of triode Q2 through resistance R n, and the emitter of triode Q1 is through resistance R s ground connection; The source electrode of PMOS pipe P3, P4 connects power supply, and the grid of PMOS pipe P3, P4 links to each other, the corresponding respectively source electrode that connects NMOS pipe N1, N2 of the drain electrode of PMOS pipe P3, P4, and the drain electrode of NMOS pipe N1, N2 links to each other and through resistance R t ground connection;

The output terminal of two cmos switches that the drain electrode of PMOS pipe P3 connects is connected to A point, B point respectively separately; The negative, positive clock end that is connected to the cmos switch that A order with the drain electrode connection of PMOS pipe P3 and output terminal is corresponding connection pulse signal X1, pulse signal X1 inversion signal respectively, and the positive and negative clock end that is connected to the cmos switch that B orders with drain electrode connection and output terminal that PMOS manages P3 is distinguished corresponding connection pulse signal X1, pulse signal X1 inversion signal;

The output terminal of two cmos switches that the drain electrode of PMOS pipe P4 connects is connected to A point, B point respectively separately; The positive and negative clock end that is connected to the cmos switch that A order with the drain electrode connection of PMOS pipe P4 and output terminal is corresponding connection pulse signal X1, pulse signal X1 inversion signal respectively, and the negative, positive clock end that is connected to the cmos switch that B orders with drain electrode connection and output terminal that PMOS manages P3 is distinguished corresponding connection pulse signal X1, pulse signal X1 inversion signal;

The output terminal of two cmos switches that the drain electrode of NMOS pipe N1 connects is connected to C point, D point respectively separately; The negative, positive clock end that is connected to the cmos switch that C order with the drain electrode connection of NMOS pipe N1 and output terminal is corresponding connection pulse signal X1, pulse signal X1 inversion signal respectively, and the positive and negative clock end that is connected to the cmos switch that D orders with drain electrode connection and output terminal that NMOS manages N1 is distinguished corresponding connection pulse signal X1, pulse signal X1 inversion signal;

The output terminal of two cmos switches that the drain electrode of NMOS pipe N2 connects is connected to C point, D point respectively separately; The positive and negative clock end that is connected to the cmos switch that C order with the drain electrode connection of NMOS pipe N2 and output terminal is corresponding connection pulse signal X1, pulse signal X1 inversion signal respectively, and the negative, positive clock end that is connected to the cmos switch that D orders with drain electrode connection and output terminal that NMOS manages N2 is distinguished corresponding connection pulse signal X1, pulse signal X1 inversion signal;

A, B, C, D point are respectively PMOS pipe P1, P3 grid, triode Q1, Q2 collector.

The structure of cmos switch is: PMOS pipe source electrode links to each other with a NMOS pipe source electrode and as input end, drain electrode links to each other and as output terminal, gate pmos is very born clock end, and the NMOS tube grid is positive clock end.

Technical characterstic of the present invention and effect:

The present invention utilizes the two divided-frequency clock that each device is alternately connected, make offset voltage that each device produces in some cycles equal and opposite in direction, in the opposite direction, the duration is identical, can reach the purpose of eliminating offset voltage.

Description of drawings

Fig. 1. traditional band-gap reference circuit.

Fig. 2. the band-gap reference circuit after the optimization.

Fig. 3. the two divided-frequency clock waveform.

The inner structure of Fig. 4 .CMOS switch.

Fig. 5. inverter circuit.

Embodiment

Fig. 2 is the band-gap reference circuit structure after optimizing.Wherein X1 and X2 are the two divided-frequency clock, and its oscillogram is as shown in Figure 3, and the X1 cycle is 1us, and the X2 cycle is 2us.Fig. 4 is the inner structure of cmos switch.Fig. 5 is the circuit structure of phase inverter.

Can find out by Fig. 2 that like this in X1 cycle change procedure, N1 is connected with the D point with the C point with N2 in turn, and two branch roads of N1 and N2 are connected with the B point with the A point in turn.Simultaneously, in X2 cycle change procedure, Q1 is connected with P2 with P1 with Q2 in turn.

So design when producing mismatch in the circuit, also is that periodically height changes to output voltage influence, can regard stationary value as through behind the follow-up filtering circuit.

Table 1 is each MOS size of devices in the circuit shown in Figure 2.

Table 2 is the resistance of each resistance in the circuit shown in Figure 2.

Table 3 is the device size of circuit shown in Figure 4.

Table 4 is the device size of circuit shown in Figure 5.

When supply voltage was 1.5V, output voltage stabilization was at 1.232V, and at this moment Q1 and Q2 branch current are 14.33uA, and the N1 branch current is 537.9nA, and the N2 branch current is 619.2nA.

When supply voltage is that 3.3V is, output voltage stabilization is at 1.232V, and at this moment Q1 and Q2 branch current are 14.24uA, and the N1 branch current is 579.3nA, and the N2 branch current is 638.9nA.

When P1 reduces 10%, utilize Fig. 1 circuit structure output voltage values to be 1.175V, utilize Fig. 2 circuit structure output voltage values to be 1.232V.

When P1 increases by 10%, utilize Fig. 1 circuit structure output voltage values to be 1.287V, utilize Fig. 2 circuit structure output voltage values to be 1.234V.

This shows, utilize circuit structure shown in the present can obviously suppress offset voltage.

. table 1

Title

W

L

M

Title

W

L

M

P1

20u

0.4u

4

Q1

1u

1u

1

P2

20u

0.4u

4

Q2

1u

1u

8

P3

10u

1u

3

N1

5u

0.35u

2

P4

10u

1u

3

N2

5u

0.35u

2

Table 2

Title	Resistance (unit: ohm)
		Rs	17500
Rn	3700
		Rt	600000

Table 3

Title	W	L	M
				P9	5u	0.35u	2
N9	5u	0.35u	2

Table 4

Title	W	L	M
				P10	1.6u	0.35u	1
N10	1u	0.35u	1

Claims (2)

1. high precision band-gap reference circuit; By PMOS pipe P1, P2, P3, P4; NMOS pipe N1, N2, triode Q1, Q2 form, and it is characterized in that; The grid of PMOS pipe P1, P2 links to each other; The source electrode of PMOS pipe P1, P2 connects power supply, and the drain electrode of PMOS pipe P1 connects the input end of two cmos switches, and the output terminal of two cmos switches that the drain electrode of PMOS pipe P1 connects is connected to C point, D point respectively separately; The negative, positive clock end that is connected to the cmos switch that C order with the drain electrode connection of PMOS pipe P1 and output terminal is corresponding connection pulse signal X2, pulse signal X2 inversion signal respectively, and the positive and negative clock end that is connected to the cmos switch that D orders with drain electrode connection and output terminal that PMOS manages P1 is distinguished corresponding connection pulse signal X2, pulse signal X2 inversion signal; The output terminal of two cmos switches that the drain electrode of PMOS pipe P2 connects is connected to C point, D point respectively separately; The positive and negative clock end that is connected to the cmos switch that C order with the drain electrode connection of PMOS pipe P2 and output terminal is corresponding connection pulse signal X2, pulse signal X2 inversion signal respectively, and the negative, positive clock end that is connected to the cmos switch that D orders with drain electrode connection and output terminal that PMOS manages P2 is distinguished corresponding connection pulse signal X2, pulse signal X2 inversion signal; Triode Q1, Q2 base stage link to each other and are connected to the C point, and the emitter of triode Q1 is connected to the emitter of triode Q2 through resistance R n, and the emitter of triode Q1 is through resistance R s ground connection; The source electrode of PMOS pipe P3, P4 connects power supply, and the grid of PMOS pipe P3, P4 links to each other, the corresponding respectively source electrode that connects NMOS pipe N1, N2 of the drain electrode of PMOS pipe P3, P4, and the drain electrode of NMOS pipe N1, N2 links to each other and through resistance R t ground connection;

The output terminal of two cmos switches that the drain electrode of PMOS pipe P3 connects is connected to A point, B point respectively separately; The negative, positive clock end that is connected to the cmos switch that A order with the drain electrode connection of PMOS pipe P3 and output terminal is corresponding connection pulse signal X1, pulse signal X1 inversion signal respectively, and the positive and negative clock end that is connected to the cmos switch that B orders with drain electrode connection and output terminal that PMOS manages P3 is distinguished corresponding connection pulse signal X1, pulse signal X1 inversion signal;

The output terminal of two cmos switches that the drain electrode of PMOS pipe P4 connects is connected to A point, B point respectively separately; The positive and negative clock end that is connected to the cmos switch that A order with the drain electrode connection of PMOS pipe P4 and output terminal is corresponding connection pulse signal X1, pulse signal X1 inversion signal respectively, and the negative, positive clock end that is connected to the cmos switch that B orders with drain electrode connection and output terminal that PMOS manages P3 is distinguished corresponding connection pulse signal X1, pulse signal X1 inversion signal;

The output terminal of two cmos switches that the drain electrode of NMOS pipe N1 connects is connected to C point, D point respectively separately; The negative, positive clock end that is connected to the cmos switch that C order with the drain electrode connection of NMOS pipe N1 and output terminal is corresponding connection pulse signal X1, pulse signal X1 inversion signal respectively, and the positive and negative clock end that is connected to the cmos switch that D orders with drain electrode connection and output terminal that NMOS manages N1 is distinguished corresponding connection pulse signal X1, pulse signal X1 inversion signal;

The output terminal of two cmos switches that the drain electrode of NMOS pipe N2 connects is connected to C point, D point respectively separately; The positive and negative clock end that is connected to the cmos switch that C order with the drain electrode connection of NMOS pipe N2 and output terminal is corresponding connection pulse signal X1, pulse signal X1 inversion signal respectively, and the negative, positive clock end that is connected to the cmos switch that D orders with drain electrode connection and output terminal that NMOS manages N2 is distinguished corresponding connection pulse signal X1, pulse signal X1 inversion signal;

A, B, C, D point are respectively PMOS pipe P1, P3 grid, triode Q1, Q2 collector.

2. high precision band-gap reference circuit as claimed in claim 1; It is characterized in that the structure of cmos switch is: PMOS pipe source electrode links to each other with a NMOS pipe source electrode and as input end, and drain electrode is continuous and as output terminal; The very negative clock end of gate pmos, the NMOS tube grid is positive clock end.

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