CN102662902A - Method, device and system for preventing I2C (inter-integrated circuit) bus locking - Google Patents
Method, device and system for preventing I2C (inter-integrated circuit) bus locking Download PDFInfo
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Abstract
The invention discloses a method, a device and a system for preventing I2C (inter-integrated circuit) bus locking. An externally transmitted reset signal to an I2C master device is acquired by a reset signal acquisition module which is connected with the I2C master device, and after the reset signal is acquired, the I2C master device needs resetting; and then a control module effectively connected an I2C bus transmits preset termination signal to the I2C bus to finish current unfinished operation on the I2C bus, so that the I2C master device is prevented from being locked due to a communication terminal in resetting, misoperation of an I2C slave device in recovering I2C bus communication is avoided, and operational reliability and stability of the system are improved.
Description
Technical field
The present invention relates to electronic communication control field, be specifically related to a kind of method, Apparatus and system of the I2C of preventing lock bus.
Background technology
I2C (Inter-Integrated Circuit) bus is by the twin wire universal serial bus of PHILIPS company exploitation, is used to connect microcontroller and peripherals thereof.It is a kind of bus standard that extensively adopt in microelectronics Control on Communication field.It is a kind of special shape of synchronous communication, and it is few to have an interface line, and control mode is simple, and the device package form is little, and traffic rate is than advantages such as height.Computing machine manufacturing, telecommunication apparatus, fields such as consumer electronics have been widely used at present.
In I2C bussing technique standard, bus protocol has strict sequential requirement.During bus work,, transmit data by bidirectional data line SDA by the pulse of the control of the main device on bus clock line SCL transmission clock.The data word joint number of each transmission is unrestricted on the I2C bus, but each byte is necessary for 8, and the byte of each transmission back must follow an authorization bit (the 9th) from device, also is response bits (ACK, Acknowledge bit)
In the I2C bussing technique standard, beginning and end signal (also claiming the initial sum stop signal) define as follows:
Start signal (S): keep between high period at clock line SCL, bidirectional data line SDA appearance to low level variation, is used to start the I2C bus by high level, is the start signal of I2C bus;
Stop signal (P): keep between high period at clock line SCL, bidirectional data line SDA occurs being used to stop the I2C bus by the variation of low level to high level, is the termination signal of I2C bus;
Answer signal (A): the corresponding response bits of the 9th pulse of I2C bus, show that low level then " replys " (A) for bus if bidirectional data line SDA goes up, if bidirectional data line SDA go up show high level then be " non-replying " (/A).
Beginning generally all is to be produced by main device with end signal, has only main device to realize management and detection to the I2C bus, as initial, stop, tranmitting data register etc.During the transmission of I2C bus data, between clock line SCL high period, must maintain stable logic level state on the data line SDA, high level is data 1, and low level is data 0.Only when clock line was low level, just allowing the operating rate of the level state variation I2C bus on the data line generally was the performance that depends on primary controller, and with reference to the bus specification of I2C, the frequency of operation of clock line SCL can be low to moderate 0Hz.
The I2C bus can not lock under the situation of proper communication, but when system reset, if the I2C main device also is in the communication process; And this moment SDA just by the time from device drive, the clock because the back main device that resets is not redispatched so, SDA is given from device to move fixed level to; If SDA is low level at this moment, after main device resets so, can think always that the I2C bus is busy; And then can't be to from device operation; And can't withdraw from this state automatically from device, and cause the I2C bus to be hung up, need human intervention to recover the normal sequential of bus.
At present each tame chip producer provides some solutions over against this situation; For example can detect SCL from device; In certain hour, finish this operation without clock; But all variant between numerous each producers of I2C device, this just needs an additional control device, unified addressing this problem.
For the recovery of I2C locking, the main method that adopts at present has two kinds:
Detect the SDA state when 1, resetting,, go up 9 clocks of output toward SCL if be low.
This method realizes relatively simple; Also can remove the state of lock bus; If but sequential is reset in certain location, can cause toward from device write error data, owing to generally do not have reset function from device; This mistake is lifted device EEPROM AT24C04 instance analysis commonly used below and is write situation once by mistake with the operate as normal that may influence system.
Fig. 1 is the SDA sequential of a byte write operation, Fig. 2 be a byte with machine-readable SDA sequential, on two figure, have 1 ACK mark one indicate line; Can see that at first the sequential of read and write all is identical, if after main device resets from beginning to indicating line; Just in time be in the sign line from the device sequential, send ACK and wait for the response of main device clock, can drag down data line from device so always; Wait for the clock that main device sends, at this moment anti-locking device detects SDA and drags down, and on SCL, sees 9 clocks off; Finish response from device behind the 1st clock and discharge SDA, 8 the clock reference Fig. 1 in back are actually and have write FF or 00 toward the current address (the acquiescence level that depends on main device SDA pin output under reset mode is if 1 or three-state; Write FF, if 0, write 00); Because EEPROM preserves some configuration informations through regular meeting, this maloperation probably causes the unusual of system, and sequential does not finish behind other 9 clocks; The back main device that resets operate for the first time and during last reset residual operation be spliced into wrong sequential, also can cause operation failure for the first time; Have only to main device and send a STOP, could recover normal.
Detect the SDA state when 2, resetting, if be low, go up 1 clock of output, and then detect the SDA state,, move in circles, uprise up to SDA if send a clock again for low toward SCL.
This method is compared first kind and is wanted complicated a lot, can avoid the operation write from the device mistake, uprises and is not necessarily to have discharged SDA from device but detect SDA; Might be when read data, to have sent one 1 from device, if at this moment just stop to send clock, SDA or quilt be from device drive so; The back main device START when initiating I2C operation for the first time that resets can't normally send; The failure certainly of operation for the first time has only after STOP such as transmission such as the main device of grade, just can discharge SDA from device.This in addition method also exists, the back main device that resets operate for the first time and during last reset residual operation be spliced into wrong sequential, cause the problem of operation failure for the first time
Therefore, a kind of method that prevents the I2C lock bus of a kind of new control be badly in need of to be proposed, avoid occurring in the I2C main device reseting procedure that the I2C bus is locked and when recovering the I2C bus maloperation I2C from situation such as devices.
Summary of the invention
The technical problem underlying that the present invention will solve is; A kind of method, Apparatus and system of the I2C of preventing lock bus are provided; Avoid the blocked situation generation of I2C bus in the I2C main device reseting procedure; Proper operation when guaranteeing to recover the I2C bus communication, the reliability and stability of raising system works.
For solving the problems of the technologies described above, the present invention provides a kind of device of the I2C of preventing lock bus, comprising:
The reset signal acquisition module is connected with the I2C main device, is used to obtain the reset signal that the external world sends to said I2C main device;
Control module effectively is connected with the I2C bus, is used for after said reset signal acquisition module gets access to said reset signal, sends preset termination signal and finishes current not end operation on the said I2C bus to said I2C bus.
In an embodiment of the present invention, said I2C bus comprises serial time clock line and bidirectional serial data lines, and the clock control line that said control module comprises is connected with bidirectional serial data lines with the serial clock bus of said I2C bus respectively with data line.
In an embodiment of the present invention, said preset termination signal comprises the pulse of at least 10 specific time sequence.
In an embodiment of the present invention, said preset termination signal is the pulse of 10 specific time sequence, and said characteristic sequential is that pulse and the phase differential of the pulse on the bidirectional serial data lines on the serial clock bus is T/4, and said T is the recurrence interval.
The present invention also provides a kind of system of the I2C of preventing lock bus, comprises that I2C main device and at least one I2C that is connected with said I2C main device through the I2C bus from device, also comprise the device that is used to prevent the I2C lock bus;
Said I2C main device is used to receive extraneous reset signal of sending;
Said device comprises: the reset signal acquisition module, be connected with said I2C main device, and be used to obtain the reset signal that the external world sends to said I2C main device;
Control module effectively is connected with said I2C bus, is used for after said reset signal acquisition module gets access to said reset signal, sends preset termination signal and finishes current not end operation on the said I2C bus to said I2C bus.
In an embodiment of the present invention, said I2C bus comprises serial time clock line and bidirectional serial data lines, and the clock control line that said control module comprises is connected with bidirectional serial data lines with the serial clock bus of said I2C bus respectively with data line.
In an embodiment of the present invention, said preset termination signal comprises the pulse of at least 10 specific time sequence.
In an embodiment of the present invention, said preset termination signal is the pulse of 10 specific time sequence, and said characteristic sequential is that pulse and the phase differential of the pulse on the bidirectional serial data lines on the serial clock bus is T/4, and said T is the recurrence interval.
The present invention also provides a kind of method of the I2C of preventing lock bus, comprising:
Detect the I2C main device and whether receive the extraneous reset signal of sending;
Receive the extraneous reset signal of sending if detect the I2C main device, then send preset termination signal and finish current not end operation on the said I2C bus to the I2C bus.
In an embodiment of the present invention, said preset termination signal comprises the pulse of at least 10 specific time sequence.
In an embodiment of the present invention, said preset termination signal is the pulse of 10 specific time sequence, and said characteristic sequential is that pulse and the phase differential of the pulse on the bidirectional serial data lines on the serial clock bus is T/4, and said T is the recurrence interval.
The invention has the beneficial effects as follows: the present invention obtains the reset signal that the external world sends to the I2C main device through the reset signal acquisition module that is connected with the I2C main device, get access to this reset signal after, show that the I2C main device will carry out reset operation; Finish current not end operation on this I2C bus through sending preset termination signal to the I2C bus then with the control module that the I2C bus effectively is connected; Avoid the I2C main device in reseting procedure, to cause communication terminal to cause that the blocked situation of I2C bus takes place; When having avoided recovery I2C bus communication I2C is carried out maloperation from device, improved the reliability and stability of system works.
Description of drawings
Fig. 1 is the SDA sequential chart of a kind of byte write operation of the present invention;
Fig. 2 is that a kind of byte of the present invention is with machine-readable SDA sequential chart;
Fig. 3 is the structured flowchart of the system that prevents the I2C lock bus of an embodiment of the present invention;
Fig. 4 is the structured flowchart of the device that prevents the I2C lock bus of an embodiment of the present invention;
Fig. 5 is the pulse synoptic diagram of the specific time sequence of an embodiment of the present invention;
Fig. 6 is the process flow diagram of the method that prevents the I2C lock bus of an embodiment of the present invention.
Embodiment
Combine accompanying drawing that the present invention is done further explain through embodiment below.
Please refer to Fig. 3; The system that prevents the I2C lock bus that provides in the present embodiment comprises that I2C main device and at least one I2C that is connected with said I2C main device through the I2C bus are from device; I2C also can comprise polytype from device, also comprises the device that is used to prevent the I2C lock bus; Wherein,
The I2C main device can be used for receiving extraneous reset signal of sending;
See also Fig. 4, being used in the present embodiment prevents that the device of I2C lock bus from specifically comprising:
The reset signal acquisition module is connected with the I2C main device, is used to obtain the reset signal that the external world sends to the I2C main device;
Control module effectively is connected with the I2C bus, is used for after the reset signal acquisition module gets access to reset signal, sends preset termination signal and finishes current not end operation on the I2C bus to the I2C bus.Be that embodiment is mainly through increasing a device that is used to prevent the I2C lock bus on the I2C bus; The reset signal of monitoring I2C main device; When finding that main device is reset, see the termination signal of setting off, finish the I2C bus operation that possibly interrupt on the I2C bus.
Controller at the reseting period main device generally all is high resistant output; And generally all do not have reseting pin from device; Therefore also can't be reset by the perception main device, be used in this state prevent that the device of I2C lock bus from can simulate main device fully to operating from device.Avoid the I2C main device in reseting procedure, to cause communication terminal to cause that the blocked situation of I2C bus takes place, in the time of can avoiding recovering the I2C bus communication I2C is carried out maloperation from device, improve the reliability and stability of system works.
Concrete, being used in the present embodiment can realize through specific hardware circuit or programming device at the reset signal acquisition module; The I2C bus comprises serial time clock line SCL and bidirectional serial data lines SDA; The control module that the above-mentioned device that is used to prevent the I2C lock bus comprises comprises clock control line and data line; And be connected with bidirectional serial data lines with the serial clock bus of I2C bus respectively; With when the I2C main device resets, send preset termination signal on the I2C bus.
Because each transmits byte back I2C and must follow an authorization bit from device on the I2C bus; Therefore can think that the length of each byte on the I2C bus is 9; And then can know that I2C needs maximum 9 termination signal STOP could discharge bidirectional serial data lines SDA from device; Based on above-mentioned analysis, the preset termination signal in the present embodiment comprises the pulse of at least 10 specific time sequence, and specifically can be preferably preset termination signal is the pulse of 10 specific time sequence; See also Fig. 5; This specific time sequence is that the pulse of SCL on the serial clock bus and the phase differential of the pulse on the bidirectional serial data lines SDA are T/4, and this T is the recurrence interval, and the phase place that is specially the pulse of SCL on the serial clock bus shifts to an earlier date T/4 than the phase place of the pulse on the bidirectional serial data lines SDA.When I2C when device needs maximum 9 termination signal STOP could discharge bidirectional serial data lines SDA, when the pulse of the 10th specific time sequence from response device, this EO.
By on can know; If need the individual clock of N (0＜N＜10) to discharge SDA from device, SDA is for from device being output within that N clock so, and top n STOP just equivalence is a N clock; N+1 STOP is from response device; Bus operation finishes, if the back also has STOP, to not influence of bus.Therefore the pulse number of the specific time sequence that comprises of the preset termination signal in the present embodiment specifically can be selected according to actual conditions, is not to be fixed as above-mentioned 10.
For a better understanding of the present invention, the present invention is further specified, sees also Fig. 6 below in conjunction with the concrete grammar that prevents the I2C lock bus:
Step 61: detect the I2C main device and receive the extraneous reset signal of sending;
Step 62: send above-mentioned preset termination signal (being pulse signal shown in Figure 5) and finish current not end operation on the said I2C bus to the I2C bus.
The state of I2C bus need not monitored or consider to method in the present embodiment, and realization flow is simpler, cost is lower, is that example is done further brief description with various situation below:
The I2C bus is idle when 1, resetting, and does not have ongoing read-write operation:
In this case, 10 STOP are to having no influence from device, and it is idle that bus keeps
The I2C bus is communicated by letter when 2, resetting, and SDA is driven by main device:
This situation from first STOP of response device, finishes last operation, and follow-up STOP does not respond, and it is idle that bus keeps.
3 buses of I2C when resetting are communicated by letter, and SDA is by from device drive:
Here being height or low regardless of the SDA from device drive, all is output for SDA from device, and supposing needs 9 maximum clocks ability release data lines from device; Preceding 9 STOP of sending of control module so are for saying from device, because SDA is output from device; Actual is 9 clocks with regard to equivalence, discharges SDA from device behind such 9 STOP, and at this moment last the 10th STOP is from response device; This EO, bus keep idle.
Step 63: EO.
Whether the present invention will carry out reset operation through the reset signal acquisition module monitoring I2C main device that is connected with the I2C main device; In this way; Finish current not end operation on this I2C bus through sending preset termination signal to the I2C bus with the control module that the I2C bus effectively is connected; Avoid the I2C main device in reseting procedure, to cause communication terminal to cause that the blocked situation of I2C bus takes place; In the time of can avoiding recovering the I2C bus communication I2C is carried out maloperation from device, and then improve the reliability and stability of system works.
Above content is to combine concrete embodiment to the further explain that the present invention did, and can not assert that practical implementation of the present invention is confined to these explanations.For the those of ordinary skill of technical field under the present invention, under the prerequisite that does not break away from the present invention's design, can also make some simple deduction or replace, all should be regarded as belonging to protection scope of the present invention.
Claims (11)
1. device that prevents the I2C lock bus is characterized in that comprising:
The reset signal acquisition module is connected with the I2C main device, is used to obtain the reset signal that the external world sends to said I2C main device;
Control module effectively is connected with the I2C bus, is used for after said reset signal acquisition module gets access to said reset signal, sends preset termination signal and finishes current not end operation on the said I2C bus to said I2C bus.
2. prevent the device of I2C lock bus according to claim 1; It is characterized in that; Said I2C bus comprises serial time clock line and bidirectional serial data lines, and the clock control line that said control module comprises is connected with bidirectional serial data lines with the serial clock bus of said I2C bus respectively with data line.
3. according to claim 1 or claim 2 the device that prevents the I2C lock bus is characterized in that said preset termination signal comprises the pulse of at least 10 specific time sequence.
4. the device that prevents the I2C lock bus as claimed in claim 3; It is characterized in that; Said preset termination signal is the pulse of 10 specific time sequence, and said characteristic sequential is that pulse and the phase differential of the pulse on the bidirectional serial data lines on the serial clock bus is T/4, and said T is the recurrence interval.
5. a system that prevents the I2C lock bus is characterized in that, comprises that I2C main device and at least one I2C that is connected with said I2C main device through the I2C bus from device, also comprise the device that is used to prevent the I2C lock bus;
Said I2C main device is used to receive extraneous reset signal of sending;
Said device comprises: the reset signal acquisition module, be connected with said I2C main device, and be used to obtain the reset signal that the external world sends to said I2C main device;
Control module effectively is connected with said I2C bus, is used for after said reset signal acquisition module gets access to said reset signal, sends preset termination signal and finishes current not end operation on the said I2C bus to said I2C bus.
6. like the said system that prevents the I2C lock bus of claim 5; It is characterized in that; Said I2C bus comprises serial time clock line and bidirectional serial data lines, and the clock control line that said control module comprises is connected with bidirectional serial data lines with the serial clock bus of said I2C bus respectively with data line.
7. like claim 5 or the 6 described systems that prevent the I2C lock bus, it is characterized in that said preset termination signal comprises the pulse of at least 10 specific time sequence.
8. the system that prevents the I2C lock bus as claimed in claim 7; It is characterized in that; Said preset termination signal is the pulse of 10 specific time sequence, and said characteristic sequential is that pulse and the phase differential of the pulse on the bidirectional serial data lines on the serial clock bus is T/4, and said T is the recurrence interval.
9. method that prevents the I2C lock bus is characterized in that comprising:
Detect the I2C main device and whether receive the extraneous reset signal of sending;
Receive the extraneous reset signal of sending if detect the I2C main device, then send preset termination signal and finish current not end operation on the said I2C bus to the I2C bus.
10. the method that prevents the I2C lock bus as claimed in claim 9 is characterized in that said preset termination signal comprises the pulse of at least 10 specific time sequence.
11. the method that prevents the I2C lock bus as claimed in claim 10; It is characterized in that; Said preset termination signal is the pulse of 10 specific time sequence; Said characteristic sequential is that pulse and the phase differential of the pulse on the bidirectional serial data lines on the serial clock bus is T/4, and said T is the recurrence interval.
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| CN201210090362.5A CN102662902B (en) | 2012-03-30 | 2012-03-30 | Method, device and system for preventing I2C (inter-integrated circuit) bus locking |
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| CN201210090362.5A CN102662902B (en) | 2012-03-30 | 2012-03-30 | Method, device and system for preventing I2C (inter-integrated circuit) bus locking |
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| CN103810132A (en) * | 2014-03-07 | 2014-05-21 | 福州瑞芯微电子有限公司 | Bus multi-bit separate control circuit and design and control method thereof |
| CN106326163A (en) * | 2016-08-16 | 2017-01-11 | 深圳天珑无线科技有限公司 | Data transfer system and transfer method |
| CN110908841A (en) * | 2019-12-03 | 2020-03-24 | 锐捷网络股份有限公司 | I2C communication abnormity recovery method and device |
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| CN102662902B (en) | 2015-05-13 |
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