CN102662812A

CN102662812A - Performance testing system for PCI (peripheral Component Interconnect) bus-based single-way reception demodulator

Info

Publication number: CN102662812A
Application number: CN2012101045477A
Authority: CN
Inventors: 吴伟林; 税成侠; 肖跃先; 姜维; 宋慧
Original assignee: Chengdu Linhai Electronics Co Ltd
Current assignee: Chengdu Linhai Electronics Co Ltd
Priority date: 2012-04-11
Filing date: 2012-04-11
Publication date: 2012-09-12
Anticipated expiration: 2032-04-11
Also published as: CN102662812B

Abstract

The invention discloses a performance testing system for a PCI (peripheral Component Interconnect) bus-based single-way reception demodulator. The performance testing system comprises a received signal input-output circuit, wherein the received signal input-output circuit is connected with a test interface signal logic circuit provided with an FPGA (field programmable gate array); the FPGA is connected with an FPGA logic information static storage circuit; the test interface signal logic circuit is connected with a PCI protocol interface circuit; a computer is provided with a PCI slot; and the PCI protocol interface circuit is connected with the computer and a PCI interface configuration circuit. According to the performance testing system for the PCI bus-based single-way reception demodulator, the debugging speed of the single-way reception demodulator is greatly accelerated, the development period of the single-way reception demodulator is shortened and the integration degree of a circuit board and the performance of the system are improved.

Description

Based on pci bus single channel receiving demodulation device Performance Test System

Technical field

The present invention relates to the VSAT satellite communication field, particularly a kind of based on pci bus single channel receiving demodulation device Performance Test System.

Background technology

Pci bus is the computer bus that a kind of compatibility is very strong, function is very complete.Pci bus can be supported many group peripherals simultaneously; And be not limited by processor; The data path of high-performance, high-throughput is provided for CPU and high-speed peripheral; Therefore pci bus has become the new standard of local bus, and pci bus is extensively applied to the communications field and computer realm as interface.

The wherein a kind of utilization of pci bus in the VSAT satellite communication field be, pci bus applies in the single channel receiving demodulation device as interface, and for example LH-2 receiving demodulation device is exactly the single channel receiving demodulation device based on pci bus that adopts.Based on pci bus single channel receiving demodulation device is the important component part of LH-2 receiving demodulation device system; For the receiving system of LH-2 receiving demodulation device system is verified; Need carry out the long-time running examination to receiving system, each subsystem of LH-2 receiving demodulation device system is carried out single machine test and online testing, verify the matching of each subsystem and other subsystem interface; Also to import, and then simulation running environment is provided simultaneously for receiving system provides physical connection interface, dynamic parameter.

As shown in Figure 1; Principle based on the single channel receiving demodulation device of pci bus is: the analog if signal that transmits from intermediate frequency processor becomes digital intermediate frequency signal through high-precision analog to digital converter; In digital down converter, digital intermediate frequency signal is carried out down coversion, filtering and extraction; Send into the demodulation of carrying out digital signal in the PLD FPGA then; Obtain the numerical information of needs at last,, the digital data transmission after handling is carried out analyzing and processing to main frame at last through pci bus interface.

Demodulation based on the single channel receiving demodulation device of pci bus is in FPGA, to realize, so can in-circuit emulation realize the performance based on the single channel receiving demodulation device of pci bus is tested.

Summary of the invention

The purpose of this invention is to provide and a kind ofly utilize this test macro to carry out performance test, can increase substantially debugging speed, shorten the construction cycle, improve the integrated level of circuit board and the performance of system based on pci bus single channel receiving demodulation device Performance Test System.

In order to realize the foregoing invention purpose, the invention provides following technical scheme:

Based on pci bus single channel receiving demodulation device Performance Test System; This system comprises the reception signal input and output circuit; Said reception signal input and output circuit connects the test interface signal logic circuit; Said test interface signal logic circuit comprises FPGA and peripheral circuit (following live road, crystal oscillating circuit, power circuit) thereof; Said test interface signal logic circuit connects PCI protocol interface circuit, and said PCI protocol interface circuit is connected with the computing machine of PCI slot, and said PCI protocol interface circuit also is connected with the pci interface configuration circuit; Said pci interface configuration circuit is configured the PCI configuration register and the local configuration register of PCI protocol interface circuit; Said PCI protocol interface circuit provides high performance pci bus interface for the test interface signal logic circuit, and said test interface signal logic circuit communicates through pci bus interface and computing machine, and said test interface signal logic circuit also is connected with fpga logic information static memory circuit.

Utilize above-mentioned Performance Test System, realize performance test, at first write in the computing machine in logical message with demodulator circuit based on pci bus single channel receiving demodulation device; Carry out emulation, whether the verifying logic relation is correct, can be through compiling then this logical message; Otherwise this logical message is incorrect; Logical message after the emulation is correctly carried out comprehensive post-simulation, and input clock signal is observed simulation result; Carry out placement-and-routing after simulation result is correct, and whether checking placement-and-routing is correct, input clock signal is observed simulation result; If simulation result is correct; With the file that generates after the placement-and-routing through among the FPGA that is loaded on the test interface signal logic circuit; Through receiving the signal input and output circuit input signal to the FPGA demodulation; Utilize simulation software to measure the exchange of the digital signal of imput output circuit, whether the output signal is consistent with simulation result after the observation demodulation, and whether logical message is correct during the checking real work; If correct, then logical sequence information is loaded on fpga logic information static memory circuitry stores from FPGA.

Compared with prior art, beneficial effect of the present invention: the present invention is based on pci bus single channel receiving demodulation device performance test methods and system; Utilize the in-circuit emulation function of FPGA to realize in-circuit emulation; When simulation result is incorrect, carry out online modification; Increased substantially based on pci bus single channel receiving demodulation device debugging speed, shortened, improved the integrated level of circuit board and the performance of system based on the pci bus single channel receiving demodulation device construction cycle.

Description of drawings:

Fig. 1 is the theory diagram based on the single channel receiving demodulation device of pci bus.

Fig. 2 is based on pci bus single channel receiving demodulation device Performance Test System block diagram.

Embodiment

Below in conjunction with Test Example and embodiment the present invention is made further detailed description.But should this be interpreted as that the scope of the above-mentioned theme of the present invention only limits to following embodiment, allly all belong to scope of the present invention based on the technology that content of the present invention realized.

As shown in Figure 2, based on pci bus single channel receiving demodulation device Performance Test System block diagram.This test macro comprises reception signal input and output circuit, fpga logic information static memory circuit, test interface signal logic circuit, computing machine, PCI protocol interface circuit, pci interface configuration circuit; Said reception signal input and output circuit connects the test interface signal logic circuit; Said test interface signal logic circuit comprises FPGA and peripheral circuit (following live road, crystal oscillating circuit, power circuit etc.) thereof; Fpga logic information static memory circuit is connected with FPGA; Said test interface signal logic circuit connects PCI protocol interface circuit; Said computing machine is provided with the PCI slot, and said PCI protocol interface circuit is connected with computing machine, and PCI protocol interface circuit also is connected with the pci interface configuration circuit.

Said PCI protocol interface circuit provides high performance pci bus interface for the test interface signal logic circuit; Said test interface signal logic circuit communicates through pci bus interface and computing machine; PCI protocol interface circuit is provided by pci bus interface chip 9054; The PCI configuration register and the local configuration register of said pci bus interface chip 9054 are provided with by the pci interface configuration circuit, and the pci interface configuration circuit is provided by 93CS46N Serial E EROM chip.

Utilization realizes the performance test based on pci bus single channel receiving demodulation device based on pci bus single channel receiving demodulation device Performance Test System, and its step is following:

Step 1: logic, the time sequence information of demodulator circuit are write in the computing machine, use the ISE of simulation software that this demodulator circuit logical message is carried out preceding emulation, promptly select compilation facility in the simulation software; Whether the logical relation of this demodulator circuit logical message of checking input correct, if during emulation through compiling, then logical relation is correct; If logical relation is incorrect; Then can not then need revise the logical sequence information of input through the compilation facility of simulation software during emulation, pass through until compiling;

Step 2: if logical relation is correct, then carry out complex optimum, promptly the comprehensive function through ISE software is converted into concrete circuit diagram with logic, time sequence information; Carry out the complex optimum post-simulation then, select the analog functuion of ISE software, input clock signal is observed simulation result; If simulation result is correct, then get into step 3; If simulation result is incorrect, check then whether complex optimum is correct, if complex optimum is incorrect, then carry out complex optimum again, if complex optimum is correct, then logical sequence information is made amendment, return step 1;

Step 3: carry out placement-and-routing and placement-and-routing's post-simulation, the logic netlist of comprehensive back output is translated into the bottom document and the hardware primitive of selected device, this logical message is mapped on the concrete device architecture unit, realize placement-and-routing; Select the analog functuion of ISE software, input clock signal is observed simulation result; If placement-and-routing's post-simulation is correct, then get into step 4, if placement-and-routing's post-simulation is incorrect; Check then whether placement-and-routing is correct; If placement-and-routing is incorrect, placement-and-routing again then is if placement-and-routing is correct; Check then whether complex optimum is correct, check further whether logical sequence information is correct;

Step 4: carry out the simulation hardware checking, the configuration file that the wiring back is generated downloads among the FPGA, and real physical interface is provided, and dynamically input verifies whether its actual working condition is consistent with the function that the logical sequence information of input realizes.Its operation is, PCI protocol interface circuit provides high performance EBI through pci interface chip, and pci bus interface is connected with computing machine through the PCI slot, through pci bus interface realization FPGA and compunication.The signal input and output circuit that receives provides input signal to FPGA; FPGA provides the test interface signal and realizes and the docking of ISE software interface; When FPGA transfers to computing machine with input signal input signal is carried out demodulation, the signal input and output circuit output of the signal after the demodulation through receiving, whether observe the output signal consistent with ISE software emulation result; If it is consistent; Then logical sequence information is loaded on fpga logic information static memory circuitry stores from FPGA, if inconsistent, checks successively then whether hardware, placement-and-routing, comprehensive simulating, logical sequence information is correct;

Step 5: verify for a long time; The signal input and output circuit that receives provides input signal; After system powered on, FPGA utilized the exchange of the digital signal of ISE software measurement imput output circuit from the automatic load logic time sequence information of fpga logic information static memory circuit; Verify whether promptly observe the output signal consistent with ISE software emulation result.

Utilization the present invention is based on the performance system of pci bus single channel receiving demodulation device; Realization is based on the performance test of pci bus single channel receiving demodulation device; Utilize the in-circuit emulation function of FPGA to realize in-circuit emulation; When simulation result is incorrect, carry out online modification, increased substantially, shortened based on the pci bus single channel receiving demodulation device construction cycle based on pci bus single channel receiving demodulation device debugging speed.

Claims

1. based on pci bus single channel receiving demodulation device Performance Test System; It is characterized in that; This system comprises the reception signal input and output circuit; Said reception signal input and output circuit is connected with the test interface signal logic circuit of FPGA; Said test interface signal logic circuit connects PCI protocol interface circuit, and said PCI protocol interface circuit is connected with the computing machine of PCI slot, and said PCI protocol interface circuit also is connected with the pci interface configuration circuit; Said pci interface configuration circuit is configured the PCI configuration register and the local configuration register of PCI protocol interface circuit; Said PCI protocol interface circuit provides high performance pci bus interface for the test interface signal logic circuit, and said test interface signal logic circuit communicates through pci bus interface and computing machine, and said test interface signal logic circuit also is connected with fpga logic information static memory circuit;

Utilize this Performance Test System to carry out performance test based on pci bus single channel receiving demodulation device,

At first write in the computing machine in the logical message with demodulator circuit, carry out emulation, whether the verifying logic relation is correct, can pass through then this logical message of compiling, otherwise this logical message is incorrect;

Logical message after the emulation is correctly carried out comprehensive post-simulation, and input clock signal is observed simulation result; Carry out placement-and-routing after simulation result is correct, and whether checking placement-and-routing is correct, input clock signal is observed simulation result;

If simulation result is correct; With the file that generates after the placement-and-routing through among the FPGA that is loaded on the test interface signal logic circuit; Through receiving the signal input and output circuit input signal to the FPGA demodulation; Utilize simulation software to measure the exchange of the digital signal of imput output circuit, whether the output signal is consistent with simulation result after the observation demodulation, and whether logical message is correct during the checking real work; If correct, then logical sequence information is loaded on fpga logic information static memory circuitry stores from FPGA.