CN102651360A - 一种可铜线键接的封装体结构及其制作方法 - Google Patents
一种可铜线键接的封装体结构及其制作方法 Download PDFInfo
- Publication number
- CN102651360A CN102651360A CN2011100504052A CN201110050405A CN102651360A CN 102651360 A CN102651360 A CN 102651360A CN 2011100504052 A CN2011100504052 A CN 2011100504052A CN 201110050405 A CN201110050405 A CN 201110050405A CN 102651360 A CN102651360 A CN 102651360A
- Authority
- CN
- China
- Prior art keywords
- chip
- chips
- pins
- copper wire
- lead frame
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 title claims abstract description 39
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 22
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 230000003014 reinforcing effect Effects 0.000 claims abstract description 36
- 239000004065 semiconductor Substances 0.000 claims abstract description 9
- 229910052802 copper Inorganic materials 0.000 claims description 14
- 239000010949 copper Substances 0.000 claims description 14
- 238000000034 method Methods 0.000 claims description 9
- 239000000969 carrier Substances 0.000 claims description 7
- 239000003351 stiffener Substances 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 3
- 238000002955 isolation Methods 0.000 claims description 3
- 239000000463 material Substances 0.000 claims description 3
- 150000001875 compounds Chemical class 0.000 claims 3
- 238000000465 moulding Methods 0.000 claims 3
- 238000005260 corrosion Methods 0.000 abstract description 2
- 230000007797 corrosion Effects 0.000 abstract 1
- 238000005538 encapsulation Methods 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01015—Phosphorus [P]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
Claims (10)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201110050405.2A CN102651360B (zh) | 2011-02-24 | 2011-02-24 | 一种可铜线键接的封装体结构及其制作方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201110050405.2A CN102651360B (zh) | 2011-02-24 | 2011-02-24 | 一种可铜线键接的封装体结构及其制作方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN102651360A true CN102651360A (zh) | 2012-08-29 |
CN102651360B CN102651360B (zh) | 2015-03-11 |
Family
ID=46693327
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201110050405.2A Active CN102651360B (zh) | 2011-02-24 | 2011-02-24 | 一种可铜线键接的封装体结构及其制作方法 |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN102651360B (zh) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103413801A (zh) * | 2013-07-12 | 2013-11-27 | 无锡红光微电子有限公司 | 一种dfn封装引线框架 |
CN103985693A (zh) * | 2014-05-20 | 2014-08-13 | 安徽国晶微电子有限公司 | 无刷直流电机集成驱动电路的封装结构及其封装方法 |
CN104465423A (zh) * | 2014-12-08 | 2015-03-25 | 杰群电子科技(东莞)有限公司 | 一种双引线框架叠合设计半导体器件封装方法 |
CN104716117A (zh) * | 2013-12-17 | 2015-06-17 | 万国半导体股份有限公司 | 多芯片器件及其封装方法 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1735963A (zh) * | 2003-01-15 | 2006-02-15 | 先进互联技术有限公司 | 具有局部预制图形化引线框架的半导体封装及其制造方法 |
US20060088956A1 (en) * | 2001-01-31 | 2006-04-27 | Siliconware Precision Industries Co., Ltd. | Method for fabricating semiconductor package with short-prevented lead frame |
US20070228534A1 (en) * | 2006-03-28 | 2007-10-04 | Tomoaki Uno | Semiconductor device and manufacturing method of the same |
CN101601133A (zh) * | 2006-10-27 | 2009-12-09 | 宇芯(毛里求斯)控股有限公司 | 部分图案化的引线框以及在半导体封装中制造和使用其的方法 |
-
2011
- 2011-02-24 CN CN201110050405.2A patent/CN102651360B/zh active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060088956A1 (en) * | 2001-01-31 | 2006-04-27 | Siliconware Precision Industries Co., Ltd. | Method for fabricating semiconductor package with short-prevented lead frame |
CN1735963A (zh) * | 2003-01-15 | 2006-02-15 | 先进互联技术有限公司 | 具有局部预制图形化引线框架的半导体封装及其制造方法 |
US20070228534A1 (en) * | 2006-03-28 | 2007-10-04 | Tomoaki Uno | Semiconductor device and manufacturing method of the same |
CN101601133A (zh) * | 2006-10-27 | 2009-12-09 | 宇芯(毛里求斯)控股有限公司 | 部分图案化的引线框以及在半导体封装中制造和使用其的方法 |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103413801A (zh) * | 2013-07-12 | 2013-11-27 | 无锡红光微电子有限公司 | 一种dfn封装引线框架 |
CN104716117A (zh) * | 2013-12-17 | 2015-06-17 | 万国半导体股份有限公司 | 多芯片器件及其封装方法 |
CN104716117B (zh) * | 2013-12-17 | 2017-10-24 | 万国半导体股份有限公司 | 多芯片器件及其封装方法 |
CN103985693A (zh) * | 2014-05-20 | 2014-08-13 | 安徽国晶微电子有限公司 | 无刷直流电机集成驱动电路的封装结构及其封装方法 |
CN104465423A (zh) * | 2014-12-08 | 2015-03-25 | 杰群电子科技(东莞)有限公司 | 一种双引线框架叠合设计半导体器件封装方法 |
CN104465423B (zh) * | 2014-12-08 | 2017-08-22 | 杰群电子科技(东莞)有限公司 | 一种双引线框架叠合设计半导体器件封装方法 |
Also Published As
Publication number | Publication date |
---|---|
CN102651360B (zh) | 2015-03-11 |
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SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
C41 | Transfer of patent application or patent right or utility model | ||
TR01 | Transfer of patent right |
Effective date of registration: 20160909 Address after: 400700 Chongqing city Beibei district and high tech Industrial Park the road No. 5 of 407 Patentee after: Chongqing Wanguo Semiconductor Technology Co.,Ltd. Address before: Bermuda Hamilton Church 2 Cola Lunden House Street Patentee before: ALPHA & OMEGA SEMICONDUCTOR, Ltd. Effective date of registration: 20160909 Address after: Bermuda Hamilton Church 2 Cola Lunden House Street Patentee after: ALPHA & OMEGA SEMICONDUCTOR, Ltd. Address before: The 94085 California Oak Park Road No. 475 in Sunnyvale, Mead Patentee before: ALPHA & OMEGA SEMICONDUCTOR, Ltd. |
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PE01 | Entry into force of the registration of the contract for pledge of patent right |
Denomination of invention: Packaging body structure capable of realizing copper wire keyed joint and manufacturing method thereof Effective date of registration: 20191210 Granted publication date: 20150311 Pledgee: Chongqing Branch of China Development Bank Pledgor: Chongqing Wanguo Semiconductor Technology Co.,Ltd. Registration number: Y2019500000007 |
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PE01 | Entry into force of the registration of the contract for pledge of patent right | ||
PC01 | Cancellation of the registration of the contract for pledge of patent right |
Granted publication date: 20150311 Pledgee: Chongqing Branch of China Development Bank Pledgor: Chongqing Wanguo Semiconductor Technology Co.,Ltd. Registration number: Y2019500000007 |
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PC01 | Cancellation of the registration of the contract for pledge of patent right |