CN102650970B

CN102650970B - Data access method, memory controller using same and storage device using same

Info

Publication number: CN102650970B
Application number: CN201110051084.8A
Authority: CN
Inventors: 詹清文
Original assignee: Phison Electronics Corp
Current assignee: Phison Electronics Corp
Priority date: 2011-02-25
Filing date: 2011-02-25
Publication date: 2015-06-10
Anticipated expiration: 2031-02-25
Also published as: CN102650970A

Abstract

The invention discloses a data access method, a memory controller using the same and a storage device using the same. The method, the controller and the device are used for accessing data on a rewritable nonvolatile memory module through a first thread module and a second thread module by a single data bus. The method comprises the following steps of: designating an access execution right to the second thread module to write page data; when the second thread module writes the page data with preset amount into entity pages with preset amount, judging whether an access instruction which should be executed by the first thread module is received or not; and when the access instruction which should be executed by the first thread module is received, designating the access execution right to the first thread module to execute the access instruction in a foreground mode, wherein the second thread module executes operation which is being carried out, in a background mode. Therefore, by the method, the time-out problem which is caused by the first thread module which does not response in real time can be effectively solved.

Description

The Memory Controller Hub of data access method and use the method and storage device

Technical field

The present invention relates to a kind of data access method, and in particular to a kind of data access method for the access duplicative Nonvolatile memory module by multiple Thread module and the Memory Controller Hub and the internal storing memory that use the method.

Background technology

Digital camera, mobile phone and MP3 are very rapid in growth over the years, and the demand of consumer to Storage Media is also increased rapidly.Due to duplicative Nonvolatile memory (rewritablenon-volatile memory) there is data non-volatile, power saving, the characteristic such as volume is little, mechanical structure, read or write speed are fast, be most suitable for portable electronic product, such as mobile computer.Solid state hard disc is exactly a kind of storage device using flash memory as Storage Media.Therefore, flash memory industry becomes a ring quite popular in electronic industry in recent years.

Duplicative nonvolatile memory storage device has multiple physical blocks (physical block), and each physical blocks has multiple physical page (physical page), when wherein writing data in physical blocks, data must be write in order according to the order of physical page.In addition, the physical page needing being written into data could again for writing data after first being erased.Particularly, physical blocks is the least unit of erasing, and physical page is the minimum unit of sequencing (also known as write).Therefore, in the management of flash memory system, physical blocks can be divided into data field and idle district.

The physical blocks of data field is the data stored stored by host computer system.Specifically, the logic access address that host computer system can access by memory management circuit is converted to the logical page (LPAGE) of logical blocks and videos the logical page (LPAGE) of logical blocks to the physical page of the physical blocks of data field.That is, in the management of flash memory module, the physical blocks of data field is regarded as by the physical blocks (such as, having stored the data that host computer system writes) used.Such as, memory management circuit can use logical blocks-physical blocks mapping table to record the reflection relation of the physical blocks of logical blocks and data field, and the logical page (LPAGE) wherein in logical blocks is the physical page of the physical blocks that correspondence is sequentially videoed.

The physical blocks in idle district is the physical blocks of rotating in data field.Specifically, as mentioned above, the physical blocks of written data just can again for writing data after must being erased, and the physical blocks in idle district be designed to write more new data to replace the physical blocks of original reflection logical blocks.Base this, the physical blocks in idle district is empty or spendable block, i.e. no record data or be labeled as invalid data useless.

Because the physical blocks of data field and the physical blocks in idle district are the data that the mode of rotating writes to store host computer system.Successfully can be accessed to allow host computer system to rotate the physical blocks of mode storage data, and duplicative nonvolatile memory storage device can provide logical blocks and logic access address host computer system accessed corresponds to the logical page (LPAGE) in these logical blocks.Specifically, the logic access address that main frame can access by duplicative nonvolatile memory storage device is converted to corresponding logical blocks, and reflects rotating of physical blocks by record in logical blocks-physical blocks mapping table (logicalblock-physical block mapping table) and the reflection relation upgraded between logical blocks and the physical blocks of data field.So main frame only needs to access according to logic access address, and flash memory system can according to logical blocks-physical blocks mapping table in the reading of the enterprising row data of videoed physical blocks or write.

Specifically, when host computer system for by data storing in a logic access address time, the control circuit of flash memory system can identify this logical blocks belonging to logic access address, from idle district, extract a physical blocks and new data can be write to the physical blocks (being also called fructification block) extracted from idle district, to replace the physical blocks (being also called female physical blocks) of original this logical blocks of reflection.At this, the video running of female physical blocks and fructification block of logical blocks is called unlatching mother and child blocks.Afterwards, when host computer system is for writing data to another logical blocks, flash memory system must carry out data consolidation procedure, (that is, the data belonging to this logical blocks being all incorporated in a physical blocks) is merged with the valid data of the logical blocks by video at present female physical blocks and fructification block.

Such as, in data merge process, valid data in female physical blocks can be copied to fructification block by duplicative nonvolatile memory storage device, and this logical blocks are again videoed to fructification block (that is, this fructification block will be associated to data field).In addition, female physical blocks in original data district can be carried out erasing and be associated to idle district by duplicative nonvolatile memory storage device.

Along with the capacity of a logical blocks is increasing, duplicative nonvolatile memory storage device must spend the longer time to carry out above-mentioned data consolidation procedure, to perform next write instruction.In addition, when internal storing memory be only configured a data bus come connection control circuit and duplicative Nonvolatile memory module and multiple Thread module is configured to access this duplicative Nonvolatile memory module time, due to these Thread modules be a shared data bus to transmit data, therefore make perform write instruction required time longer.Such as, if with the background Thread module of the access of background medium process data performing above-mentioned data consolidation procedure with write data and prospect Thread module receives the write instruction of host computer system time, prospect Thread module must wait for background Thread module complete data consolidation procedure after could perform this write instruction.Particularly, prospect Thread module may also need first to perform data consolidation procedure before this write instruction of execution, therefore, what perform that this time needed for instruction of write can become is quite long, make prospect Thread module cannot real-time response host computer system, and cause overtime (time out) problem.

Summary of the invention

The invention provides a kind of data access method, Memory Controller Hub and internal storing memory, it can avoid overtime problem under with the framework of multi-threading access Nonvolatile memory module.

Exemplary embodiment of the present invention proposes a kind of data access method, for by multiple Thread module access data in a duplicative Nonvolatile memory module, this duplicative Nonvolatile memory module has multiple physical blocks and each physical blocks has multiple physical page of sequential, these Thread modules comprise the first Thread module and the second Thread module, and the second Thread module performs a write instruction to be write to by multiple page data in the second instance block among these physical blocks.Notebook data access method comprises appointment one and accesses right of execution and write to via a data bus by the page data of predetermined quantity among above-mentioned page data by this second Thread module in the physical page of the predetermined quantity of second instance block to this second Thread module, and wherein the second Thread module to discharge this access right of execution and this predetermined quantity is less than the page number that arbitrary physical blocks has after the page data of predetermined quantity is write to second instance block via data bus.Notebook data access method is also included within after the second Thread module discharges this access right of execution, and judging whether to receive should access instruction performed by the first Thread module.Notebook data access method also comprises, when judge to receive should access instruction performed by the first Thread module time, assign this access right of execution to the first Thread module and perform this access instruction by the first instance block of the first Thread module among these physical blocks, wherein the first Thread module discharges this access right of execution after this access instruction of execution.

In one embodiment of this invention, above-mentioned data access method also comprises: after the first Thread module release access right of execution, assign above-mentioned access right of execution to the second Thread module and write to via above-mentioned data bus by the page data of another predetermined quantity among above-mentioned page data by the second Thread module in the physical page of another predetermined quantity of second instance block, wherein the second Thread module discharges this access right of execution after the page data of predetermined quantity is write to second instance block via data bus.

In one embodiment of this invention, above-mentioned data access method also comprises: when judge not receive should access instruction performed by the first Thread module time, then assign access right of execution to the second Thread module and write to via data bus by the page data of another predetermined quantity among these page datas by the second Thread module in the physical page of another predetermined quantity of second instance block, wherein the second Thread module discharges this access right of execution after page data is write to second instance block via data bus.

In one embodiment of this invention, above-mentioned data access method also comprises: configure multiple logical blocks with at least part of physical blocks of videoing; These logical blocks are divided into one first cut section and one second cut section; By the physical blocks of the first Thread module logical blocks of access mapping first cut section independently; And by the physical blocks of the second Thread module logical blocks of access mapping second cut section independently, wherein first instance block is videoed one of them of logical blocks of the first cut section, one of them of the logical blocks of the second cut section and second instance block is videoed.

In one embodiment of this invention, above-mentioned data access method also comprises: by the first Thread resume module first instruction; And by the second Thread resume module second instruction, wherein when the first instruction and the second instruction all need processed, the first instruction has precedence over the second instruction and above-mentioned access instruction belongs to the first instruction.

Exemplary embodiment of the present invention proposes a kind of data access method, for by multiple Thread module access data in duplicative Nonvolatile memory module, this duplicative Nonvolatile memory module has multiple physical blocks and each physical blocks has multiple physical page of sequential, these Thread modules comprise the first Thread module and the second Thread module, and the second Thread module performs a write instruction to be write to by multiple page data in the second instance block among these physical blocks.Notebook data access method comprises the number judging the page data be not yet written among these page datas and whether is less than default threshold value.Notebook data access method also comprises, when judging that the number of the page data be not yet written among these page datas is less than this default threshold value, then assign this access right of execution to the second Thread module and by the second Thread module, the page data be not yet written among these page datas write in second instance block via data bus.Notebook data access method also comprises, and when judging that the number of the page data be not yet written among these page datas is non-and being less than this default threshold value, then judging whether to receive should access instruction performed by the first Thread module.Notebook data access method also comprises, when judge to receive should access instruction performed by the first Thread module time, assign this access right of execution to the first Thread module and on the first instance block of data bus among these physical blocks thus, perform this access instruction by this first Thread module, wherein the first Thread module discharges this access right of execution after this access instruction of execution.

In one embodiment of this invention, above-mentioned data access method also comprises assigns access right of execution to the second Thread module and writes in the physical page of in second instance block predetermined quantity by the page data of predetermined quantity among these page datas via data bus by the second Thread module, and wherein the second Thread module discharges this access right of execution after the page data of predetermined quantity is write to second instance block via data bus.At this, the above-mentioned step judging whether the number of the page data be not yet written among page data is less than default threshold value is performed after the second Thread module discharges this access right of execution.

In one embodiment of this invention, when the first Thread module and the second Thread module all need to be performed, the first Thread module performs with foreground mode, and the second Thread module performs with background mode.

The embodiment of the present invention proposes a kind of Memory Controller Hub, and for controlling duplicative Nonvolatile memory module, wherein this duplicative Nonvolatile memory module has multiple physical blocks, and each physical blocks has multiple physical page of sequential.This Memory Controller Hub comprises memory interface and memory management circuit.Memory interface is in order to be electrically connected to duplicative Nonvolatile memory module.Memory management circuit is electrically connected to memory interface, and in order to perform a write instruction to be write to by multiple page data in the second instance block among these physical blocks.At this, memory management circuit comprises the first Thread module, the second Thread module and is electrically connected the resource distribution module of so far the first Thread module and the second Thread module.The page data of the predetermined quantity among these page datas to write in the physical page of the predetermined quantity of second instance block in order to assign access right of execution by data assignment circuit via a data bus to the second Thread module and the second Thread module, wherein the second Thread module discharges this access right of execution and predetermined quantity is less than the page number that arbitrary physical blocks has after the page data of predetermined quantity is write to second instance block via data bus.In addition, after the second Thread module discharges this access right of execution, resource distribution module judges whether to receive should access instruction performed by the first Thread module.And, when judge to receive should access instruction performed by the first Thread module time, this resource distribution module assigns this access right of execution to perform this access instruction to the first Thread module and the first Thread module via on the first instance block of data bus among these physical blocks, and wherein the first Thread module discharges this access right of execution after this access instruction of execution.

In one embodiment of this invention, after the first Thread module discharges above-mentioned access right of execution, above-mentioned resource distribution module assigns this access right of execution to the second Thread module and the page data of another predetermined quantity among these page datas writes in the physical page of another predetermined quantity of second instance block by the second Thread module via above-mentioned data bus, and wherein the page data of this predetermined quantity is being discharged this access right of execution through data bus thus by the second Thread module after writing to second instance block.

In one embodiment of this invention, when judge not receive should access instruction performed by the first Thread module time, above-mentioned resource distribution module assigns access right of execution to the second Thread module and the page data of another predetermined quantity among these page datas writes in the physical page of another predetermined quantity of second instance block by the second Thread module via above-mentioned data bus, and wherein the page data of this predetermined quantity is being discharged this access right of execution through data bus thus by the second Thread module after writing to second instance block.

In one embodiment of this invention, the above-mentioned multiple logical blocks of memory management Circnit Layout is to video at least part of above-mentioned physical blocks and these logical blocks are divided into the first cut section and the second cut section.At this, the physical blocks of the first Thread module logical blocks of access mapping first cut section independently, and the physical blocks of the second Thread module logical blocks of access mapping second cut section independently, wherein first instance block is videoed one of them of logical blocks of the first cut section, one of them of the logical blocks of the second cut section and second instance block is videoed.

Exemplary embodiment of the present invention proposes a kind of Memory Controller Hub, and for controlling duplicative Nonvolatile memory module, wherein this duplicative Nonvolatile memory module has multiple physical blocks, and each physical blocks has multiple physical page of sequential.This Memory Controller Hub comprises memory interface and memory management circuit.Memory interface is in order to be electrically connected to duplicative Nonvolatile memory module.Memory management circuit is electrically connected to memory interface, and in order to perform a write instruction to be write to by multiple page data in the second instance block among these physical blocks.At this, memory management circuit comprises the first Thread module, the second Thread module and is electrically connected the resource distribution module of so far the first Thread module and the second Thread module.Resource distribution module judges whether the number of the page data be not yet written among these page datas is less than one and presets threshold value.And, when judging that the number of the page data be not yet written among these page datas is less than default threshold value, resource distribution module assigns this access right of execution to be write in second instance block through data bus thus by the page data be not yet written among these page datas to the second Thread module and the second Thread module.In addition, when judging that the number of the page data be not yet written among these page datas is non-and being less than default threshold value, resource distribution module can judge whether to receive should access instruction performed by the first Thread module.And, when judge to receive should access instruction performed by the first Thread module time, resource distribution module assigns this access right of execution on the first instance block of data bus among these physical blocks thus, to perform this access instruction to the first Thread module and the first Thread module, and wherein the first Thread module discharges this access right of execution after this access instruction of execution.

In one embodiment of this invention, above-mentioned resource distribution module assigns access right of execution to the second Thread module and the page data of the predetermined quantity among these page datas writes in the physical page of the predetermined quantity of second instance block by the second Thread module via a data bus, and wherein the second Thread module discharges this access right of execution after the page data of predetermined quantity is write to second instance block via data bus.In addition, resource distribution module, after the second Thread module discharges this access right of execution, judges whether the number of the page data be not yet written among these page datas is less than above-mentioned default threshold value.

In one embodiment of this invention, above-mentioned first Thread module is in order to process the first instruction, and the second Thread module is in order to process the second instruction, and wherein when the first instruction and the second instruction all need processed, the first instruction has precedence over the second instruction.Further, above-mentioned access instruction belongs to the first instruction.

Exemplary embodiment of the present invention proposes a kind of internal storing memory, and it comprises above-mentioned duplicative Nonvolatile memory module and above-mentioned Memory Controller Hub.

Based on above-mentioned, the data access method of exemplary embodiment of the present invention, Memory Controller Hub and internal storing memory can be avoided accessing the issuable overtime problem of Nonvolatile memory module with multi-threading effectively.

For above-mentioned feature and advantage of the present invention can be become apparent, special embodiment below, and coordinate institute's accompanying drawings to be described in detail below.

Accompanying drawing explanation

Figure 1A is according to the present invention first exemplary embodiment display host computer system and internal storing memory.

Figure 1B is the schematic diagram of computing machine, input/output device and internal storing memory according to exemplary embodiment display of the present invention.

Fig. 1 C is host computer system according to the display of another exemplary embodiment of the present invention and the schematic diagram of internal storing memory.

Fig. 2 is the schematic block diagram of the internal storing memory shown in Figure 1A.

Fig. 3 and Fig. 4 is the schematic diagram of the management entity block according to the display of the present invention first exemplary embodiment.

Fig. 5 ~ Fig. 7 is the example of the write data according to the display of the present invention first exemplary embodiment.

Fig. 8 is the schematic block diagram of the Memory Controller Hub according to the display of the present invention first exemplary embodiment.

Fig. 9 is the process flow diagram of the data access method according to the display of the present invention first exemplary embodiment.

Figure 10 is the process flow diagram of the data access method according to the display of the present invention second exemplary embodiment.

Primary clustering symbol description

1000: host computer system

1100: computing machine

1102: microprocessor

1104: random access memory

1106: input/output device

1108: system bus

1110: data transmission interface

1202: mouse

1204: keyboard

1206: display

1208: printer

1212: Portable disk

1214: memory card

1216: solid state hard disc

1310: digital camera

1312:SD card

1314:MMC card

1316: memory stick

1318:CF card

1320: embedded storage device

100: internal storing memory

102: connector

104: Memory Controller Hub

106: duplicative Nonvolatile memory module

106a: data bus

310 (0) ~ 310 (R): physical blocks

502: data field

504: idle district

506: system region

508: replace district

510 (0) ~ 510 (H): logical blocks

610: the first cut sections

620: the second cut sections

710 (0) ~ 710 (M): logic access address

202: memory management circuit

204: host interface

206: memory interface

252: memory buffer

254: electric power management circuit

256: bug check and correcting circuit

282: the first Thread modules

284: the second Thread modules

286: resource distribution module

S901, S903, S905, S907, S909, S911: the step of data access

S1001, S1003, S1005, S1007, S1009, S1011, S1013, S1015, S1017: the step of data access

Embodiment

First exemplary embodiment

Please refer to Figure 1A, host computer system 1000 generally comprises computing machine 1100 and I/O (input/output, I/O) device 1106.Computing machine 1100 comprises microprocessor 1102, random access memory (random access memory, RAM) 1104, system bus 1108 and data transmission interface 1110.Input/output device 1106 comprises as the mouse 1202 of Figure 1B, keyboard 1204, display 1206 and printer 1208.It must be appreciated, the unrestricted input/output device 1106 of the device shown in Figure 1B, input/output device 1106 can also comprise other device.

In embodiments of the present invention, internal storing memory 100 is electrically connected by data transmission interface 1110 other assembly with host computer system 1000.Data can be write to internal storing memory 100 by microprocessor 1102, random access memory 1104 with the running of input/output device 1106 or read data from internal storing memory 100.Such as, internal storing memory 100 can be the nonvolatile memory storage device of Portable disk 1212, memory card 1214 or solid state hard disc (Solid State Drive, SSD) 1216 etc. as shown in Figure 1B.

Generally speaking, host computer system 1000 can be can any system of storage data substantially.Although in this exemplary embodiment, host computer system 1000 explains with computer system, but host computer system 1000 can be the systems such as digital camera, video camera, communicator, reproducing apparatus for phonotape or video signal player in another exemplary embodiment of the present invention.Such as, when host computer system is digital camera (video camera) 1310, nonvolatile memory storage device is then its SD card 1312 used, mmc card 1314, memory stick (memory stick) 1316, CF card 1318 or embedded storage device 1320 (as shown in Figure 1 C).Embedded storage device 1320 comprises embedded multi-media card (Embedded MMC, eMMC).It is worth mentioning that, embedded multi-media card is directly electrically connected on the substrate of host computer system.

Please refer to Fig. 2, internal storing memory 100 comprises connector 102, Memory Controller Hub 104 and duplicative Nonvolatile memory module 106.

In this exemplary embodiment, connector 102 is secure digital (Secure Digital, SD) interface connector.But, it must be appreciated, the present invention is not limited thereto, connector 102 can also be universal serial bus (Universal Serial Bus, USB) connector, Institute of Electrical and Electric Engineers (Institute of Electrical and Electronic Engineers, IEEE) 1394 connectors, high-speed peripheral component connecting interface (Peripheral Component Interconnect Express, PCI Express) connector, advanced annex (the Serial Advanced Technology Attachment of sequence, SATA) connector, memory stick (Memory Stick, MS) interface connector, Multi Media Card (Multi Media Card, MMC) interface connector, compact flash (Compact Flash, CF) interface connector, integrated driving electrical interface (Integrated Device Electronics, IDE) connector or other connector be applicable to.

Memory Controller Hub 104 in order to perform with multiple logic lock of hardware pattern or firmware pattern implementation or steering order, and according to the instruction of host computer system 1000 carry out in duplicative Nonvolatile memory module 106 data write, read and the running such as to erase.

Duplicative Nonvolatile memory module 106 is electrically connected to Memory Controller Hub 104, and in order to store the data that host computer system 1000 writes.Particularly, duplicative Nonvolatile memory module 106 is electrically connected to Memory Controller Hub 104 via single data bus 106a.

Duplicative Nonvolatile memory module 106 has physical blocks 310 (0) ~ 310 (R).Each physical blocks has a plurality of physical page respectively, and the physical page wherein belonging to same physical blocks can be written independently and side by side be erased.Such as, each physical blocks is made up of 128 physical page.But it must be appreciated, the present invention is not limited thereto, each physical blocks can be made up of 64 physical page, 256 physical page or other any physical page.

In more detail, physical blocks is the least unit of erasing.That is, each physical blocks contain minimal amount in the lump by the memory cell of erasing.Physical page is the least unit of sequencing.That is, physical page is the least unit of write data.But it must be appreciated, in another exemplary embodiment of the present invention, the least unit of write data can also be sector (Sector) or other size.Each physical page generally includes data bit district D and redundant digit district R.Data bit district D is in order to store the data of user, and redundant digit district R is in order to the data (such as, bug check and correcting code) of stocking system.

In this exemplary embodiment, duplicative Nonvolatile memory module 106 is multistage memory cell (Multi Level Cell, MLC) nand flash memory module.But, the present invention is not limited thereto, duplicative Nonvolatile memory module 106 also single-order memory cell (Single Level Cell, SLC) nand flash memory module, other flash memory module or other there is the memory modules of identical characteristics.

Please refer to Fig. 3, physical blocks 310 (0) ~ 310 (R) logically can be grouped into data field 502, idle district 504, system region 506 and replace district 508 by Memory Controller Hub 104.

Belonging to data field 502 in logic with the physical blocks in idle district 504 is in order to storage data.Specifically, data field 502 is physical blocks of storage data, and the physical blocks in idle district 504 is the physical blocks in order to replacement data district 502.Therefore, the physical blocks in idle district 504 be sky or spendable physical blocks, i.e. no record data or be labeled as invalid data useless.That is, the physical blocks in idle district 504 has been performed running of erasing, or the physical blocks be extracted for extracting before storage data when the physical blocks in idle district 504 can be performed running of erasing.Therefore, the physical blocks in idle district 504 is can by the physical blocks used.

The physical blocks belonging to system region 506 is in logic in order to register system data, and wherein this system data comprises manufacturer about duplicative Nonvolatile memory module and model, the physical blocks number of duplicative Nonvolatile memory module, the physical page number etc. of each physical blocks.

Belonging to the physical blocks replaced in district 508 is in logic replace bad physical blocks.Such as, Nonvolatile memory module 106 can reserve the physical blocks of 4% as replacing use in time dispatching from the factory.That is, when data field 502, idle district 504 damage with the physical blocks in system region 506, reserve and can be used to replacing damaged physical blocks in replacing the physical blocks in district 508.Therefore, if when still having normal physical blocks in replacement district 508 and physical blocks damage occurs, Memory Controller Hub 104 can extract normal physical blocks to change the physical blocks of damage from replacement district 508.If when to replace in district 508 without normal physical blocks and physical blocks damage occurs, then whole internal storing memory 100 can be declared as write protection (write protect) state by Memory Controller Hub 104, and cannot write data again.

Particularly, data field 502, idle district 504, system region 506 can be different according to different memory standards with the quantity of the physical blocks in replacement district 508.In addition, it must be appreciated, during the running of internal storing memory 100, physical blocks is associated to data field 502, idle district 504, system region 506 can dynamically change with the grouping relation replacing district 508.Such as, when the physical blocks in idle district 504 is damaged and is substituted the physical blocks replacement in district, then the physical blocks originally replacing district 508 can be associated to idle district 504.

Please refer to Fig. 4, as mentioned above, data field 502 is data that the mode of rotating writes to store host computer system 1000 with the physical blocks in idle district 504.In this exemplary embodiment, Memory Controller Hub 104 meeting configuration logic block 510 (0) ~ 510 (H) is with the physical blocks carrying out storage data in the above-mentioned mode of rotating of videoing.Particularly, logical blocks 510 (0) ~ 510 (H) can be divided into the first cut section 610 and the second cut section 620 comprising logical blocks 510 (L+1) ~ 510 (H) that comprise logical blocks 510 (0) ~ 510 (L) by Memory Controller Hub 104.

At this, the first cut section 610 is supplied to host computer system 1000 to identify and the cut section generally accessed.Such as, when internal storing memory 100 is electrically connected to host computer system 1000, host computer system 1000 will identify that internal storing memory 100 is for Large Copacity storage class and can access space be the first cut section 610 after the signal exchange (handshaking).

Such as, Memory Controller Hub 104 by the logical page (LPAGE) of logical blocks 510 (0) ~ 510 (L) reflection to the logic access address 710 (0) ~ 710 (M) that host computer system 1000 accesses, can carry out access data in order to host computer system 1000.Such as, the first cut section logical blocks 510 (0) ~ 510 (L) can initially be videoed to the physical blocks belonging to data field 502 by Memory Controller Hub 104.Specifically, when internal storing memory 100 is done manufacture, logical blocks 510 (0) ~ 510 (L) is videoed respectively to the physical blocks 310 (0) ~ 310 (L) of data field 502.That is, a physical blocks in a logical blocks meeting Image Data district 502.At this, Memory Controller Hub 104 can set up logical blocks-physical blocks mapping table (logical block-physical block mapping table), to record the reflection relation between logical blocks and physical blocks.That is, host computer system 1000 can be converted to the logical page (LPAGE) of corresponding logical blocks by Memory Controller Hub 104 for the logic access address accessed, thus by query logic block-physical blocks mapping table access data in physical page.

Second cut section 620 is the storage areas belonging to application-specific.Such as, in the present invention one illustrative examples, second cut section 620 be for deposit through complexity encryption and decryption mechanism (such as, meet Federal Information Processing Standards (Federal Information Processing Standards, FIPS) tertiary gradient or more high-grade or meet the tertiary gradient of EMV EL or more high-grade encryption and decryption mechanism of 140-2) secure data encrypted, and host computer system 1000 only could access the data being stored in the second cut section 620 by specific communication software and identification.That is, when internal storing memory 100 is electrically connected to host computer system 1000, the archives economy None-identified of host computer system 1000 goes out the existence of the second cut section 620.Such as, the storage area of the second cut section 620 can be used as the region of data storage of smart card (smart card) application program, and wherein host computer system 1000 must use this application program of intelligent card and by accessing the secure data in the second cut section 620 after authentication.

Fig. 5 ~ Fig. 7 is the example of the write data according to the display of the present invention first exemplary embodiment.At this, be the logical blocks that writes data to the first cut section 610 for example is described, but its function mode is also applicable to the logical blocks writing data to the second cut section 620.

Referring to Fig. 5 ~ Fig. 7, such as, logical blocks 510 (0) be reflection under the state of physical blocks 310 (0), when Memory Controller Hub 104 receives write instruction and for write data to when belonging to the logical page (LPAGE) of logical blocks 510 (0) from host computer system 1000, Memory Controller Hub 104 can be video to physical blocks 310 (0) and from idle district 504, extract physical blocks 310 (D+1) as replacement physical blocks to physical blocks 310 (0) of rotating according to logical blocks-physical blocks mapping table recognition logic block 510 (0) at present.But, while new data is write to fructification block 310 (D+1) by Memory Controller Hub 104, all valid data in physical blocks 310 (0) can not be moved the physical blocks 310 (0) of erasing to physical blocks 310 (D+1) by Memory Controller Hub 104 at once.Specifically, Memory Controller Hub 104 can by the valid data before wish write physical page in physical blocks 310 (0) (namely, data in 0th physical page of physical blocks 310 (0) and the 1st physical page) be copied in the 0th physical page of physical blocks 310 (D+1) and the 1st physical page (as shown in Figure 5), and new data is write in 2nd ~ 4 physical page of physical blocks 310 (D+1) (as shown in Figure 6).Now, namely Memory Controller Hub 104 completes the running of write.Because the valid data in physical blocks 310 (0) likely in next operation (such as, write instruction) in become invalid, therefore at once other valid data in physical blocks 310 (0) are moved to physical blocks 310 (D+1) and meaningless moving may be caused.In addition, data must write to the physical page in physical blocks in order, therefore, Memory Controller Hub 104 only can first move for write physical page before valid data (namely, be stored in data in the 0th physical page of physical blocks 310 (0) and the 0th physical page), and all the other valid data (that is, being stored in data in the 5th ~ (K-1) physical page of physical blocks 310 (0)) wouldn't be moved.

In this exemplary embodiment, the running temporarily maintaining these instantaneous relationship is called unlatching (open) mother and child blocks, and former physical blocks (such as, above-mentioned physical blocks 310 (0)) be called female physical blocks and replace physical blocks (such as, above-mentioned with physical blocks 310 (D+1)) and be called fructification block.

Afterwards, when needing physical blocks 310 (0) to merge (merge) with the data of physical blocks 310 (D+1), Memory Controller Hub 104 can by whole to physical blocks 310 (0) and the data of physical blocks 310 (D+1) and to a physical blocks, promote the service efficiency of physical blocks thus.At this, the running merging mother and child blocks is called data consolidation procedure or closedown (close) mother and child blocks.Such as, as shown in Figure 7, when carrying out closedown mother and child blocks, Memory Controller Hub 104 can by remaining valid data in physical blocks 310 (0) (namely, data in 5th ~ (K-1) physical page of physical blocks 310 (0)) be copied in the 5th physical page ~ the (K-1) physical page of replacing physical blocks 310 (D+1), then erase operation for use is performed to physical blocks 310 (0) and the physical blocks 310 (0) after erasing is associated to idle district 504, meanwhile, physical blocks 310 (D+1) is associated to data field 502.That is, logical blocks 510 (0) again can be videoed to physical blocks 310 (D+1) by Memory Controller Hub 104 in logical blocks-physical blocks mapping table.In addition, in this exemplary embodiment, Memory Controller Hub 104 can be set up idle district's physical blocks table (not illustrating) and record the physical blocks being associated to idle district at present.

It is worth mentioning that, in idle district 504, the number of physical blocks is limited, base this, during internal storing memory 100 operates, the group number of the mother and child blocks of unlatching also can be restricted.Therefore, when internal storing memory 100 receives the write instruction coming from host computer system 1000, if the group number having opened mother and child blocks reaches in limited time, Memory Controller Hub 104 just can perform this write instruction after need closing at least one group of mother and child blocks of having opened at present.

Such as, be in the example of SD memory card at internal storing memory 100, the upper limit of the group number of openable mother and child blocks is generally be set as 1.Such as, when under state as shown in Figure 6 and Memory Controller Hub 104 receives write instruction and for write data to when belonging to the logic access address of logical blocks 510 (1) from host computer system 1000, Memory Controller Hub 104 first must close mother and child blocks (as shown in Figure 7), and afterwards, then from idle district 504 extract a physical blocks to open mother and child blocks (as Suo Shi Fig. 5 ~ 6) to complete data write.

Please refer to Fig. 8, Memory Controller Hub 104 comprises memory management circuit 202, host interface 204 and memory interface 206.

Memory management circuit 202 is in order to control the overall operation of Memory Controller Hub 104.Specifically, memory management circuit 202 has multiple steering order, and when internal storing memory 100 operates, and these steering orders can be performed with the write carrying out data in duplicative Nonvolatile memory module 106, read and the running such as to erase.Particularly, in this exemplary embodiment, the steering order of memory management circuit 202 can with multiple Thread carry out in duplicative Nonvolatile memory module 106 data write, read and the running such as to erase.

In this exemplary embodiment, the steering order of memory management circuit 202 carrys out implementation with firmware pattern.Such as, memory management circuit 202 has microprocessor unit (not illustrating) and ROM (read-only memory) (not illustrating), and these steering orders are burned onto in this ROM (read-only memory).When internal storing memory 100 operates, the write that these steering orders can perform to carry out data by microprocessor unit is read and the running such as to be erased.

In another exemplary embodiment of the present invention, the steering order of memory management circuit 202 can also program code pattern be stored in the specific region (such as, being exclusively used in the system region of storage system data in memory modules) of duplicative Nonvolatile memory module 106.In addition, memory management circuit 202 has microprocessor unit (not illustrating), ROM (read-only memory) (not illustrating) and random access memory (not illustrating).Particularly, this ROM (read-only memory) has driving code section, and when Memory Controller Hub 104 is enabled, microprocessor unit first can perform this and drive code section the steering order be stored in duplicative Nonvolatile memory module 106 to be loaded in the random access memory of memory management circuit 202.Afterwards, microprocessor unit can operate these steering orders with perform data write, read and the running such as to erase.In addition, in another exemplary embodiment of the present invention, the steering order of memory management circuit 202 a hardware pattern can also carry out implementation.

Host interface 204 is electrically connected to memory management circuit 202 and in order to receive and to identify the instruction that transmits of host computer system 1000 and data.That is, the instruction that transmits of host computer system 1000 and data can be sent to memory management circuit 202 by host interface 204.In this exemplary embodiment, host interface 204 is corresponding connectors 102 is SD interface.。But, it must be appreciated and the present invention is not limited thereto, host interface 204 can also be USB interface, PATA interface, IEEE1394 interface, PCI Express interface, SATA interface, MS interface, MMC interface, CF interface, ide interface or other data transmission interface be applicable to.

Memory interface 206 is electrically connected to memory management circuit 202 and in order to access duplicative Nonvolatile memory module 106.That is, the data for writing to duplicative Nonvolatile memory module 106 can be converted to the receptible form of duplicative Nonvolatile memory module 106 via memory interface 206.

In the present invention one exemplary embodiment, Memory Controller Hub 104 also comprises memory buffer 252.Memory buffer 252 is electrically connected to memory management circuit 202 and comes from the data and instruction of host computer system 1000 in order to temporary or come from the data of duplicative Nonvolatile memory module 106.

In the present invention one exemplary embodiment, Memory Controller Hub 104 also comprises electric power management circuit 254.Electric power management circuit 254 is electrically connected to memory management circuit 202 and power supply in order to control internal storing memory 100.

In the present invention one exemplary embodiment, Memory Controller Hub 104 also comprises bug check and correcting circuit 256.Bug check and correcting circuit 256 are electrically connected to memory management circuit 202 and in order to execution error inspection and correction program to guarantee the correctness of data.Specifically, when memory management circuit 202 receives write instruction from host computer system 1000, bug check and correcting circuit 256 can be that the corresponding data that this writes instruction produce corresponding bug check and correcting code (Error Checkingand Correcting Code, ECC Code), and the data of this write instruction corresponding can write in duplicative Nonvolatile memory module 106 with corresponding bug check and correcting code by memory management circuit 202.Afterwards, can read bug check corresponding to these data and correcting code when memory management circuit 202 reads data from duplicative Nonvolatile memory module 106, and bug check and correcting circuit 256 can according to this bug check and correcting code to read data execution error inspection and correction programs simultaneously.

In this exemplary embodiment, memory management circuit 202 comprises the first Thread module 282, second Thread module 284 and resource distribution module 286.

First Thread module 282 and the second Thread module 284 access duplicative Nonvolatile memory module 106 by memory interface 206 with data bus 106a.Such as, in this exemplary embodiment, the first Thread module 282 is in order to manage independently and access the first cut section 610, and the second Thread module 284 is in order to manage independently and to access the second cut section 620.That is, in this exemplary embodiment, the first Thread module 282 only can access the first cut section 610 and cannot access the second cut section 620, and the second Thread module 284 only can access the second cut section 620 and cannot access the first cut section 610.

It is worth mentioning that, in exemplary embodiment of the present invention, the first Thread module 282 and the second Thread module 284 are that jointly usage data district 502 and the physical blocks in idle district 504 write the data of the logical blocks for being stored in the first cut section 610 and the second cut section 620.Therefore, the first Thread module 282 and the second Thread module 284 are the physical blocks using identical memory management rule (such as, as shown in figure 3 to figure 7) to access duplicative Nonvolatile memory module 106.

But in another exemplary embodiment of the present invention, the first Thread module 282 and the second Thread module 284 also can use individually different memory management rules to access the physical blocks of duplicative Nonvolatile memory module 106.Such as, the physical blocks of duplicative Nonvolatile memory module 106 can be divided into the physical blocks being independently assigned to the first Thread module 282 and the physical blocks being independently assigned to the second Thread module 284, base this, the first Thread module 282 and the second Thread module 284 just can carry out packet entities block with logical blocks of videoing according to rule itself.

Such as, in exemplary embodiment of the present invention, the first Thread module 282, relative to the second Thread module 284, is the instruction (at this, being called the first instruction) in order to process with the data type that the stricter data processing time limit requires.Such as, first Thread module 282 is the access instruction belonging to safe digital card (Secure Digital Card) instruction or MMC (MultiMedia Card) card instruction coming from host computer system 1000 in order to perform, the data for being stored to the first cut section 610 are write to physical blocks or read data from the physical blocks that the logical blocks of the first cut section 610 is videoed.In this exemplary embodiment, first Thread module 282 is in order to perform the module of the higher programmed instruction of priority level, that is when the host computer system 1000 of multitask is simultaneously when processing multiple program, first Thread module 282 is in the program processed or instruction, the program in using at present can be become, that is become the module performed with prospect (foreground) pattern.

Such as, in exemplary embodiment of the present invention, the second Thread module 284, relative to the first Thread module 282, is the instruction (at this, being called the second instruction) in order to process with the data type that the looser data processing time limit requires.Such as, the second Thread module 284 is the access instructions belonging to smart card (Smart Card) instruction or USB (Universal Serial Bus) instruction in order to process.In this exemplary embodiment, the second Thread module 284 is in order to perform the module of the lower programmed instruction of priority level, that is when the host computer system 1000 of multitask is simultaneously when processing multiple program, second Thread module 284 is in the program processed or instruction, be the program be in non-usage, that is become the module performed with background (background) pattern.Wherein, in another exemplary embodiment, the job procedure in host computer system 1000, only the control of such as specific device can be given the first Thread module, the second Thread module then can be released automatically to the control of this specific device.

Specifically, as instruction-Application Protocol Data Unit (Command-Application Protocol Data Unit that host computer system 1000 is transmitted by specific intelligence card application, C-APDU), time to internal storing memory 100, memory management circuit 202 can identify this smart card instruction and the second Thread module 284 can with background medium to perform this smart card instruction.That is, when the second Thread module 284 performs instruction, memory management circuit 202 still can receive by host interface 204 instruction coming from host computer system 1000.Such as, when the second Thread module 284 performs write instruction data to be write to the physical blocks of the logical blocks of reflection second cut section 620, memory management circuit 202 still can receive the access instruction accessing the first cut section 610 from host computer system 1000.

Resource distribution module 286 is in order to assign the access right of execution of duplicative Nonvolatile memory module 106 to the first Thread module 282 and the second Thread module 284.Specifically, first Thread module 282 and the second Thread module 284 all must access duplicative Nonvolatile memory module 106 by memory interface 206 with data bus 106a, therefore, in order to make access channel (namely, memory interface 206 and data bus 106a) instruction alternately transmitting the first Thread module 282 and assign with the second Thread module 284 can be taken turns, resource distribution module 286 is configured to the right to use of coordination access channel.Such as, resource assignment unit 1046 is real time operating system (Real Time OperationSystem, RTOS).But, it must be appreciated, the present invention is not limited thereto.

It is worth mentioning that, in this exemplary embodiment, when memory management circuit 202 receives the access instruction for access the first cut section 610, the first Thread module 282 must complete this access instruction as quickly as possible, otherwise overtime problem can occur.As mentioned above, when the second Thread module 284 performs write instruction with background medium, memory management circuit 202 still may receive the access instruction of wish access the first cut section 610 from host computer system 1000.If when the first Thread module 282 is waited for and performed received access instruction again after the second Thread module 284 completes write instruction, may there is overtime problem in internal storing memory 100.

Such as, be in the example of SD memory card at internal storing memory 100, the time performing write instruction must be less than 250 milliseconds (millisecond, ms), and the time performing reading command must be less than 150ms.But in general, performing above-mentioned data consolidation procedure need expend 150ms.Such as, suppose that the first Thread module 282 waits for that 150ms (namely, second Thread module 284 completes the time of write needed for instruction) after when carrying out data consolidation procedure again to perform write instruction, the first Thread module 282 completes this time writing instruction must more than 250ms.Moreover, suppose that the first Thread module 282 waits for that 150ms (namely, second Thread module 284 completes the time of write needed for instruction) after when carrying out digital independent again, the first Thread module 282 completes time of this reading command also must more than 150ms.

For avoiding above-mentioned overtime problem, in exemplary embodiment of the present invention, when the second Thread module 284 is for performing write instruction so that data are write to physical blocks with background medium, access right of execution can be assigned to the second Thread module 284 for resource distribution module 286 and when the second Thread module 284 completes the write of the physical page of predetermined quantity, resource distribution module 286 can require that the second Thread module 284 discharges access right of execution and judges whether access right of execution to be assigned to the first Thread module 282.

Specifically, duplicative Nonvolatile memory module 106 is that unit is to write data with physical page, therefore, the data for write can be divided into multiple page data and can be transferred in batches in duplicative Nonvolatile memory module 106 with each page data by the second Thread module 284.And, after the page data transmitting predetermined quantity in the second Thread module 284 to duplicative Nonvolatile memory module 106, resource distribution module 286 can require the second Thread module 284 to discharge access right of execution at once and confirm whether internal storing memory 100 receives should access instruction performed by the first execution module 282.Particularly, should access instruction performed by the first execution module 282 when receiving, access right of execution can be assigned to the first execution module 282, to suspend the second Thread module 284 with the write instruction performed by background medium by resource distribution module 286.Afterwards, after the access instruction performed by the first execution module 282 completes this access instruction and release accesses right of execution, access right of execution can be assigned to the second Thread module 284 by resource distribution module 286 again, continues to perform write instruction send the page data of another predetermined quantity to duplicative Nonvolatile memory module 106 to make the second Thread module 284.In this exemplary embodiment, predetermined quantity is 1, but it must be appreciated, the present invention is not limited thereto, and predetermined quantity can be the Arbitrary Digit of the number (that is, page number) being less than the physical page that a physical blocks has.

Because the second Thread module 284 is the write instructions processed with background medium, therefore, postpone the second Thread module 284 and perform the overtime that the time writing instruction can not cause internal storing memory 100.

Fig. 9 be according to the present invention first exemplary embodiment the process flow diagram of data access method that shows, it illustrates the step of the access data when the second Thread module 284 performs write instruction many page datas to be write to physical blocks (hereinafter referred to as second instance block) with background medium.

Please refer to Fig. 9, first, in step S901, access right of execution is assigned to the second Thread module 284.

Afterwards, in step S903, by the second Thread module 284, the page data of predetermined quantity among these page datas to be write in order via data bus 106a in the physical page of the predetermined quantity of second instance block and to make the second Thread module 284 discharge access right of execution after the page data of this predetermined quantity of write.

Then, in step S905, judging whether to receive should access instruction performed by the first Thread module 282.

If do not receive should access instruction performed by the first Thread module 282 time, then in step s 907, judge whether the page data for writing to second instance block is written into all.

If for write to second instance block page data among still have the page data be not also written into time, perform step S901.

If when the page data for writing to second instance block is written into all, terminate the flow process of Fig. 9.

If receive should access instruction performed by the first Thread module 282 time, then in step S909, access right of execution is assigned to the first Thread module 282.And, in step S911, perform this access instruction by the first Thread module 282 and after this access instruction of execution, make the first Thread module 282 discharge access right of execution the physical blocks (hereinafter referred to as first instance block) of reflection is upper.Afterwards, step S907 can be performed.

Second exemplary embodiment

The internal storing memory of the present invention second exemplary embodiment and host computer system are the internal storing memory and the host computer system that are same as the first exemplary embodiment in essence, and wherein difference is only that the resource distribution module of the Memory Controller Hub of the second exemplary embodiment more can decide to access according to the practice condition of the second Thread module the appointment of right of execution.The difference part will utilizing the graphic of the first illustrative examples and Ref. No. that the second exemplary embodiment and the first exemplary embodiment are described below.

In the second exemplary embodiment, when the second Thread module 284 is for performing write instruction so that page data is write to physical blocks with background medium, resource distribution module 286 can assign access right of execution to the second Thread module 284.Particularly, resource distribution module 286 can judge whether the second Thread module 284 is less than one for the number writing to the page data be not yet written among the page data of physical blocks and presets threshold value.

If when the number of the page data be not yet written into is less than this default threshold value, resource distribution module 286 can assign access right of execution to the second Thread module 284, and discharges access right of execution again after the page data these be not yet written into writes to physical blocks.

If the number of the page data be not yet written into is non-when being less than this default threshold value, resource distribution module 286 can assign access right of execution to the second Thread module 284.Further, resource distribution module 286 can require when the second Thread module 284 completes the write of a physical page that the second Thread module 284 discharges access right of execution, and judges whether access right of execution to be assigned to the first Thread module 282.

That is, if the first Thread module 282 performs access instruction again when can't cause overtime problem after the page data be not yet written into is write to physical blocks by wait second Thread module 284, resource distribution module 286 directly can will access right of execution to the second Thread module 284, until the second Thread module 284 completes write instruction.At this, default threshold value is that the maximum delay time that can bear according to internal storing memory 100 is estimated.Such as, the first Thread module 282 need respond the write instruction of host computer system 1000 and perform this write instruction when need expend 150ms in 250ms, then maximum delay time is 100ms.If suppose that the second Thread module 284 writes a page data when needing 2ms, then this default threshold value can be set to 50.Base this, can avoid assigning continually and discharging access right of execution.

Figure 10 is the process flow diagram of data access method according to the display of the present invention second exemplary embodiment, its illustrate when the second Thread module 284 with background medium perform write instruction many page datas to be write to physical blocks (hereinafter referred to as second instance block) time access data step.

Please refer to Figure 10, first, in step S1001, access right of execution is assigned to the second Thread module 284.

Afterwards, in the step s 1003, by the second Thread module 284, the page data of the predetermined quantity among these page datas to be write in order via data bus 106a in the physical page of the predetermined quantity of second instance block and to make the second Thread module 284 discharge access right of execution after this page data of write.

Then, in step S1005, judging whether to receive should access instruction performed by the first Thread module 282.

If do not receive should access instruction performed by the first Thread module 282 time, then in step S1007, judge whether the page data for writing to second instance block is written into all.

If for write to second instance block page data among still have the page data be not also written into time, in step S1009, judge whether the number of the page data be not also written into is less than minimum threshold value.

If the number of the page data be not also written into is non-when being less than minimum threshold value, then perform step S1001.

If when the number of the page data be not also written into is less than minimum threshold value, then in step S1011, access right of execution is assigned to the second Thread module 284.Then, in step S1013, by the second Thread module 284 page data be not also written into write to second instance block in order via data bus 106a and make the second Thread module 284 discharge access right of execution after these page datas of write.

If when the page data for writing to second instance block is written into all, terminate the flow process of Figure 10.

If in step S1005, judge to receive should access instruction performed by the first Thread module 282 time, then in step S1015, access right of execution is assigned to the first Thread module 282.And, in step S1017, perform this access instruction by the first Thread module 282 and after this access instruction of execution, make the first Thread module 282 discharge access right of execution the physical blocks (hereinafter referred to as first instance block) of reflection is upper.Afterwards, step S1007 can be performed.

In sum, under the framework accessing duplicative Nonvolatile memory module with multiple Thread, the data access method of exemplary embodiment of the present invention, Memory Controller Hub and internal storing memory can be avoided waiting the overtime problem caused because waiting the second Thread with the first Thread.

Although the present invention with embodiment disclose as above, so itself and be not used to limit the present invention, the those of ordinary skill in any art, when doing a little change and retouching, and does not depart from the spirit and scope of the present invention.

Claims

1. a data access method, for by multiple Thread module access data in a duplicative Nonvolatile memory module, wherein this duplicative Nonvolatile memory module has multiple physical blocks, physical blocks described in each has multiple physical page of sequential, described Thread module comprises one first Thread module and one second Thread module, and this second Thread module performs a write instruction to be write to by multiple page data in the second instance block among described physical blocks, and this data access method comprises:

Judge whether the number of the page data be not yet written among described multiple page data is less than one and presets threshold value;

When judging that the number of the page data be not yet written among described multiple page data is less than this default threshold value, then an access right of execution is assigned to give this second Thread module and write in this second instance block by the page data be not yet written among described multiple page data via this data bus by this second Thread module;

When judging that the number of the page data be not yet written among described multiple page data is non-and being less than this default threshold value, assign this access right of execution to this second Thread module and by this second Thread module the page data of the predetermined quantity among described multiple page data write to via this data bus in the physical page of this predetermined quantity among the described physical page in this second instance block, wherein this second Thread module discharges this access right of execution and this predetermined quantity is less than the page number that arbitrary described physical blocks has after the page data of this predetermined quantity among described multiple page data is write to this second instance block via this data bus,

After this second Thread module discharges this access right of execution, judging whether to receive should an access instruction performed by this first Thread module; And,

When judge to receive should this access instruction performed by this first Thread module time, then assign this access right of execution to this first Thread module and perform this access instruction by this first Thread module via on the first instance block of this data bus among described physical blocks, wherein this first Thread module discharges this access right of execution after this access instruction of execution.

2. data access method according to claim 1, also comprises:

After this first Thread module discharges this access right of execution, assign this access right of execution to this second Thread module and in the physical page of another predetermined quantity among the described physical page by this second Thread module the page data of another predetermined quantity among described multiple page data being write to this second instance block via this data bus, wherein this second Thread module discharges this access right of execution after the page data of this another predetermined quantity among described multiple page data is write to this second instance block via this data bus.

3. data access method according to claim 1, also comprises:

When judge not receive should this access instruction performed by this first Thread module time, then assign this access right of execution to this second Thread module and in the physical page of another predetermined quantity among the described physical page by this second Thread module the page data of another predetermined quantity among described multiple page data being write to this second instance block via this data bus, wherein this second Thread module discharges this access right of execution after the page data of this another predetermined quantity among described multiple page data is write to this second instance block via this data bus.

4. data access method according to claim 1, also comprises:

Configure multiple logical blocks with at least part of described physical blocks of videoing;

Described logical blocks is divided into one first cut section and one second cut section;

By the described physical blocks of this first Thread module described logical blocks of this first cut section of access mapping independently; And,

By the described physical blocks of this second Thread module described logical blocks of this second cut section of access mapping independently,

Wherein this first instance block is videoed one of them of described logical blocks of this first cut section, one of them of the described logical blocks of this second cut section and this second instance block is videoed.

5. data access method according to claim 1, also comprises:

By this first Thread resume module one first instruction; And,

By this second Thread resume module one second instruction,

Wherein when this first instruction and this second instruction all need processed, this first instruction has precedence over this second instruction,

Wherein this access instruction belongs to this first instruction.

6. a data access method, for by multiple Thread module access data in a duplicative Nonvolatile memory module, this duplicative Nonvolatile memory module has multiple physical blocks, physical blocks described in each has multiple physical page of sequential, described Thread module comprises one first Thread module and one second Thread module, and this second Thread module performs a write instruction to be write to by multiple page data in the second instance block among described physical blocks, and this data access method comprises:

When judging that the number of the page data be not yet written among described multiple page data is non-and being less than this default threshold value, then judge whether to receive should one of performed by this first Thread module access instruction; And,

When judge to receive should this access instruction performed by this first Thread module time, assign this access right of execution to this first Thread module and perform this access instruction by this first Thread module via on the first instance block of this data bus among described physical blocks, wherein this first Thread module discharges this access right of execution after this access instruction of execution.

7. data access method according to claim 6, also comprises:

Assign an access right of execution to give this second Thread module and by this second Thread module the page data of the predetermined quantity among described multiple page data write to via a data bus in the physical page of the predetermined quantity among the described physical page in this second instance block, wherein this second Thread module discharges this access right of execution after the page data of this predetermined quantity is write to this second instance block via this data bus

Wherein the above-mentioned step judging whether the number of the page data be not yet written among described multiple page data is less than this default threshold value is performed after this second Thread module discharges this access right of execution.

8. data access method according to claim 7, also comprises:

After this first Thread module discharges this access right of execution, assign this access right of execution to this second Thread module and by this second Thread module the page data of another predetermined quantity among described multiple page data write to via this data bus in the physical page of another predetermined quantity among the described physical page in this second instance block, wherein this second Thread module discharges this access right of execution after another page data of this predetermined quantity among described multiple page data is write to this second instance block via this data bus.

9. data access method according to claim 7, also comprises:

When judge not receive should this access instruction performed by this first Thread module time, assign this access right of execution to this second Thread module and to be write to via this data bus by the page data of another predetermined quantity among described multiple page data by this second Thread module in the physical page of another predetermined quantity among the described physical page in this second instance block, wherein this second Thread module discharges this access right of execution after another page data of this predetermined quantity among described multiple page data is write to this second instance block via this data bus.

10. data access method according to claim 7, also comprises:

11. data access methods according to claim 6, also comprise:

Wherein when this first Thread module and this second Thread module all need to be performed, this first Thread module performs with a foreground mode, and this second Thread module performs with a background mode.

12. 1 kinds of Memory Controller Hub, for controlling a duplicative Nonvolatile memory module, wherein this duplicative Nonvolatile memory module has multiple physical blocks, and physical blocks described in each has multiple physical page of sequential, and this Memory Controller Hub comprises:

One memory interface, in order to be electrically connected to this duplicative Nonvolatile memory module; And,

One memory management circuit, is electrically connected to this memory interface, and wherein this memory management circuit is in order to perform a write instruction to be write to by multiple page data in the second instance block among described physical blocks,

Wherein this memory management circuit comprises one first Thread module, one second Thread module and is electrically connected to a resource distribution module of this first Thread module and this second Thread module,

Wherein this resource distribution module is in order to judge whether the number of the page data be not yet written among described multiple page data is less than one and presets threshold value,

Wherein when judging that the number of the page data be not yet written among described multiple page data is less than this default threshold value, this resource distribution module is in order to assign an access right of execution to this second Thread module and to be write in this second instance block via this data bus by the page data be not yet written among described multiple page data by this second Thread module

Wherein when judging that the number of the page data be not yet written among described multiple page data is non-and being less than this default threshold value, this resource distribution module is in order to assign this access right of execution to this second Thread module and in the physical page of this predetermined quantity among the page data of the predetermined quantity among described multiple page data to write in this second instance block by this second Thread module via this data bus described physical page, wherein this second Thread module discharges this access right of execution and this predetermined quantity is less than the page number that arbitrary described physical blocks has after the page data of this predetermined quantity is write to this second instance block via this data bus,

After this second Thread module discharges this access right of execution, this resource distribution module judge whether to receive should one of performed by this first Thread module access instruction; And,

When judge to receive should this access instruction performed by this first Thread module time, then this resource distribution module assigns this access right of execution to this first Thread module and this first Thread module performs this access instruction via on the first instance block of this data bus among described physical blocks, and wherein this first Thread module discharges this access right of execution after this access instruction of execution.

13. Memory Controller Hub according to claim 12,

Wherein after this first Thread module discharges this access right of execution, this resource distribution module assign this access right of execution to this second Thread module and this second Thread module the page data of another predetermined quantity among described multiple page data is write to this second instance block via this data bus described physical page among another predetermined quantity physical page in, wherein this second Thread module discharges this access right of execution after the page data of this another predetermined quantity among described multiple page data is write to this second instance block via this data bus.

14. 1 kinds of Memory Controller Hub, for controlling a duplicative Nonvolatile memory module, wherein this duplicative Nonvolatile memory module has multiple physical blocks, and physical blocks described in each has multiple physical page of sequential, and this Memory Controller Hub comprises:

Wherein this resource distribution module judges whether the number of the page data be not yet written among described multiple page data is less than one and presets threshold value,

Wherein when judging that the number of the page data be not yet written among described multiple page data is less than this default threshold value, then this resource distribution module assigns an access right of execution to give this second Thread module and the page data be not yet written among described multiple page data writes in this second instance block via this data bus by this second Thread module

Wherein when judging that the number of the page data be not yet written among described multiple page data is non-and being less than this default threshold value, then this resource distribution module judge whether to receive should one of performed by this first Thread module access instruction,

Wherein when judge to receive should this access instruction performed by this first Thread module time, this resource distribution module assigns this access right of execution to this first Thread module and this first Thread module performs this access instruction via on the first instance block of this data bus among described physical blocks, and wherein this first Thread module discharges this access right of execution after this access instruction of execution.

15. Memory Controller Hub according to claim 14, wherein this resource distribution module assigns an access right of execution to give this second Thread module and in the physical page of a predetermined quantity among the page data of the predetermined quantity among described multiple page data writes in this second instance block by this second Thread module via a data bus described physical page, wherein this second Thread module discharges this access right of execution after the page data of this predetermined quantity is write to this second instance block via this data bus

Wherein this resource distribution module is after this second Thread module discharges this access right of execution, judges whether the number of the page data be not yet written among described multiple page data is less than this default threshold value.

16. 1 kinds of internal storing memories, comprising:

One duplicative Nonvolatile memory module, has multiple physical blocks, and wherein physical blocks described in each has multiple physical page of sequential; And,

One Memory Controller Hub, be electrically connected to a connector and this duplicative Nonvolatile memory module, this Memory Controller Hub comprises a host interface, in order to be electrically connected to a memory interface of this duplicative Nonvolatile memory module and to be electrically connected to a memory management circuit of this memory interface

Wherein this memory management circuit is in order to perform a write instruction to be write to by multiple page data in the second instance block among described physical blocks,

17. internal storing memories according to claim 16,

18. internal storing memories according to claim 16,

Wherein when judge not receive should this access instruction performed by this first Thread module time, then this resource distribution module assign this access right of execution to this second Thread module and this second Thread module the page data of another predetermined quantity among described multiple page data is write to this second instance block via this data bus described physical page among another predetermined quantity physical page in, wherein this second Thread module discharges this access right of execution after the page data of this another predetermined quantity among described multiple page data is write to this second instance block via this data bus.

19. internal storing memories according to claim 16,

Wherein the multiple logical blocks of this memory management Circnit Layout is to video at least part of described physical blocks and described logical blocks is divided into one first cut section and one second cut section,

The wherein described physical blocks of this first Thread module described logical blocks of this first cut section of access mapping independently,

The wherein described physical blocks of this second Thread module described logical blocks of this second cut section of access mapping independently,

20. internal storing memories according to claim 16, wherein when this first Thread module and this second Thread module all need to be performed, this the first Thread module performs with a foreground mode, and this second Thread module performs with a background mode.

21. 1 kinds of internal storing memories, comprising:

22. internal storing memories according to claim 21, wherein this resource distribution module assigns an access right of execution to give this second Thread module and in the physical page of a predetermined quantity among the page data of the predetermined quantity among described multiple page data writes in this second instance block by this second Thread module via a data bus described physical page, wherein this second Thread module discharges this access right of execution after the page data of this predetermined quantity is write to this second instance block via this data bus

23. internal storing memories according to claim 22, wherein after this first Thread module discharges this access right of execution, this resource distribution module assigns this access right of execution to this second Thread module and in the physical page of another predetermined quantity among the page data of another predetermined quantity among described multiple page data writes in this second instance block by this second Thread module via this data bus described physical page, wherein this second Thread module discharges this access right of execution after the page data of this another predetermined quantity among described multiple page data is write to this second instance block via this data bus.

24. internal storing memories according to claim 22,

Wherein when judge not receive should this access instruction performed by this first Thread module time, this resource distribution module assigns this access right of execution to this second Thread module and in the physical page of another predetermined quantity among the page data of another predetermined quantity among described multiple page data writes in this second instance block by this second Thread module via this data bus described physical page, wherein this second Thread module discharges this access right of execution after the page data of this another predetermined quantity among described multiple page data is write to this second instance block via this data bus.

25. internal storing memories according to claim 22,

26. internal storing memories according to claim 21, wherein this first Thread module is in order to process one first instruction, and this second Thread module is in order to process one second instruction,

Wherein this access instruction belongs to this first instruction.