CN102647192A - Data processing method and device - Google Patents
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Abstract
The invention provides a data processing method and device, relating to the field of communication and solving the problems of big overhead and low computing performance of CNU hardware. The method has the following steps of: inputting m input numbers, and dividing the m input numbers into n input subsets; each input subset contains a plurality of input numbers, wherein n and m are integral numbers, and n is smaller than a half of m; respectively obtaining the minimum and the second minimum of each input subset; the minimums of the n input subsets form a minimum group, and the second minimums of the n input subsets form a second minimum group; obtaining the minimum and the second minimum of the minimum group, namely the minimum being the minimum of the m input numbers, and outputting the minimum of the m input numbers and the minimum index of the minimum; and obtaining the minimum of the second minimum group, comparing the minimum of the second minimum group with the second minimum of the minimum group, wherein the smaller value being the second minimum of the m input numbers, and outputting the second minimum of the m input numbers.
Description
Technical field
The present invention relates to the communications field, particularly, relate in particular to data processing method and device in a kind of low-density parity-check sign indicating number (LDPC) decoding.
Background technology
The LDPC sign indicating number is one type of linear block codes based on the sparse check matrix structure, is at first proposed in 1962 by Gallager, is proposed once more in 1996 by MacKay.The LDPC sign indicating number has huge application potential, will deep space communication, optical fiber communication, satellite digital video, digital watermarking, magnetic/light/Hologram Storage, move and fixed radio communication, cable modulator/demodulator and Digital Subscriber Line in be used widely.Especially in digital information transmission technical field, the LDPC sign indicating number has become the first-selection in the 4th third-generation mobile communication coding techniques.
Then, in the decoder implementation procedure, hardware resource takies higher, and the operating rate of decoder is lower.In the decoding flow process, there is the computing circuit of more complicated, wherein that outstanding is CNU.In the prior art, the comparison gate that compares in twos that CNU adopts multilayer to enumerate more realizes that hardware spending is bigger, and performance is low.
Summary of the invention
The invention provides a kind of data processing method and device, solved the problem that the CNU hardware spending is big, operational performance is low.
A kind of data processing method comprises:
Preferably, above-mentioned data processing method also comprises:
Said m minimum value and the sub-minimum of importing number of output sent to absolute value-complement code modular converter.
Preferably, said input subclass is mutually disjointed.
Preferably, said input subclass comprises three or four input numbers.
Preferably, the minimum value and the sub-minimum that obtain said minimum value group may further comprise the steps:
Step 3a, n value in the said minimum value group is divided into j grouping, wherein, j is an integer, and j≤n/2;
Step 3b, relatively draw said each minimum value and sub-minimum that divides into groups respectively, said each minimum value of dividing into groups constitutes new minimum value group;
Step 3c, repeated execution of steps 3a and 3b are until the minimum value of obtaining said minimum value group and sub-minimum.
Preferably, the minimum value of obtaining said sub-minimum group may further comprise the steps:
Step 4a, n value in the said sub-minimum group is divided into k grouping, wherein, k is an integer, and k≤n/2;
Step 4b, relatively draw said each minimum value of dividing into groups respectively, said each minimum value of dividing into groups constitutes new sub-minimum group;
Step 4c, repeated execution of steps 4a and 4b are until the minimum value of obtaining said sub-minimum group.
The present invention also provides a kind of data processing equipment, comprising:
The prime subelement is used to receive m input number, and said m input number is divided into n input subclass; Each input subclass comprises a plurality of input numbers, obtains minimum value and the sub-minimum of respectively importing subclass respectively, and the minimum value of said n input subclass constitutes the minimum value group; The sub-minimum of said n input subclass constitutes the sub-minimum group; Wherein, n and m are integer, and n＜m/2;
The intergrade subelement; Be used to obtain the minimum value and the sub-minimum of said minimum value group; This minimum value is the minimum value of said m input number, exports the minimum value of said m input number and the minimum value index of said minimum value, and the minimum value of obtaining said sub-minimum group;
Level subelement in back is used for and the minimum value of this sub-minimum group and the sub-minimum of said minimum value group is compared, and wherein less value is the sub-minimum of said m input number, exports said m the sub-minimum of importing number.
Preferably; Said intergrade subelement comprises many levels; The output of said prime subelement is connected to the input of ground floor intergrade subelement; The output of last one deck intergrade subelement is connected to the input of said back level subelement; The output of one or more layers intergrade subelement except that said last one deck intergrade subelement is connected to down the input of one deck dynatron unit or said back level subelement, and the output of a prime subelement only is connected to the input of a dynatron unit, and the input of a dynatron unit is connected with the output of a plurality of prime subelements.
Preferably, said prime subelement comprises a plurality of comparators, an encoder and a plurality of multichannel final election device, and said multichannel final election device comprises at least three data inputs and a selection signal input part;
The output of said comparator links to each other with said encoder, and the output of said encoder links to each other with the selection signal input part of said a plurality of multichannel final election devices respectively, said comparator and said a plurality of multichannel final election device shared data input.
Preferably, said intergrade subelement comprises a plurality of comparators and a plurality of multichannel final election device, and said multichannel final election device comprises at least two data inputs and a selection signal input part;
The output of said comparator is connected to the selection signal input part of said a plurality of multichannel final election devices, said comparator and said a plurality of multichannel final election device shared data input.
Preferably, said intergrade subelement comprises a plurality of comparators and a multichannel final election device, and said multichannel final election device comprises at least two data inputs and a selection signal input part;
The output of said comparator is connected to the selection signal input part of said multichannel final election device, said comparator and said multichannel final election device shared data input.
Preferably, said intergrade subelement comprises a multichannel final election device, and said multichannel final election device comprises at least two data inputs and a selection signal input part;
The intergrade subelement before the data input pin of said multichannel final election device and the said multichannel final election device place level or the output of prime subelement link to each other, and the selection signal input part of said multichannel final election device links to each other with the intergrade subelement before said multichannel final election device belongs to level or the output of prime subelement.
The invention provides a kind of data processing method and device, at first import m input number, said m input number is divided into n input subclass; Each input subclass comprises a plurality of input numbers, and wherein, n and m are integer; And n＜m/2 obtains minimum value and the sub-minimum of respectively importing subclass respectively, and the minimum value of said n input subclass constitutes the minimum value group; The sub-minimum of said n input subclass constitutes the sub-minimum group, obtains the minimum value and the sub-minimum of said minimum value group, and this minimum value is the minimum value of said m input number; Export the minimum value of said m input number and the minimum value index of said minimum value, obtain the minimum value of said sub-minimum group, and the minimum value of this sub-minimum group and the sub-minimum of said minimum value group are compared; Wherein less value is the sub-minimum of said m input number, exports the sub-minimum of said m input number, serves as to handle unit with the input subclass; Simplify treatment step, solved the problem that the CNU hardware spending is big, operational performance is low.
Description of drawings
The flow chart of a kind of data processing method that Fig. 1 provides for embodiments of the invention one;
The theory diagram of a kind of data processing method that Fig. 2 provides for embodiments of the invention two;
The iteration theorem block diagram of a kind of data processing method that Fig. 3 provides for embodiments of the invention two;
The iteration theorem block diagram of a kind of data processing method that Fig. 4 provides for embodiments of the invention three;
Fig. 5 is the prime sub-unit structure figure of four inputs, three outputs in the embodiments of the invention three;
Fig. 6 is the intergrade sub-unit structure figure of three inputs, three outputs in the embodiments of the invention three;
Fig. 7 is the intergrade sub-unit structure figure of three inputs, one output in the embodiments of the invention three;
Fig. 8 is the intergrade sub-unit structure figure of two inputs, three outputs in the embodiments of the invention three;
Fig. 9 is the intergrade sub-unit structure figure of two inputs, one output in the embodiments of the invention three;
Figure 10 is the intergrade sub-unit structure figure of three inputs, one output in the embodiments of the invention three;
Figure 11 is the intergrade sub-unit structure figure of three inputs, one output in the embodiments of the invention three;
Figure 12 is the back intercaste sub-unit structure figure of three inputs, one output in the embodiments of the invention three;
Figure 13 is the CNU structural representation that has used the data processing equipment that embodiments of the invention provide.
Embodiment
Embodiments of the invention provide a kind of data processing method and device, have solved the problem that the CNU hardware spending is big, computing low energy is low.Hereinafter will combine accompanying drawing that embodiments of the invention are elaborated.Need to prove that under the situation of not conflicting, embodiment among the application and the characteristic among the embodiment be combination in any each other.
At first, embodiments of the invention one are described.
Embodiments of the invention one provide a kind of data processing equipment, comprising:
The prime subelement is used for n input number is divided into m input subclass, and each input subclass comprises a plurality of input numbers; Obtain minimum value and the sub-minimum of respectively importing subclass respectively; The minimum value of said m input subclass constitutes the minimum value group, and the sub-minimum of said m input subclass constitutes the sub-minimum group, wherein; M and n are integer, and m＜n/2;
The intergrade subelement is used to obtain the minimum value and the sub-minimum of said minimum value group, and this minimum value is the minimum value of said n input number, obtains the minimum value index of said minimum value, and the minimum value of obtaining said sub-minimum group;
Level subelement in back is used for and the minimum value of this sub-minimum group and the sub-minimum of said minimum value group is compared, and wherein less value is said n the sub-minimum of importing number.
Preferably; Said intergrade subelement comprises many levels; The output of said prime subelement is connected to the input of ground floor intergrade subelement; The output of last one deck intergrade subelement is connected to the input of said back level subelement; The output of one or more layers intergrade subelement except that said last one deck intergrade subelement is connected to down the input of one deck dynatron unit or said back level subelement, and the output of a prime subelement only is connected to the input of a dynatron unit, and the input of a dynatron unit is connected with the output of a plurality of prime subelements.
Preferably, said prime subelement comprises a plurality of comparators, an encoder and a plurality of multichannel final election device, and said multichannel final election device comprises at least three data inputs and a selection signal input part;
The output of said comparator links to each other with said encoder, and the output of said encoder links to each other with the selection signal input part of said a plurality of multichannel final election devices respectively, said comparator and said a plurality of multichannel final election device shared data input.
Preferably, said intergrade subelement comprises a plurality of comparators and a plurality of multichannel final election device, and said multichannel final election device comprises at least two data inputs and a selection signal input part;
The output of said comparator is connected to the selection signal input part of said a plurality of multichannel final election devices, said comparator and said a plurality of multichannel final election device shared data input.
Preferably, said intergrade subelement comprises a plurality of comparators and a multichannel final election device, and said multichannel final election device comprises at least two data inputs and a selection signal input part;
The output of said comparator is connected to the selection signal input part of said multichannel final election device, said comparator and said multichannel final election device shared data input.
Preferably, said intergrade subelement comprises a multichannel final election device, and said multichannel final election device comprises at least two data inputs and a selection signal input part;
The intergrade subelement before the data input pin of said multichannel final election device and the said multichannel final election device place level or the output of prime subelement link to each other, and the selection signal input part of said multichannel final election device links to each other with the intergrade subelement before said multichannel final election device belongs to level or the output of prime subelement.
Below in conjunction with said apparatus, embodiments of the invention two are described.
Embodiments of the invention provide a kind of data processing method, and it is as shown in Figure 1 to use this method to obtain the flow process of minimum value, comprising:
Suppose a finite aggregate V who is made up of real number, comprise m input number among the V, V can be divided into a limited number of subclass v
0, v
1..., v
N-1, n ∈ Z
+, and the norator of V set mutually disjoints, that is:
V＝v
0∪v
1∪...∪v
n (1)
Wherein, 0≤i, j≤n and i ≠ j.
Suitably the chooser set sizes can realize the retrieval of minimum value and sub-minimum with the combination of minimum comparator and final election device.
To each input subclass min (v that minimizes
i) and sub-minimum min2nd (v
i), the minimum value of then gathering among the V is:
min(V)＝min({min(v
i)})，i＝0，1，...，n-1 (3)
Sub-minimum is among the set V:
min
2nd(V)＝min(min({min
2nd(v
i)})，min
2nd({min(v
i)}))，i＝0，1，...，n-1 (4)
Can obtain the minimum value group according to formula (3), according to formula (4) or acquisition sub-minimum group.
The theory diagram that carries out minimum value, sub-minimum retrieval according to above-mentioned steps is as shown in Figure 2.
According to embodiments of the invention one Chinese style (3), formula (4) and method shown in Figure 2; Increase in grouping; Be that the minimum value of intergrade and the input of sub-minimum also increase thereupon, at this moment under the situation of n value increase; Also have very big space that intergrade is optimized, promptly intergrade can have more complicated hierarchical structure.In addition, prime also can have different influences to the resource consumption of global design to the different grouping of the data acquisition system of input.In order to address the above problem, embodiments of the invention two provide a kind of data processing method, use the flow process of this method following:
If a finite aggregate V who is made up of real number, V can be divided into some mutually disjoint subclass v
0, v
1..., v
N-1, n ∈ Z
+, and
0≤k ≠ l≤n-1; Wherein, norator set v
i, i=0,1 ..., n-1 is by some mutually disjoint subclass u
0, u
1...,
n
i∈ Z
+Form, and
0≤i ≠ j≤n
i-1, the minimum value of then gathering V is:
min(V)＝min({v
i})，0≤i≤n-1 (5)
Can obtain the minimum value group according to formula (5).
Sub-minimum is:
min2nd(V)＝min({min2nd(v
i)}，min2nd({min(v
i)}))，0≤i≤n-1 (6)
Can obtain the sub-minimum group according to formula (6).
Wherein:
min(v
i)＝min({u
k})，0≤k≤n
i-1 (7)
min2nd(v
i)＝min({min2nd(u
k)}，min2nd({min(u
k)}))，0≤k≤n
i-1 (8)
Can obtain by formula (5)-Shi (6):
min(V)＝min({min
i{min(u
k)}})，0≤i≤n-1，0≤k≤n
i-1 (9)
min2nd(V)
＝min(min({min2nd
i(u
k)})，min2nd({min
i(u
k)}))，0≤i≤n-1，0≤k≤n
i-1 (10)
Formula (9) and formula (10) are explained and can be adopted the method realization minimum value of iteration and the retrieval of sub-minimum through the division again to minimum value group and sub-minimum group.
The flow process of the minimum value group being carried out iteration is following:
1, n value in the said minimum value group is divided into j grouping, wherein, j is an integer, and j≤n/2;
2, obtain said each minimum value and sub-minimum that divides into groups respectively, said each minimum value of dividing into groups constitutes new minimum value group;
3, repeated execution of steps 1 and 2 is until the minimum value of obtaining said minimum value group and sub-minimum.
The flow process of the sub-minimum group being carried out iteration is following:
1, n value in the said sub-minimum group is divided into k grouping, wherein, k is an integer, and k≤n/2;
2, obtain said each minimum value of dividing into groups respectively, said each minimum value of dividing into groups constitutes new sub-minimum group;
3, repeated execution of steps 1 and 2 is until the minimum value of obtaining said sub-minimum group.
In the flow process that reality is carried out, it is as a whole, specific as follows that iteration is obtained the flow process of minimum value and sub-minimum:
1, one group of input number is carried out many groups and divide, to every group of retrieval of carrying out minimum value, sub-minimum respectively of dividing, and the index of output minimum value, get into step 2;
2, the sub-minimum and the minimum value that retrieval are obtained divide sub-minimum group and minimum value group respectively into, the minimum value group is returned step 1 heavily divide into groups and retrieve, and the sub-minimum group gets into step 3; If this minimum value is a final result, get into step 4;
3, the sub-minimum group is divided into groups again, ask the minimum value of sub-minimum group;
4, at last the sub-minimum of minimum value group and the minimum value of sub-minimum group are compared, the minimum value that relatively obtains promptly is the sub-minimum of all inputs.
The minimum value that the method for employing iteration realizes and the retrieval design of sub-minimum are as shown in Figure 3, and wherein, finally finding the solution of sub-minimum group can select suitable grouping and compound mode to realize according to the actual optimization situation.
Below in conjunction with accompanying drawing, embodiments of the invention three are described.
The embodiment of the invention is an example with 24 input numbers, and the process of a kind of data processing method of using embodiments of the invention to provide being obtained maximum and minimum value and output from the input data describes.Concrete; Adopt and elementaryly be divided into 4 element subclass, middle rank is divided into 3 element subclass; The back level is divided into the mode of 2 element subclass and carries out the retrieval of minimum value and sub-minimum, and its theory diagram is as shown in Figure 4, each subclass is carried out the retrieval of minimum value and/or sub-minimum by the multilayer subelement; Wherein each sub-cells such as Fig. 5 are to shown in Figure 12; Subelement uses comparator that minimum value, sub-minimum are retrieved, and makes total design reduce the usage quantity of comparator and final election device simultaneously, has significantly reduced the consumption of logic.
Concrete, shown in Figure 5 is the subelement of one or four inputs (four subclass that the input number constitutes), two outputs (a minimum value output I_MIN, a sub-minimum output I_MIN2nd), optional, also comprises the output of a minimum value index Index.Use
individual comparator that A, B, C, four inputs of D number are compared completely; Encoder confirms codimg logic through encoder, and with the selection signal of this logic as the final election device.In fact can not only confirm minimum and sub-minimum among A, B, C, the D, also can sort completely A, B, C, D.Only needing to confirm under the situation of minimum value and sub-minimum that this subelement only needs the codimg logic of 6 comparators, 2 final election devices and 2 groups of final election device selection signals.The codimg logic expression formula of this encoder is following:
Need to prove that preceding text have only provided a kind of available encoder logic, the encoder logic that other realization minimum values, sub-minimum obtain is also in protection range of the present invention.
Among Fig. 5, A, B, C, D obtain 6 comparative results after relatively in twos, and by these 6 comparative results, according to above-mentioned logical expression, coding obtains two groups of multiplexer select signals, and every group of multiplexer select signal is 2 bit wides, the final election device of corresponding 4 inputs.Wherein, the index of the minimum value that obtains behind the I_MIN presentation code, the index of the sub-minimum that obtains behind the I_MIN2nd presentation code, the index value of coding is the input position of corresponding A, B, C, D respectively.Fig. 5 has exported the index Index of minimum value, supplies other subelements to use.
Subelement shown in Figure 5 need not carry out final election to data in comparison procedure, the number of comparators of use is also fewer.And the structure of four inputs (2 power time) is beneficial to divides into groups and simplifies the index coding of inter-stage the set of multielement, has optimized to design and reduced resource consumption.Generally as elementary subelement.In input number quantity more for a long time, also can be through multilayer four input subelements shown in Figure 5, will import that number repeatedly screens and dividing subset is closed.
Fig. 6 is the subelement of one or three inputs (three subclass that the input number constitutes), two outputs (a minimum value output I_MIN, a sub-minimum output I_MIN2nd), and is optional, also comprises minimum value index Index output.This subelement uses
individual comparator that A, B, C three numbers are compared fully, and can sort to this three number.
Among Fig. 6, A, B, C obtain 3 comparative results after relatively in twos.Can encode to these three comparative result LT_AB, LT_BC, LT_AC, obtain two groups of multiplexer select signals of similar Fig. 5, reduce consumption final election device resource; Also can directly use these three comparative results, simplify logical level as multiplexer select signal.But in practical application, this part combinational circuit might comprehensively become same circuit.As signal, shown in Figure 6 for three comparative results not being encoded, but directly with its situation as the selection signal of final election device, the final election principle of the back output signal that compared result is encoded is identical with subelement shown in Figure 5, repeats no more at this.
Shown in Figure 7 is the subelement of one or three inputs (three subclass that the input number a constitutes) output (a minimum value output I_MIN), and it realizes that principle is identical with subelement shown in Figure 6, only is to have removed sub-minimum final election device.
Shown in Figure 8 is the subelement of one or two inputs (two subclass that the input number a constitutes) output (a minimum value output I_MIN), on the basis of the circuit (Fig. 9) of common comparison minimum value, has increased sub-minimum final election device.
Figure 10 and Figure 11 are the subelement of three inputs, one output, and its input and output are index value (can be the minimum value index, also can be the sub-minimum index), are specially the index encoder.In prime, 24 input numbers have been divided into 2 half, every partly 3 groups, import minimum value, sub-minimum comparator for totally 6 group 4.In prime; The minimum value index (2) that the advantage of 4 inputs is embodied in each group has directly reflected minimum two of final index; If promptly a certain group minimum value is exactly the minimum value of final output in these 6 groups, minimum value index of this group output is exactly minimum two of minimum value index of final output so.Therefore, minimum two actual can generations of final index by 6: 1 final election devices.Because design is relevant with the iteration level, so example design adopted 3: 1 and final election device cascade final election in 2: 1 realizes.
The index encoder of Figure 10 produces the minimum value index of 12 inputs of upper half number according to the minimum value index of three input minimum value comparator outputs of the upper half of intergrade.In fact the minimum index of upper half has only 4 (highest order is 0), and low two final elections are from the minimum index of three groups of comparators of prime, the generation of encoding of high two minimum index (comparative result) by three input minimum values, sub-minimum.Below for realizing a kind of logical expression group of this index encoder:
I7＝{LT_AB，LT_AC，LT_BC}
I9[4]＝0
The index encoder of Figure 11 produces the minimum value index of 12 inputs of bottom half number according to the minimum value index of three input minimum value comparator outputs of the bottom half of intergrade.Different with upper half, the border of the Senior Three position that is next to upper half of the Senior Three position of bottom half index, so codimg logic and Figure 10 are different.Below for realizing a kind of logical expression group of this index encoder:
I10[3]＝LT_AB<_AC
I8＝{LT_AB，LT_AC，LT_BC}
Shown in Figure 12 is one or two subelements exported, and its input and output are index value (can be the minimum value index, also can be the sub-minimum index).From two inputs, select the minimum value index of first sheet or second sheet.
Because the quantity that the element of n element subclass is minimized with the needed comparator of sub-minimum is n (n-1)/2, only use 2 n: 1 final election device.On this basis, suitably the chooser set sizes can realize the retrieval design of minimum value and sub-minimum with the combination of minimum comparator and final election device.Used the CNU structure of the data processing equipment that embodiments of the invention provide shown in figure 13.Wherein, Min&min2SORTER is minimum value, sub-minimum retrieval module (being the data processing equipment that embodiments of the invention provide); CC2ABS is data complement code-absolute value modular converter; ABS2CC is absolute value-complement code modular converter, and XOR Logics calculates the symbol of each check-node, and Sign Modifier is in order to revise the null value symbol; MUXes Data Distibuter is all check-node information of output under the effect of the selection of Docoder and sign out, finally accomplish the parallel computation function of CNU.Prime CC2ABS is the conversion circuit of complement code number to absolute value number; Wherein, the distribution of negative and integer is also asymmetric, if do not want to increase for negative the data bit width of absolute value, then need under the condition that allows, be similar to by the maximum value to negative.The symbol and the absolute value of each number of CC2ABS output.Symbol is asked symbol to connect in XOR LOGICs and is taken advantage of, and adiabatic index is minimized in minimum value and sub-minimum comparison circuit, sub-minimum and minimum value index.The company of output takes advantage of symbol to proofread and correct, to eliminate the ambiguity of absolute value 0 in changing into the complement code process.The minimum value of output and sub-minimum at first carry out the complement code conversion, are selected the result of each required output in road by index decoder and output symbol.
Below, embodiments of the invention four are described.
The embodiment of the invention provides a kind of data processing equipment, comprising:
The prime subelement is used to receive m input number, and said m input number is divided into n input subclass; Each input subclass comprises a plurality of input numbers, obtains minimum value and the sub-minimum of respectively importing subclass respectively, and the minimum value of said n input subclass constitutes the minimum value group; The sub-minimum of said n input subclass constitutes the sub-minimum group; Wherein, n and m are integer, and n＜m/2;
The intergrade subelement; Be used to obtain the minimum value and the sub-minimum of said minimum value group; This minimum value is the minimum value of said m input number, exports the minimum value of said m input number and the minimum value index of said minimum value, and the minimum value of obtaining said sub-minimum group;
Level subelement in back is used for and the minimum value of this sub-minimum group and the sub-minimum of said minimum value group is compared, and wherein less value is the sub-minimum of said m input number, exports said m the sub-minimum of importing number.
Preferably; Said intergrade subelement comprises many levels; The output of said prime subelement is connected to the input of ground floor intergrade subelement; The output of last one deck intergrade subelement is connected to the input of said back level subelement; The output of one or more layers intergrade subelement except that said last one deck intergrade subelement is connected to down the input of one deck dynatron unit or said back level subelement, and the output of a prime subelement only is connected to the input of a dynatron unit, and the input of a dynatron unit is connected with the output of a plurality of prime subelements.
Preferably, said prime subelement comprises a plurality of comparators, an encoder and a plurality of multichannel final election device, and said multichannel final election device comprises at least three data inputs and a selection signal input part;
The output of said comparator links to each other with said encoder, and the output of said encoder links to each other with the selection signal input part of said a plurality of multichannel final election devices respectively, said comparator and said a plurality of multichannel final election device shared data input.
Preferably, said intergrade subelement comprises a plurality of comparators and a plurality of multichannel final election device, and said multichannel final election device comprises at least two data inputs and a selection signal input part;
The output of said comparator is connected to the selection signal input part of said a plurality of multichannel final election devices, said comparator and said a plurality of multichannel final election device shared data input.
Preferably, said intergrade subelement comprises a plurality of comparators and a multichannel final election device, and said multichannel final election device comprises at least two data inputs and a selection signal input part;
The output of said comparator is connected to the selection signal input part of said multichannel final election device, said comparator and said multichannel final election device shared data input.
Preferably, said intergrade subelement comprises a multichannel final election device, and said multichannel final election device comprises at least two data inputs and a selection signal input part;
The intergrade subelement before the data input pin of said multichannel final election device and the said multichannel final election device place level or the output of prime subelement link to each other, and the selection signal input part of said multichannel final election device links to each other with the intergrade subelement before said multichannel final election device belongs to level or the output of prime subelement.
Said apparatus can be applicable among the CNU, realizes the function of min&min2nd SORTER module shown in Figure 12.
The data processing equipment that embodiments of the invention four are provided combines with a kind of data processing method that embodiments of the invention one to three provide, and the invention provides a kind of data processing method and device, at first n input number is divided into m input subclass; Each input subclass comprises a plurality of input numbers, and wherein, m and n are integer; And m＜n/2 obtains minimum value and the sub-minimum of respectively importing subclass then respectively, and the minimum value of said m input subclass constitutes the minimum value group; The sub-minimum of said m input subclass constitutes the sub-minimum group; Obtain the minimum value and the sub-minimum of said minimum value group afterwards, this minimum value is the minimum value of said n input number, obtains the minimum value index of said minimum value; Obtain the minimum value of said sub-minimum group; And the minimum value of this sub-minimum group and the sub-minimum of said minimum value group compared, wherein less value is the sub-minimum of said n input number, serves as to handle unit with the input subclass; Simplify treatment step, solved the problem that the CNU hardware spending is big, operational performance is low.Technical scheme that embodiments of the invention provided adopts retrieval minimum value, sub-minimum and exports the CUN (Figure 13) that the method design of its index has computation capability; Compared with prior art; Reached the effect of remarkable optimization CNU design; Saved the quantity of a large amount of comparators and final election device; Improved the sharing efficiency of CNU to logical resource, to design fast, have great importance on the ldpc decoder of the big code length code word of parallel processing, under the effect of degree of parallelism; Reduce to have reduced the logic consumption of ldpc decoder significantly, to the small size of design parallel processing big code length code word, efficiently, at a high speed, the ldpc decoder of big throughput has important realization meaning and using value.
The all or part of step that the one of ordinary skill in the art will appreciate that the foregoing description program circuit that can use a computer is realized; Said computer program can be stored in the computer-readable recording medium; Said computer program (like system, unit, device etc.) on the relevant hardware platform is carried out; When carrying out, comprise one of step or its combination of method embodiment.
Alternatively, all or part of step of the foregoing description also can use integrated circuit to realize, these steps can be made into integrated circuit modules one by one respectively, perhaps a plurality of modules in them or step is made into the single integrated circuit module and realizes.Like this, the present invention is not restricted to any specific hardware and software combination.
Each device/functional module/functional unit in the foregoing description can adopt the general calculation device to realize, they can concentrate on the single calculation element, also can be distributed on the network that a plurality of calculation element forms.
Each device/functional module/functional unit in the foregoing description is realized with the form of software function module and during as independently production marketing or use, can be stored in the computer read/write memory medium.The above-mentioned computer read/write memory medium of mentioning can be a read-only memory, disk or CD etc.
Any technical staff who is familiar with the present technique field can expect changing or replacement in the technical scope that the present invention discloses easily, all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the described protection range of claim.
Claims (12)
1. a data processing method is characterized in that, comprising:
Step 1, m input of input number are divided into n input subclass with said m input number, and each input subclass comprises a plurality of input numbers, and wherein, n and m are integer, and n＜m/2;
Step 2, obtain minimum value and the sub-minimum of respectively importing subclass respectively, the minimum value of said n input subclass constitutes the minimum value group, the sub-minimum formation sub-minimum group of said n input subclass;
Step 3, the minimum value of obtaining said minimum value group and sub-minimum, this minimum value are the minimum value of said m input number, export the minimum value of said m input number and the minimum value index of said minimum value;
Step 4, obtain the minimum value of said sub-minimum group, and the minimum value of this sub-minimum group and the sub-minimum of said minimum value group are compared, wherein less value is the sub-minimum of said m input number, exports said m the sub-minimum of importing number.
2. data processing method according to claim 1 is characterized in that, this method also comprises:
Said m minimum value and the sub-minimum of importing number of output sent to absolute value-complement code modular converter.
3. data processing method according to claim 1 is characterized in that, said input subclass is mutually disjointed.
4. data processing method according to claim 1 is characterized in that, said input subclass comprises three or four input numbers.
5. data processing method according to claim 1 is characterized in that, the minimum value and the sub-minimum that obtain said minimum value group may further comprise the steps:
Step 3a, n value in the said minimum value group is divided into j grouping, wherein, j is an integer, and j≤n/2;
Step 3b, relatively draw said each minimum value and sub-minimum that divides into groups respectively, said each minimum value of dividing into groups constitutes new minimum value group;
Step 3c, repeated execution of steps 3a and 3b are until the minimum value of obtaining said minimum value group and sub-minimum.
6. data processing method according to claim 1 is characterized in that, the minimum value of obtaining said sub-minimum group may further comprise the steps:
Step 4a, n value in the said sub-minimum group is divided into k grouping, wherein, k is an integer, and k≤n/2;
Step 4b, relatively draw said each minimum value of dividing into groups respectively, said each minimum value of dividing into groups constitutes new sub-minimum group;
Step 4c, repeated execution of steps 4a and 4b are until the minimum value of obtaining said sub-minimum group.
7. a data processing equipment is characterized in that, comprising:
The prime subelement is used to receive m input number, and said m input number is divided into n input subclass; Each input subclass comprises a plurality of input numbers, obtains minimum value and the sub-minimum of respectively importing subclass respectively, and the minimum value of said n input subclass constitutes the minimum value group; The sub-minimum of said n input subclass constitutes the sub-minimum group; Wherein, n and m are integer, and n＜m/2;
The intergrade subelement; Be used to obtain the minimum value and the sub-minimum of said minimum value group; This minimum value is the minimum value of said m input number, exports the minimum value of said m input number and the minimum value index of said minimum value, and the minimum value of obtaining said sub-minimum group;
Level subelement in back is used for and the minimum value of this sub-minimum group and the sub-minimum of said minimum value group is compared, and wherein less value is the sub-minimum of said m input number, exports said m the sub-minimum of importing number.
8. data processing equipment according to claim 7; It is characterized in that; Said intergrade subelement comprises many levels; The output of said prime subelement is connected to the input of ground floor intergrade subelement, and the output of last one deck intergrade subelement is connected to the input of said back level subelement, and the output of one or more layers intergrade subelement except that said last one deck intergrade subelement is connected to down the input of one deck dynatron unit or said back level subelement; The output of a prime subelement only is connected to the input of a dynatron unit, and the input of a dynatron unit is connected with the output of a plurality of prime subelements.
9. according to claim 7 or 8 described data processing equipments; It is characterized in that; Said prime subelement comprises a plurality of comparators, an encoder and a plurality of multichannel final election device, and said multichannel final election device comprises at least three data inputs and a selection signal input part;
The output of said comparator links to each other with said encoder, and the output of said encoder links to each other with the selection signal input part of said a plurality of multichannel final election devices respectively, said comparator and said a plurality of multichannel final election device shared data input.
10. according to claim 7 or 8 described data processing equipments, it is characterized in that said intergrade subelement comprises a plurality of comparators and a plurality of multichannel final election device, said multichannel final election device comprises at least two data inputs and a selection signal input part;
The output of said comparator is connected to the selection signal input part of said a plurality of multichannel final election devices, said comparator and said a plurality of multichannel final election device shared data input.
11., it is characterized in that said intergrade subelement comprises a plurality of comparators and a multichannel final election device according to claim 7 or 8 described data processing equipments, said multichannel final election device comprises at least two data inputs and a selection signal input part;
The output of said comparator is connected to the selection signal input part of said multichannel final election device, said comparator and said multichannel final election device shared data input.
12., it is characterized in that said intergrade subelement comprises a multichannel final election device according to claim 7 or 8 described data processing equipments, said multichannel final election device comprises at least two data inputs and a selection signal input part;
The intergrade subelement before the data input pin of said multichannel final election device and the said multichannel final election device place level or the output of prime subelement link to each other, and the selection signal input part of said multichannel final election device links to each other with the intergrade subelement before said multichannel final election device belongs to level or the output of prime subelement.
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| CN1770641A (en) * | 2005-11-21 | 2006-05-10 | 东南大学 | Minimal sum decoding method based on grading excursion correction |
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