CN102646627B - Soft error rate (SER) reduction in advanced silicon processes - Google Patents

Soft error rate (SER) reduction in advanced silicon processes Download PDF

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CN102646627B
CN102646627B CN201210035521.1A CN201210035521A CN102646627B CN 102646627 B CN102646627 B CN 102646627B CN 201210035521 A CN201210035521 A CN 201210035521A CN 102646627 B CN102646627 B CN 102646627B
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boron
rich
substrate
semiconductor device
conductive contact
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CN102646627A (en
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李永辉
蔡超杰
吴佳芳
李正中
曲维正
桂东
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

Provided is a method of fabricating a semiconductor device. The method includes providing a substrate. The method includes forming a portion of an interconnect structure over the substrate. The portion of the interconnect structure has an opening. The method includes obtaining a boron-containing gas that is free of a boron-10 isotope. The method includes filling the opening with a conductive material to form a contact. The filling of the opening is carried out using the boron-containing gas. Also provided is a semiconductor device. The semiconductor device includes a substrate. The semiconductor device includes an interconnect structure formed over the substrate. The semiconductor device includes a conductive contact formed in the interconnect structure. The conductive contact has a material composition that includes Tungsten and Boron, wherein the Boron is a 11B-enriched Boron.

Description

Soft error rate (SER) in advanced silicon process reduces
The cross reference of related application
The sequence number that this application claims " SOFT ERROR RATE (SER) the REDUCTION IN ADVANED SILICON PROCES SES " by name submitted on August 4th, 2010 is No.61/370, the priority of the provisional application of 671, its full content is hereby expressly incorporated by reference.
Technical field
Relate generally to semiconductor applications of the present invention, more specifically, relates to semiconductor device and manufacture method thereof.
Background technology
Semiconductor integrated circuit (IC) industry experienced by fast development.The technological progress of IC material and design aspect creates many for IC, and wherein, every generation all has than last Dai Geng little and more complicated circuit.But, these progressive complexity adding process and manufacture IC.In the process of integrated circuit evolution, function density (that is, the quantity of the interconnect devices of per unit chip area) increases usually, and physical dimension (that is, the minimal modules that manufacturing process can be used to create) reduces simultaneously.This scaled technique provides advantage by increasing product efficiency and reducing relevant cost usually.
Along with dimensions of semiconductor devices continues to shrink, soft error rate (soft error rate, SER) may become problem.Soft error is the mistake caused by the mistake in device or incorrect signal (such as, by noise), thus causes the maloperation of device, and device itself may not have defect.Soft error rate is the ratio that device runs into soft error.Along with semiconductor technology node is developed to more of new generation, especially for the device manufactured according to 65 nanometers (nm) node and node afterwards, the soft error rate for these devices becomes more remarkable.Current semiconductor manufacturing technology does not also propose to reduce the effective ways about the soft error rate of more recent technology node.
Thus although the existing method reduced for the soft error rate of semiconductor device is enough to reach its expection object usually, they can not be entirely satisfactory in each.
Summary of the invention
In order to solve defect existing in prior art, according to an aspect of the present invention, providing a kind of method, comprising: substrate is provided; Square one-tenth contact hole over the substrate; And use is rich in 11the boron material of B forms conductive contact piece in described contact hole.
In the method, be rich in described in 11the boron material of B 11b content is in fact higher than boron material 11b content.
In the method, be rich in described in 11the boron material of B 11b content is higher than about 95%.
In the method, the mode comprising tungsten with described conductive contact piece is implemented to form described conductive contact piece.
In the method, form described conductive contact piece to comprise: be rich in described in use 11the boron material of B forms tungstenic Seed Layer.
In the method, form described conductive contact piece to comprise: in described contact hole, form tungstenic Seed Layer by ald (ALD) technique; Wherein, be rich in described in described ALD technique 11the boron material of B is used as precursor.
In the method, form described conductive contact piece and comprise further: after described ALD technique, implement chemical vapor deposition (CVD) technique, described CVD technique forms tungsten material above described tungstenic Seed Layer.
In the method, described method is implemented as the part of manufacturing process of technology node belonging to below 90-nm technology node.
The method comprises further: before the described contact hole of formation, form transistor at least partially in described substrate, described transistor has channel region; Wherein, the mode being less than about 0.5 micron with conductive contact piece and interval, described channel region is implemented to form described conductive contact piece.
According to a further aspect in the invention, provide a kind of method, comprising: substrate is provided; A part for square one-tenth interconnection structure over the substrate, a part for described interconnection structure has opening; Acquisition there is no 10the isotopic boron-containing gas of B; And with opening described in filled with conductive material to form contact, use described boron-containing gas to implement to fill.
In the method, described boron-containing gas comprises 11b isotope, and wherein, described in described boron 11the isotopic concentration of B is greater than about 99.7%, and wherein, described in described boron 10the isotopic concentration of B is less than about 0.3%.
In the method, the mode being tungsten plug with described contact is implemented to fill described opening.
In the method, fill described opening and comprise: use ald (ALD) technique to form Seed Layer in said opening, in described ALD technique, described boron-containing gas is used as precursor; And use chemical vapor deposition (CVD) technique to form tungsten material above described Seed Layer.
The method comprises further: before the described interconnection structure of formation, form transistor at least in part in described substrate; Wherein, described conductive contact piece is formed as be less than about 0.5 micron apart from the channel region of described transistor.
According to another aspect of the invention, provide a kind of semiconductor device, comprising: substrate; Interconnection structure, is formed in described types of flexure; And conductive contact piece, be formed in described interconnection structure, described conductive contact piece has the material composition comprising tungsten and boron, and wherein, described boron is rich in 11the boron of B.
In this semiconductor device, described in be rich in 11the boron of B 11b content is in fact higher than boron material 11b content.
In this semiconductor device, described in be rich in 11the boron of B 11b content is higher than about 95%.
In this semiconductor device, described in be rich in 11the boron of B there is no 10b isotope.
This semiconductor device comprises further: be formed in the transistor in described substrate, and wherein, channel region and the described conductive contact piece interval of described transistor are less than about 0.5 micron.
In this semiconductor device, described semiconductor device belongs to the semiconductor technology generation being less than the 90-era of nanotechnology.
Accompanying drawing explanation
When reading in conjunction with the accompanying drawings, many aspects of the present invention are understood best by following detailed description.It is emphasized that, according to the standard practices in industry, multiple parts are not drawn in proportion.In fact, for the purpose of discussing and knowing, the size of multiple parts can increase arbitrarily or reduce.
Fig. 1 is the flow chart of the method for the synthesis of the boron gas after purification illustrated according to many aspects of the present invention.
Fig. 2 illustrates the flow chart utilizing the method for the boron gas after purification in semiconductor fabrication process according to many aspects of the present invention.
Fig. 3-Fig. 4 is according to the schematic section cross-sectional side view of the method shown in Fig. 1 and Fig. 2 at the semiconductor device of fabrication stage.
Fig. 5 is the chart of the simulation result that the correlation between soft error rate and the concentration of B-10 represented in tungsten plug is shown.
Fig. 6 is the flow chart of the method for the manufacture semiconductor device that method disclosed in Fig. 1 and Fig. 2 is shown.
Embodiment
Should be appreciated that, below invention is provided for the multiple different embodiment or the example that realize different characteristic of the present invention.The particular instance of assembly and layout is below described, to simplify the present invention.Certainly, these are only example and are not used in restriction.And, in the following description, the formation of first component above second component can comprise the embodiment that the first and second parts directly contact formation, and can comprise and can form optional feature between the first and second parts, make the embodiment that the first and second parts can not directly contact.In order to simple and clear, multiple parts can be drawn arbitrarily by different size.
Fig. 1 is the flow chart of the method 10 for the synthesis of the B-11 isotope gas after purification illustrated according to many aspects of the present invention.Subsequently discuss in, B-11 and 11b can use instead, to specify boron-11 isotope.Similarly, B-10 and 10B can use instead, to specify boron-10 isotope.B-10 and B-11 is the different isotopes of boron, and eachly has five protons.But isotope B-10 has five neutrons, but isotope B-11 has six neutrons.In fact, B-10 and B-11 according to about 20%/80% share (about 20%B-10 and about 80%B-11) exist.
With reference to figure 1, method 10 relates to multistage exchange-distillation process (multi-stageexchange-distillation process).The method 10 comprises frame 20, wherein, and synthesis 11bF 3gas.In an embodiment, following chemical reaction process is used for generate 11bF 3gas:
11bF 3o (CH 3) 2+ 10bF 3<=> 10bF 3o (CH 3) 2+ 11bF 3(the first chemical reaction process (first chemical process))
Wherein, 11bF 3o (CH 3) 2with 10bF 3o (CH 3) 2for liquid form, and 10bF 3with 11bF 3for gas form.
First chemical reaction process listed above is two-way chemical reaction.The direction of reaction can control by regulating the pressure of chemical reaction process.Such as, low pressure may cause the method for the first chemical reaction process to be reacted from " left side " to " right side ", thus produces 10bF 3o (CH 3) 2liquid and 11bF 3gas.Due to 11bF 3consist of gas form, so this composition can be with 10bF 3o (CH 3) 2fluid separation applications and be collected in order to using subsequently.
Method 10 proceeds to frame 30, wherein, and will 11bF 3gas for the synthesis of 11b 2f 6gas.In an embodiment, following chemical reaction process is used for generate 11b 2f 6gas:
2* 11bF 3+ 6*NaH=> 11b 2h 6+ 6*NaF (the second chemical reaction process)
Can collect discretely with NaF 11b 2f 6.Will 11b 2f 6being considered as comprising does not have the isotopic gas of B-10 (or rich substantially 11b gas) purification after B-11 isotope.After purification 11b 2h 6the B-11 content of the boron material in gas is greater than about 80% substantially, such as, and about 95%.In an embodiment, the B-11 content of the boron material in the boron gas after purification is 99.7 about %, means that the B-10 isotope of the boron gas after purification is less than about 0.3%.If expect the B-11 isotope of high level, then can implement additional purification process, to be rich in the B-11 content of gas further. 11b 2h 6the B-11 isotope of gas is also highly stable.Due to these characteristics, use in the semiconductor fabrication processing of following discussion 11b 2h 6gas.
Fig. 2 is using after purification in semiconductor fabrication processing according to many aspects of the present invention 11b 2h 6the flow chart of the method 50 of gas.With reference to figure 2, method 50 comprises frame 60, wherein, in substrate (being also called wafer), forms opening.In an embodiment, substrate is Semiconductor substrate, such as, doped with the silicon substrate of P-type or N-type dopant.Polytype semiconductor device can be formed in substrate.These semiconductor device can comprise field-effect transistor (FET) device or bipolar transistor.Substrate can also comprise interconnection structure, and this interconnection structure comprises multiple interconnection layers (metal level) of the metal wire of the multiple semiconductor device comprised for interconnect substrate.Electrical connection between different interconnection layer can be set up by contact/through hole.
In block 60, opening can be formed in an interconnect structure, makes opening can be filled with electric conducting material (such as, tungsten), thus forms one of contact after a while.Therefore, opening can also be called as contact hole.
Method 50 proceeds to frame 70, wherein, uses the B-11 isotope gas after purification to implement ald (ALD) technique, with partly filling contact hole.ALD technique can occur in ALD room.In an embodiment, the use of ALD technique is collected by the method 10 of Fig. 1 11b 2h 6gas is as precursor.In such embodiments, ALD technique has multiple circulation.Each circulation comprises soaking technology and nucleation technique.Soaking technology is implemented under technological temperature more than 250 degrees Celsius.During soaking technology, there is following chemical reaction process:
11b 2h 6=> 2* 11b+3*H 2(the 3rd chemical reaction process)
In other words, by purification after 11b 2h 6gas is used for the thin layer (for atomic level) depositing B-11 in the contact hole.Other products 3*H of chemical reaction process 2be gas and will overflow, or on the contrary, can not be collected.
Each circulation of ALD technique also comprises nucleation technique.To the operation pressure of about 15 holders, nucleation technique is being implemented from about 2 holders.During nucleation technique, there is following chemical reaction process:
WF 6+ 11b 2h 6=> W+3* 11bF 3+ 3*H 2(the 4th chemical reaction process)
By WF 6as another precursor.Thus, by purification after 11b 2h 6gas is used for the thin layer (atomic level) of deposits tungsten (W) in the contact hole.Because soaking technology is prior to nucleation technique, so the thin layer forming tungsten in the contact hole can comprise B-11 isotope.Other products of chemical reaction process 11bF 3and 3*H 2be gas and will overflow, or on the contrary, can not be collected.
After enforcement is repeatedly with cocycle (each circulation comprises soaking technology, is then nucleation technique), tungsten layer is formed to be partially filled contact hole.This tungsten layer comprises B-11, and B-11 stablizes.
Method 50 proceeds to frame 80, wherein, implements chemical vapor deposition (CVD) technique, to form the tungsten plug of filling contact hole.CVD technique uses the tungsten layer formed by the ALD technique of above-mentioned frame 70 as Seed Layer, to deposit more tungsten materials in the contact hole.CVD technique can implemented to the operation pressures of 400 holders from the technological temperature of about 350 degrees Celsius to about 500 degrees Celsius and from about 200 holders.CVD technique can occur in a cvd chamber.During CVD technique, there is following chemical reaction process:
WF 6+ 3*H 2=> W+6*HF (the 5th chemical reaction process)
The product 6*HF of chemical reaction process is gas and can overflows, or on the contrary, can not be collected.The product W of chemical reaction process is the tungsten block of filling contact hole, and may be called tungsten plug.Therefore, run through the whole manufacture process forming tungsten plug, do not use B-10 isotope.On the contrary, stable B-11 isotope is used for help to form tungsten plug and this B-11 isotope can be there is in the final tungsten plug formed.
And, the reason one of of two phase process (multi cycle ALD technique, then for CVD technique) for the formation of tungsten plug is, ALD technique is used for improving gap-filling properties.Technology node becomes less, and device size reduces, and contact hole also becomes less.Use conventional deposition processes, be difficult to fill so little contact hole and not leaving gap wherein.These gaps may reduce device performance or cause device defects.ALD technique at this, ALD technique is used for the base section of filling contact hole and very close to each other, this is because can form widget in point-device mode.After this, the CVD technique forming the block of tungsten plug can the remainder of filling contact hole and not leaving gap.
Fig. 3-Fig. 4 is the schematic section cross-sectional side view helping to illustrate the semiconductor device 100 of the advantage of embodiment disclosed herein.With reference to figure 3, semiconductor device 100 has the silicon substrate 110 of doping.Semiconductor device 100 comprises FET transistor device, and this FET transistor device has source/drain regions 120 and 121 and grid structure 122.Each in source/drain regions is adulterated by P-type dopant (such as, boron) or N-type dopant (such as, arsenic or phosphorus).Although not shown, each in source/drain regions 120 and 121 can comprise further: lightly doped source/drain regions and heavily doped source/drain regions.In an embodiment, semiconductor device 100 belongs to be less than the technology node of 90 nanometers (nm) or the semiconductor device of Age of Technology.Such as, semiconductor device 100 can be 65nm technology node transistor, 40nm technology node transistor, 28nm technology node transistor or 20nm technology node transistor.In certain embodiments, semiconductor device 100 can comprise: FINFET transistor or vertical transistor.
Grid structure 122 to be arranged on above substrate 110 and between source/drain regions 120 and 121.Grid structure 122 comprises: gate dielectric and the gate electrode layer be formed in above gate dielectric.In one embodiment, gate dielectric comprises: oxide material, and gate electrode layer comprises: polycrystalline silicon material.In another embodiment, gate dielectric comprises height-k dielectric material, and gate electrode layer comprises metal material.When appropriate voltage being applied to gate/drain district 120 and 121 and grid structure 122, conducting channel district 125 can be formed in a part for the substrate 110 above grid structure 122.
Next, interlayer dielectric layer 126 to be formed in above substrate 110 and above grid 122.Interlayer dielectric layer 126 is subsequently by a part for the interconnection structure (not shown) of formation.Interconnection structure has multiple interconnecting metal layer, and is provided in the electrical connection between semiconductor device 100 and external devices.Interlayer dielectric layer 126 can comprise low-k material.Opening 128 is formed in interlayer dielectric layer 126.In an embodiment, opening 128 is formed above one in source/drain regions 120 and 121.In other embodiments, opening 128 can be formed in above grid structure 122.
With reference to figure 4, in opening 128, form tungsten plug 130.As mentioned above, interconnection structure can have multiple interconnection layer.At this, tungsten plug 130 can be used for setting up the electrical connection with source/drain regions 121.Similarly, other tungsten plugs being similar to tungsten plug 130 can be formed in above grid structure 122 or other source/drain regions 120.In order to simple reason, at this, these other tungsten plugs are not shown.
Tungsten plug 130 is formed according to above method 10 and 50 described in fig. 1 and 2.In other words, do not use B-10 isotope and use stable B-11 isotope to form tungsten plug 130.In an embodiment, first chemical reaction process described in frame 20 of above composition graphs 1 is first used to generate 11bF 3gas.Next, will by the second chemical reaction process described in the frame 30 of implementing above composition graphs 1 11bF 3gas is used for generating 11b 2h 6gas. 11b 2h 6the B-11 content of gas is rich B-11, and therefore, does not substantially have B-10.In an embodiment, 11b 2h 6the B-11 content of the boron in gas is greater than about 95%, such as, is more than or equal to about 99.7%.In other words, 11b 2h 6the B-10 content of the boron in gas is less than about 5%, such as, is less than or equal to about 0.3%.After this, will be rich in B-11's in the ald process 11b 2h 6gas is used as precursor, to form tungsten Seed Layer in the contact hole.ALD technique comprises multiple immersion and nucleation technique.Tungsten Seed Layer comprises boron, and boron is rich in B-11 boron in this case.Tungsten Seed Layer does not have B-11 substantially.Then, implement CVD technique, thus basically by tungsten filling contact hole, thus form tungsten plug 130.
Thermal neutron 140 may reside in tungsten plug 130 ambient air.Thermal neutron 140 can move rapidly and can clash into tungsten plug 130, such as, and the sidewall of tungsten plug 130.If by B-10 isotope for the formation of tungsten plug, then tungsten plug should comprise B-10 isotope material.In this case, can by the B-10 isotope absorption thermal neutron 140 in tungsten plug in alpha fission process.Result to form unstable B-11 isotope.Unstable B-11 isotope can be converted into lithium (Li) and alpha particle.The nearly transistor device (such as, distance channel region 125 is less than about 0.5um) if be positioned to by tungsten plug to connect, then alpha particle may cause destruction to transistor device or electrical interference, and this can show itself to be soft error rate degradation.
According to embodiment disclosed herein, because tungsten plug 130 comprises stable B-11 isotope instead of B-10 isotope, so thermal neutron 140 can clash into tungsten plug 130 and not cause the isotopic formation of unstable B-10.Similarly, alpha fission can not be there is, and do not form alpha particle.Therefore, greatly soft error rate is improved by realizing said method.Even if tungsten plug 130 to be positioned to closely (such as, distance channel region 125 is less than about 0.5um) channel region 125 or source/drain regions 120-121, this situation also remains very.
By contrast, for the method for the traditional semiconductor fabrication of 65-nm technology node and technology node afterwards have realized that with thermal neutron 140 and the B-10 that exists in tungsten plug in conjunction with relevant issues.Such as, these conventional methods can not be recognized, only use boron the B-10 material of can not ignore quantity may be introduced in tungsten plug as precursor in the ald process.As another example, according to soft error rate, conventional method also may not recognize the impact that the B-10 material of can not ignore quantity by these in soft error rate produces.And former Age of Technology, because physical dimension is comparatively large, so can orientate the tungsten plug of formation as be enough to away from noise-sensitive semiconductor device.In addition, B-10 material is not applied in this technique.In order to these reasons above-mentioned, conventional method can not be taken measures, thus prevents from using B-10 gas to form tungsten plug.Therefore, usually there is unacceptable high soft error rate in the semiconductor device manufactured by these conventional methods, especially along with Age of Technology becomes more and more less (it causes day by day less physical dimension).
By contrast, the present invention recognizes, only uses boron will to leave the B-10 material of can not ignore quantity in tungsten plug as precursor in the ald process.The present invention also recognizes that B-10 material may have a negative impact to the semiconductor device constantly reduced.Therefore, the present invention relates to and adopt careful measure to purify boron gas, substantially there is no that B-10 is isotopic is rich in B-11 boron gas to obtain.By this way, tungsten plug 130 can be formed as substantially not having B-10, thus significantly improves soft error rate problem.
In addition, method disclosed herein can use in other manufacturing process.Such as, relevant to 40-nm technology node and technology node afterwards SiGe (SiGe) epitaxy technique may relate to the use of boron.But, the B-10 isotopes concentration relevant to SiGe technique about two orders of magnitude lower than tungsten plug.Similarly, the soft error rate caused by the B-10 isotope in SiGe epitaxy technique is not obvious compared with tungsten plug technique.But, if soft error rate needs to improve, then in order to be similar to those reasons above-mentioned, B-11 isotope instead of B-10 isotope can be used for SiGe epitaxy technique.
Although not shown, should be appreciated that, can additional treatments be implemented, thus complete the manufacture of semiconductor device 100.Such as, other parts of the interconnection structure belonging to tungsten plug 130 can be formed.The wafer comprising semiconductor device 100 can also through transpassivation, test, wafer cutting/scribing (dicing/slicing) and packaging technology.
Fig. 5 be soft error rate and the B-10 in tungsten plug be shown concentration between the chart 200 of simulation result of correlation.The Y-axle of chart 200 illustrates the percentage of emulated soft error rate.The X-axle of chart 200 illustrates technology node: N90 (90-nm node), N65 (65-nm node), N40 (40-nm node), N28 (28-nm node) and N20 (20-nm node).Bar 210-214 is shown for these technology nodes respectively.Post 210-214 represents the simulation result of the soft error rate relevant to the predetermined B-10 isotopes concentration in tungsten plug.Post 220-223 also show and is respectively used to N65, N40, N28 and N20 node.Post 220-223 represents the simulation result of the soft error rate relevant to the half of the predetermined B-10 isotopes concentration in tungsten plug.
As shown in Figure 5, for N90 technology node, the soft error rate caused by the B-10 in tungsten plug can be ignored low, makes not need to be further analyzed.For N65 technology node and node afterwards (less node), the soft error rate caused by the B-10 in tungsten plug may become too large so that can not ignore.But can find out, along with the concentration of B-10 reduces, soft error rate correspondingly reduces.The concentration of the B-10 in tungsten plug and soft error rate may have 1: 1 inversely related (inverse eorrelation).In other words, soft error rate can (directly and inversely proportional to) in direct ratio and inversely proportional with the concentration of the B-10 in tungsten plug.Therefore, by the B-10 in removing tungsten plug, the present invention will improve soft error rate significantly.
Fig. 6 is the flow chart of the method for the manufacture semiconductor device of the many aspects that method disclosed in Fig. 1 and Fig. 2 is shown.Method 300 starts from frame 310, wherein, provides substrate.Method 300 proceeds to frame 320, wherein, forms a part for interconnection structure at types of flexure.This part interconnection structure has opening.Method 300 proceeds to frame 330, wherein, obtains boron-containing gas.Boron-containing gas does not have boron-10 isotope substantially.Method 300 proceeds to frame 340, and wherein, opening is filled with electric conducting material, to form contact.Boron-containing gas is used to implement this filling.
Embodiments of the invention provide and are better than now methodical advantage.But will understand, other embodiments can provide different advantage, and do not require that all embodiments all possess specific advantages.An advantage is, due to the use of (being rich in B-11) boron gas after purification, makes it possible to tungsten stopper to become substantially do not have B-10 isotope.Thus, the soft error rate problem relevant to B-10 isotope can be prevented.Another advantage is, technique of the present invention and existing manufacturing process flow can be compatible, and therefore, do not relate to extra manufacturing cost.
A kind of broad overall form of the present invention relates to a kind of method.The method comprises provides substrate.The method is also included in types of flexure and forms contact hole.The method also comprises use and is rich in 11the boron material of B forms conductive contact piece in the contact hole.
Another kind of broad overall form of the present invention relates to a kind of method.The method comprises provides substrate.The method is included in the part that types of flexure forms interconnection structure.This part interconnection structure has opening.The method comprises: obtain and substantially do not have 10the isotopic boron-containing gas of B.The method comprises uses filled with conductive material opening, to form contact.Boron-containing gas is used to implement to fill.
Another broad overall form of the present invention relates to semiconductor device.Semiconductor device comprises substrate.Semiconductor device comprises the interconnection structure being formed in types of flexure.Semiconductor device comprises formation conductive contact piece in an interconnect structure.Conductive contact piece has the material composition comprising tungsten and boron, and wherein, boron is rich in 11the boron of B.
The foregoing describe the feature of multiple embodiment, make those skilled in the art can understand following detailed description better.Those skilled in the art should expect, they easily can use based on the present invention and design or revise the identical object reaching the embodiment introduced at this and/or other techniques and the structure that realize same advantage.Those of skill in the art also will appreciate that, these equivalent structures do not depart from the spirit and scope of the invention, and they in the case of without departing from the spirit and scope of the present invention, can make multiple change, replacement and change at this.

Claims (12)

1. form a method for semiconductor device, comprising:
Substrate is provided;
Form transistor at least partially in described substrate, described transistor has channel region;
Square one-tenth contact hole over the substrate; And
Use is rich in 11the boron material of B forms conductive contact piece in described contact hole,
Wherein, the mode being less than 0.5 micron with conductive contact piece and interval, described channel region is implemented to form described conductive contact piece,
Wherein, be rich in described in 11the boron material of B 11b content higher than 95%, and is rich in 11the boron material of B is 11b 2h 6,
Wherein, form described conductive contact piece to comprise: form tungstenic Seed Layer.
2. method according to claim 1, wherein, the mode comprising tungsten with described conductive contact piece is implemented to form described conductive contact piece.
3. method according to claim 1, wherein, forms described conductive contact piece and comprises: in described contact hole, form tungstenic Seed Layer by ald ALD technique;
Wherein, be rich in described in described ALD technique 11the boron material of B is used as precursor.
4. method according to claim 3, wherein, forms described conductive contact piece and comprises further: after described ALD technique, and implement chemical vapor deposition CVD technique, described CVD technique forms tungsten material above described tungstenic Seed Layer.
5. method according to claim 1, wherein, implements described method as the part of manufacturing process of technology node belonging to below 90-nm technology node.
6. form a method for semiconductor device, comprising:
Substrate is provided;
Transistor is formed at least in part in described substrate;
A part for square one-tenth interconnection structure over the substrate, the described part of described interconnection structure has opening;
Acquisition is rich in 11the isotopic boron-containing gas of B; And
With opening described in filled with conductive material to form contact, form described contact and comprise use described boron-containing gas enforcement filling to form tungstenic Seed Layer,
Wherein, described contact is formed as be less than 0.5 micron apart from the channel region of described transistor,
Wherein, be rich in described in 11the boron-containing gas of B 11b content higher than 95%, and is rich in 11the boron-containing gas of B is 11b 2h 6.
7. method according to claim 6, wherein, described boron-containing gas comprises 11b isotope, and wherein, described in described boron-containing gas 11the isotopic content of B is greater than 99.7%, and wherein, in described boron-containing gas 10the isotopic content of B is less than 0.3%.
8. method according to claim 6, wherein, the mode being tungsten plug with described contact is implemented to fill described opening.
9. method according to claim 6, wherein, fill described opening and comprise:
Use ald ALD technique to form Seed Layer in said opening, in described ALD technique, described boron-containing gas is used as precursor; And
Chemical vapor deposition CVD technique is used to form tungsten material above described Seed Layer.
10. a semiconductor device, comprising:
Substrate;
Be formed in the transistor in described substrate;
Interconnection structure, is formed in described types of flexure; And
Conductive contact piece, be formed in described interconnection structure, described conductive contact piece has the material composition comprising tungsten and boron, and wherein, described boron is rich in 11the boron of B,
Wherein, channel region and the described conductive contact piece interval of described transistor are less than 0.5 micron,
Wherein, be rich in described in 11the boron of B 11b content is higher than 95%.
11. semiconductor device according to claim 10, wherein, described in be rich in 11the boron of B does not have 10b isotope.
12. semiconductor device according to claim 10, wherein, described semiconductor device belongs to the device of the semiconductor technology generation being less than the 90-era of nanotechnology.
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5136355A (en) * 1987-11-25 1992-08-04 Marconi Electronic Devices Limited Interconnecting layer on a semiconductor substrate
US5395783A (en) * 1993-02-16 1995-03-07 Texas Instruments Incorporated Electronic device and process achieving a reduction in alpha particle emissions from boron-based compounds essentially free of boron-10
US5973372A (en) * 1997-12-06 1999-10-26 Omid-Zohoor; Farrokh Silicided shallow junction transistor formation and structure with high and low breakdown voltages
CN1662992A (en) * 2002-06-28 2005-08-31 前进应用科学股份有限公司 Negative differential resistance (NDR) element and memory with reduced soft error rate

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6482733B2 (en) * 2000-05-15 2002-11-19 Asm Microchemistry Oy Protective layers prior to alternating layer deposition
KR101216381B1 (en) * 2005-12-21 2012-12-28 주성엔지니어링(주) Method of forming thin film
US7560379B2 (en) * 2006-02-07 2009-07-14 Texas Instruments Incorporated Semiconductive device fabricated using a raised layer to silicide the gate
JP2011014667A (en) * 2009-07-01 2011-01-20 Panasonic Corp Semiconductor device and method of manufacturing the same

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5136355A (en) * 1987-11-25 1992-08-04 Marconi Electronic Devices Limited Interconnecting layer on a semiconductor substrate
US5395783A (en) * 1993-02-16 1995-03-07 Texas Instruments Incorporated Electronic device and process achieving a reduction in alpha particle emissions from boron-based compounds essentially free of boron-10
US5973372A (en) * 1997-12-06 1999-10-26 Omid-Zohoor; Farrokh Silicided shallow junction transistor formation and structure with high and low breakdown voltages
CN1662992A (en) * 2002-06-28 2005-08-31 前进应用科学股份有限公司 Negative differential resistance (NDR) element and memory with reduced soft error rate

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