CN102645625B - Short circuit virtual architecture, separate embedded method and device - Google Patents
Short circuit virtual architecture, separate embedded method and device Download PDFInfo
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Abstract
The invention discloses a kind of short circuit virtual test framework, separate embedded method and device.Short circuit virtual test framework comprises a ground shield, at least binary signal testing cushion and a signal transmssion line.Ground shield is positioned at a surface.Signal transmssion line is above ground shield and between binary signal testing cushion.Signal transmssion line is conductively coupled to ground shield, and the total length of signal transmssion line is less than a total length of the signal transmssion line of a correspondence and a test system of a test structure.The present invention is enable more accurate RF pattern when high frequency.
Description
Technical field
The present invention relates to a kind of test of semiconductor device, particularly relate to and a kind ofly separate embedded method and device.
Background technology
Form integrated circuit on a semiconductor substrate and comprise many active and passive blocks, such as resistor, inductor, capacitor, turn resistance device, amplifier etc.The design specification that they can present (such as resistance value, inductance value, capacitance, gain etc.) desirable physics/electric characteristics according to definition manufactures these assemblies.Although want to verify and be obedient to particular design specification and each assembly manufactured, typically, after being incorporated into circuit, respective assembly can not be tested rapidly.Therefore, " independence " that wafer manufactures indivedual IC assembly copies, the assembly manufactured with same process and same physics/electric characteristics; And hypothesis " independence " copy measured physics/electric characteristics indicate without test indivedual IC assemblies.
At test period, " independence " copies, and is called " test system " (DUT), and be electrically connected to wire head and testing cushion, it is connected to external test arrangements again.Although physics/electric characteristics should those (and indivedual IC assemblies) of Precise Representation DUT, testing cushion and wire head contribution physics/electric characteristics, be called " parasitic animal and plant (parasitics) " (such as from the resistance value of testing cushion and wire head, capacitance and inductance value), it provides the characteristic of the test of DUT.By being called that the technique of " separating embedded " can obtain parasitic animal and plant to manifest the intrinsic propesties of DUT.
Therefore, accurate embedded method of separating needs to lower parasitic animal and plant contribution and accurately describes the intrinsic characteristic of DUT (and finally, indivedual IC assembly represents).At present, wafer is separated embedded method and be called " open, short ", " open-thru ", and " thru-reflect-line " (" TRL ") has been widely used in parasitic animal and plant is described, such as, the resistance value of testing cushion and wire head, inductance value and capacitance are stemmed from high frequency (GHz grade).Such as, but separate embedded method at present and meet with some problems, short circuit is crossed and separated embedded (shortoverde-embedding), come from excessive parasitic thing contribution that is mesoporous and interconnection, and lack the embedded ability of Three-Dimensional Solution.These problems become more serious when high frequency, such as, in the frequency close to 50Ghz.Therefore, when existing solution embedded method has been be applicable to desired object, be can not fully meet each aspect.
Summary of the invention
In order to solve the problem of prior art, a first level of this disclosure comprises a short circuit virtual test framework.Short circuit virtual test framework comprises a ground shield, is positioned at a surface; At least binary signal testing cushion; One signal transmssion line, above this ground shield and between binary signal testing cushion.In an embodiment, this signal transmssion line is conductively coupled to this ground shield, and the total length of wherein this signal transmssion line is less than a total length of the signal transmssion line of a correspondence and a test system of a test structure.
Another aspect of this disclosure comprises separates embedded device.Separate embedded device and comprise a test structure, test structure comprises a test system (DUT) and is couple to a left signal pad via one first transmission line and is couple to a right signal pad via one second transmission line, and a short-circuit test framework.Short-circuit test framework comprises a ground shield, is positioned on a substrate; At least binary signal testing cushion; And one the 3rd signal transmssion line, in ground shield and between this binary signal testing cushion.3rd signal transmssion line is conductively coupled to this ground shield, and the total length of wherein the 3rd transmission line is less than the total length of this first transmission line, this test system and this second transmission line.
Another aspect of this disclosure comprises separates embedded method.Separate embedded method to comprise: form a test structure, this test structure comprises a test system (DUT) and is couple to a left signal pad by one first transmission line and is couple to a right signal pad by one second transmission line; Form multiple virtual test framework, at least one virtual test framework is a short circuit virtual test framework, this short circuit virtual test framework comprises a ground shield, at least the binary signal testing cushion on a substrate and one the 3rd signal transmssion line in ground shield and between this binary signal testing cushion, wherein the 3rd signal transmssion line is conductively coupled to this ground shield, and the total length of wherein the 3rd transmission line is less than the total length of this first transmission line, this test system and this second transmission line; Measure the transformation parameter of this test structure and this virtual test framework; And use the transformation parameter of this test structure and the plurality of virtual test framework to determine the intrinsic transformation parameter of this DUT.
The present invention is enable more accurate RF pattern when high frequency.
For making above-mentioned purpose of the present invention, feature and advantage become apparent, special embodiment below, and coordinate appended accompanying drawing, be described in detail as follows.
Accompanying drawing explanation
Fig. 1 is that a process flow diagram illustrates according to this disclosure embodiment the method that solution is embedded;
Fig. 2 A, Fig. 3 A-Fig. 3 B and Fig. 4 A-Fig. 4 B foundation Fig. 1 are for separating the vertical view of the various test structures of embedded method;
Fig. 1 is for separating the cut-open view of the various test structures of embedded method for Fig. 2 B foundation;
Fig. 5 A-Fig. 5 B is have slot form to float the sloping wave CPW transmission line covered and the three-dimensional accompanying drawing with the sloping wave CPW transmission line that slot form ground connection is covered according to disclosure of the present invention;
Fig. 6 illustrates according to another embodiment of the present invention and separates embedded method;
Fig. 7 A-Fig. 7 C is according to the vertical view of embodiments of the invention display test structure;
Fig. 8 A-Fig. 8 C is according to the vertical view of embodiments of the invention display test structure;
Fig. 9 A-Fig. 9 B shows skeleton view and the cut-open view of short virtual test framework according to embodiments of the invention;
According to embodiments of the invention, Figure 10 illustrates that display will be separated the parasitic equivalent electrical circuit of embedded test structure;
Figure 11 obtains the block scheme of the system of the intrinsic propesties of DUT according to embodiments of the invention display;
Figure 12 shows the block scheme of the workstation of the system of Figure 11 according to embodiments of the invention; And
Figure 13 shows a two-port network.
Wherein, description of reference numerals is as follows:
11,13,15,17,19 ~ step
30 ~ test system;
40 ~ test structure;
44,46,48,50 ~ testing cushion;
52,54 ~ transmission line;
55 ~ length;
56 ~ length;
58A ~ wire;
58B ~ wire;
65 ~ width;
70 ~ width;
75 ~ conductive layer;
80 ~ mesoporous;
85 ~ left half framework;
90 ~ right half framework;
95,100 ~ virtual test framework;
105 ~ left testing cushion;
110 ~ right testing cushion;
115 ~ transmission line;
125 ~ left testing cushion;
130 ~ right testing cushion;
135 ~ transmission line;
145 ~ framework;
160 ~ virtual test framework;
170 ~ right testing cushion;
175 ~ transmission line;
185,190,195 ~ section;
202,204,206,208 ~ step
300,320,350 ~ test structure;
302a, 302b, 304a, 304b, 306a, 306b ~ testing cushion;
310,311 ~ transmission line;
308,312,314,315 ~ ground wire;
301 ~ test system;
351 ~ ground shield;
352,356 ~ wire;
400,420,450 ~ test structure;
410,411 ~ signal transmssion line;
414,415 ~ ground wire;
451 ~ ground shield;
452,456 ~ wire;
550 ~ short circuit virtual test framework;
551 ~ screen layer;
552 ~ ground wire;
554 ~ signal transmssion line;
556,558 ~ mesoporous;
557 ~ conductive layer;
600 ~ equivalent electrical circuit;
602 ~ the first ports;
604 ~ the second ports;
700 ~ system;
703 ~ wafer;
704,705 ~ test structure;
706,707 ~ probe;
709 ~ automatic network analyzer;
711 ~ workstation;
715 ~ server;
802 ~ processor;
804 ~ storer;
805 ~ program;
806 ~ analyser interface;
Embodiment
Fig. 1 is that a process flow diagram illustrates according to this disclosure embodiment the method that solution is embedded.With reference to figure 1, method 11 is by step 13, and in step 13, form the test structure with test system, test system is embedded in test structure.Test structure has left and right pad and couples test system.Test structure is divided into left and right framework by test system.Left and right framework respectively has intrinsic transformation parameter.The step 15 of method 11 forms multiple virtual test framework.The each of multiple virtual test framework comprises left and right pad.The step 17 of method 11 measures the transformation parameter of test structure and virtual test framework.The step 19 of method 11 uses the intrinsic transformation parameter of left and right framework and the transformation parameter of test structure and virtual test framework to obtain the intrinsic transformation parameter of test system.
Fig. 2 to Fig. 4 is vertical view and/or the cut-open view of various test structures for separating embedded method according to Fig. 1.With reference to figure 2A, test system (DUT) 30 is embedded in test structure 40.DUT30 comprises active or passive RF (RF) device in the present embodiment.For example, DUT30 may be radio frequency integrated circuit (RFIC) device.Test structure 40 comprises testing cushion 44,46,48 and 50.Testing cushion 44 and 46 comprises signal testing pad, and testing cushion 48 and 50 comprises earthing test pad.In the present invention, testing cushion 44 and 48 (and 46 and 50) is arranged in ground-signal-ground (GSG) configuration, and ground mat 48 is close to signal pad 44.In another embodiment, test structure 40 may with other configurations of testing cushion 44 and 48 such as ground, signal (GS), ground-signal-ground-signal (GSGS), and/or any other suitable test configuration is implemented.In another embodiment, use known substrate-shield technology design and manufaction test structure 40, so reduce the potential electromagnetic field radiation leaking into semiconductor substrate (not shown).At this shield technology, test structure 40 is manufactured on substrate, and comprises substrate plane (not shown), and substrate plane uses closeer mesoporous array ground to shield silicon substrate.Implementation focus is that test structure may be regarded as separate network and can not be couple to other networks.
With reference to figure 2A, signal testing pad 44 and 46 is conductively coupled to the transmission line 52 and 54 with length 55 and 56.Transmission line 52 and 54 is also couple to DUT30.Therefore, the electrical connection between DUT30 and external device (ED) may be set up.Earthing test pad 48 is coupled mutually via wire 58 with 50, and wire 58 is that transmission line is also referred to as ground wire.Earthing test pad 48 and ground wire 58 provide electrical ground reference point to DUT30.Testing cushion 44 and 48, transmission line 52 and 54, and ground wire 58, eachly comprise conductive material, such as aluminium, copper, aluminium copper, aluminium alloy, aldary, other metals, polysilicon and/or its combination.In the present embodiment, signal testing pad 44 and 46 and earthing test pad 48 and 50 have close dimension and material.Can recognize, testing cushion 44,46,48 and 50 may be couple to external device (ED) such as tester, so may set up the electrical connection between DUT03 and external device (ED).Transmission line 52 and 54 also comprises width 65 and 70 respectively.In the present embodiment, width 65 and 70 approximates all greatly 0.4 micron (um), although width 65 and 70 may be greater than 0.4um in other embodiments.
With reference to figure 2B, the cut-open view of test structure 40 is described.Test structure 40 comprises the multiple conductive layers 75 and mesoporous 80 being couple to DUT30.Conductive layer 75 may also be (inter-level) metal layer between the stratum known, may be present in multiple semiconductor device.Conductive layer 75 and mesoporous 80 comprises conductive material, such as metal, for example, and aluminium, copper, aluminium copper, tungsten or its combination.DUT30 may be embedded in any one of the conductive layer 75 of test structure 40.In the present embodiment, in Fig. 2 A, wire 75 represents to the transmission line 52 of signal testing pad 44 to couple DUT30 from point A to point B with mesoporous 80, and conductive layer 75 and mesoporous 80 represents from a C to a F to be couple to DUT30 to the transmission line 54 of signal testing pad 46.
DUT30 has the intrinsic transformation parameter of the actual physics/electric characteristics representing DUT30.When DUT30 measures these intrinsic transformation parameters, be couple to the assembly of DUT30, signal pad 44 and 46 and the transmission line 52 and 54 of such as Fig. 2 A contribute parasitic animal and plant, comprise dead resistance, stray capacitance and stray inductance to measurement result, therefore affect the measuring accuracy of DUT30 negatively.Various " separating embedded " method is for obtaining the intrinsic transformation parameter of DUT from the measurement result of DUT30.But when test frequency increases, the parasitic contribution change being couple to the assembly of DUT30 may make greatly to separate embedded method out of true at present.For example, with reference to figure 2B, the some C of the test structure 40 of half may be had to 40% of the electrical signal path of some F by the electrical signal path of a C to some E.Be difficult to illustrate that the some C stemming from test structure contributes to the parasitic animal and plant of the electrical signal path of some E for separating embedded method at present.In other examples, (open-shout-through) mode that solution embedded method prevailing at present utilizes " open circuit short circuit is passed through ", separating an embedded aspect, DUT30 is removed by test structure 40, and extra electrical short connection (not shown) is positioned between the some B of test structure and some C.May comprising metal because electrical short connects and may comprise resistance value and inductance value, should not be that solution is embedded.But " open, short-pass " is separated embedded method and can not be considered this, and is effectively connected by the embedded electrical short of measurement result solution.Therefore, the intrinsic transformation parameter that DUT30 uses " open, short-pass " solution embedded method to obtain can not be very accurate.This phenomenon is called " short circuit is excessively separated embedded " (shortoverde-embedding), mean separate embedded period the resistance value that removes and inductance value be greater than the correct value that be removed.When high frequency, " short circuit is excessively separated embedded " problem becomes remarkable especially, for example, when frequency is more than or equal to 50GHz.When electrical short connects elongated, " short circuit is excessively separated embedded " problem also changes grain.
In order to overcome the restriction of separating embedded method at present, current embodiment utilizes multiple testing framework to obtain the intrinsic transformation parameter precise results of DUT30.One of these multiple testing frameworks is test structure 40.Split test structure 40 with reference to figure 2A, DUT30 and become left half framework 85 and right half framework 90.Left half framework 85 has parasitic animal and plant to contribute, may describe according to intrinsic transformation parameter, (being also called transmission matrix) [left _ right] may be represented with abcd matrix, and right half framework 90 has parasitic animal and plant contribution, may describe with intrinsic transformation parameter, may represent with abcd matrix [right _ left].Usually, abcd matrix can be obtained by two-port network, such as, two-port network shown in Figure 13.
Abcd matrix is according to total voltage and current definition:
V
1＝A*V
2+B*I
2
I
1＝C*V
2+D*I
2
V
1with V
2the constrained input voltage of two-port network respectively, and I
1with I
2the constrained input electric current of two-port network respectively.Therefore, A, B, C, D are the elements of the abcd matrix of two-port network, A, B, C, D characterization input voltage V
1, output voltage V
2, input current I
1with output current I
2between relation.Aforesaid equation is arranged in matrix form, and abcd matrix becomes:
Abcd matrix may also referred to as transmission matrix, or the transformation parameter of two-port network.The feature of abcd matrix is the abcd matrix of the two-port network that calculating two or more is connected in series, and the abcd matrix out of the ordinary of each network is multiple.Similarly, the abcd matrix removing the two-port network be connected in series with other two-port networks is contributed, and the inverse matrix of network is multiple.Another feature of abcd matrix can obtain by the distribution parameter (S-parameter) measuring two-port network, and mathematically conversion S-parameter measurements becomes abcd matrix (the further details discussion of abcd matrix, " MicrowaveEngineering the 2nd edition " the 206-208 page with reference to DavidM.Pozar institute works).In an embodiment, the length 55 of transmission line 52 is close to the length 56 of transmission line 54.Testing cushion 44,46,48 and 50 has about same dimension and comprises same material.Therefore, in an embodiment, left half framework 85 may be considered to and almost be symmetrical in right half framework 90.In other words, test structure 40 is symmetrical test structures.
Because signal testing pad 44 and earthing test pad 48 are positioned at the left of the DUT30 of Fig. 2, they may be called left signal testing cushion 44 and left earthing test pad 48.Similarly, signal testing pad 46 and earthing test pad 50 may be called right signal testing cushion 46 and right earthing test pad 50.Left signal testing cushion 44 may represent with abcd matrix [P_left] with the intrinsic transformation parameter (representing that parasitic animal and plant is contributed) of left earthing test pad 48, and right signal testing cushion 46 may represent with abcd matrix [P_right] with the intrinsic transformation parameter of right earthing test pad 50.Can recognize, [P_left] and [P_right] consider to pad and interconnect between current potential discontinuous.In an embodiment, because all testing cushion 44,46,48 and 50 have similar dimension and comprise approximate material, [P_left] is similar to [P_right], and [P_left] and [P_right] may be called [Pad].Can recognize that in another embodiment, [P_left] may be similar to [P_right].
Testing cushion 44,46,48 and 50 may be couple to tester, so the transformation parameter of integrated testability framework 40 may be obtained by measurement result.For example, use instrument, such as network analyzer, the characteristic of test structure 40 may arrive according to S-parameter measurement.These S-parameter measurements may be transformed into abcd matrix form, with [A '] represent.The intrinsic transformation parameter of DUT30 is called [A].Can recognize that the intrinsic transformation parameter [A] of DUT30 may obtain by the transformation parameter of the measurement of test structure of taking [A '], and remove the intrinsic transformation parameter (or ghost effect) of (or capturing) left half framework 85 and right half framework 90 by the transformation parameter measured [A '].Mathematically, can be described as:
[A]=[Left_half]
-1* [A '] * [Right_half]
-1equation 1
[Left_half]
-1with [Right_half]
-1the inverse matrix of [Left_half] and [Right_half] respectively.Because [A '] can be obtained by the measurement result of test structure 40 rapidly, only need to untie [Left_half] with [Right_half] to calculate [A], and therefore accurately solution be embedded in the DUT30 beyond test structure 40.At Fig. 2 A, left half framework 85 can be seen and comprise left testing cushion 44,48 and transmission line 52,58A and right half framework comprise right testing cushion 46,50 and transmission line 54,58B.Therefore, the transformation parameter of left half framework 85 may obtain by the transformation parameter of serial connection pad 44,48 with the transformation parameter of transmission line 52,58A, and by being connected in series the transformation parameter of pad 46,50 and transmission line 54, the transformation parameter of 58B obtains the transformation parameter of right half framework 90.Be [Thru_left] at the transmission line 52 of abcd matrix form and the transformation parameter of 58A, and be [Thru_right] at the transmission line 54 of abcd matrix form with the transformation parameter of 58B.Therefore, following equation can be obtained:
[Left_half]=[P_left] * [Thru_left] equation 2
[Right_half]=[P_right] * [Thru_right] equation 3
Therefore, equation 1 also may be write as
[A]＝[P_left]
-1*[Thru_left]
-1*[A’]*[Thru_right]
-1*[P_right]
-1
With reference to figure 3A and Fig. 3 B, virtual test framework 95 and virtual test framework 100 are described.In an embodiment, use the virtual test framework 95 in the technical design of aforesaid substrate-shielding and shop drawings 3A.Virtual test framework 95 comprises left testing cushion 105 and right testing cushion 110, is arranged in GSG configuration and together with coupling by length 120 with the transmission line of width 122.In an embodiment, length 120 is greater than 300um, for example 500um, and width 122 is about 0.4um, although in other embodiments, width 122 may be greater than 0.4um.The parasitic animal and plant contribution of transmission line 115 may describe with intrinsic transformation parameter and may represent with abcd matrix [M_1].In the present embodiment, the dimension of the testing cushion 44,46,48 and 50 of the dimension of left testing cushion 105 and right testing cushion 110 and the test structure 40 of material and Fig. 2 A and material proximate.Therefore, left testing cushion 105 is similar to [P_left] and [P_right] respectively with the transformation parameter (or parasitic animal and plant is contributed) of right testing cushion 110, (both are approximate in the present embodiment).
In an embodiment, the virtual test framework 100 of aforesaid substrate shield technology design and manufaction Fig. 3 B is used.Virtual test framework comprises left testing cushion 125 and right testing cushion 130, together with it to be coupled with the transmission line 135 of width 142 with the arrangement of GSG configuration and by length 140.In an embodiment, the length 120 approximately 500um of transmission line 115, the length 140 approximately 1000um of transmission line 135.The parasitic animal and plant contribution of transmission line 135 may describe with intrinsic transformation parameter, and represents with abcd matrix [M_21].In the present embodiment, the dimension of left testing cushion 125 and right testing cushion 130 and material proximate are in the dimension of the testing cushion 44,46,48 and 50 of the test structure 40 of Fig. 2 A and material.Therefore, left testing cushion 125 is similar to [P_left] and [P_right] respectively with the transformation parameter (or parasitic animal and plant is contributed) of right testing cushion 130.The N multiple of the length 140 of the transmission line 135 about length 120 of transmission line 115.In the present embodiment, N=2, the length 140 meaning transmission line 135 is approximately the twice of the length 120 of transmission line 115.Well known, abcd matrix may be serial connection.Therefore, the transformation parameter [M_21] of transmission line 135 approximates greatly [M_1] * [M_1].
The testing cushion 105 and 110 of virtual test framework 95 may be couple to external test facility so may measure the transformation parameter of virtual test framework 95.S-parameter may be used to perform the measurement of transformation parameter, and measurement result may convert abcd matrix form to, so can obtain the transformation parameter (abcd matrix form) of the measurement of the virtual test framework 95 being described as [TL_l1].Similarly, the transformation parameter of the virtual test device 100 of abcd matrix form may be obtained and be described as [TL_l2].Following equation can be obtained:
[TL_l1]=[P_left] * [M_1] * [P_right] (equation 4)
[TL_12]＝[P_left]*[M_2l]*[P_right]
=[P_left] * [M_l] * [M_1] * [P_right] (equation 5)
Via above-mentioned equational mathematical operation, [P_left] or [P_right] and [M_1] may describe with following equation:
[P_left] * [P_right]=[TL_l1] * [TL_l2]
-1* [TL_l1] (equation 6)
[M_1]=[P_left]
-1* [TL_l1] * [P_right]
-1(equation 7)
Because [TL_l1] and [TL_l2] are obtained by measurement result, so [P_left], [P_right] and [M_1] accurately can be calculated.In an embodiment, calculate the following result of [P_left] and [P_right]:
Wherein A, B, C and D represent the element of the abcd matrix of test structure 40.May obtain ABCD parameter by the S-parameter measuring test structure 40, and mathematically conversion three S-parameters become ABCD parameter.
As aforementioned, [P_left] represents the intrinsic transformation parameter (or parasitic animal and plant is contributed) of of left testing cushion 105,125,44 and 48.[P_right] represents the intrinsic transformation parameter (or parasitic animal and plant is contributed) of of right testing cushion 110,130,46 and 50.[M_1] represents that length of transmission line is similar to the intrinsic transformation parameter (or parasitic animal and plant contribution) of the length 120 of transmission line 115.User's formula 8 and 9, also can calculate [Thru_left] and [Thru_right].Afterwards, user's formula 2 and 3 calculates [Left_half] and [Right_half].In an embodiment, the length 55 and 56 of transmission line 52 and 54 is similar to the length 120 of transmission line 115 respectively.Therefore, [Thru_left] and [Thru_right] are similar to [M_1].Because [M_1] can be calculated by user formula 4-9, [Thru_left] and [Thru_right] also may be obtained.
In addition, the intrinsic transformation parameter of left testing cushion 105 be connected in series with transmission line 115 may be described as [TL_left] with abcd matrix pattern.Also can be multiplied by [P_right] by measuring transformation parameter [TL_l1]
-1obtain [TL_left1], because [TL_left1] represents the intrinsic transformation parameter of the framework 45 the same with not having the virtual test framework 95 of right testing cushion 110.Based on giving reasons, drawing with arrow and dotted line and presenting at virtual test framework 95 framework representing [TL_left1].Similarly, the transformation parameter [TL_left2] of the framework 150 identical with not having the virtual test framework 100 of right testing cushion 130 is represented with the intrinsic transformation parameter of the left testing cushion 125 that transmission line 135 is connected in series.Based on illustration purpose, draw with arrow and dotted line and present at virtual test framework 100 framework representing [TL_left2].Be multiplied by [P_right] by by the transformation parameter [TL_l2] measured
-1obtain [TL_left2], wherein [P_ight]
-1represent the inverse matrix of [P_right].
With reference to figure 4A, virtual test framework 160 is described.In an embodiment, use the technical design of aforesaid substrate-shielding and manufacture virtual test framework 160.Virtual test framework 160 comprises left testing cushion 165 and right testing cushion 170, together with it to be coupled with the transmission line 175 of width 182 with the arrangement of GSG configuration and by length 180.In an embodiment, width 182 is 0.4um approximately, although in other embodiments, width 182 may be greater than 0.4um.Testing cushion 165 and 170 may be couple to the measurement result that external test obtains the transformation parameter of overall virtual test framework 160.For example, may measure S-parameter and be transformed into abcd matrix [THRU], wherein [THRU] represents the transformation parameter (or parasitic animal and plant contribution) of overall virtual test framework 160.Transmission line may resolve into three section-sections 185, section 190 and section 195 in idea.In the present embodiment, the length of section 185 is similar to the length 120 of the transmission line 115 of the virtual test framework 95 of Fig. 3 A.In another embodiment, the length of section 185 is similar to the length 140 of the transmission line 135 of the virtual test framework 100 of Fig. 3 B.
With reference to figure 4A, the length of section 190 is approximately similar to the length 55 of the transmission line 52 of the test structure 40 of Fig. 2 A, and the length of section 195 is similar to the length 56 of the transmission line 54 of test structure 40.Therefore, the length 180 of transmission line 175 is similar to the sum total of length 120, length 55 and length 56.In addition, virtual test framework 160 may resolve into the following framework being illustrated in Fig. 4 B in idea: the framework 145 (not having the virtual test framework 95 of right pad 110) of Fig. 3 A, do not have a left side half framework 85 of left pad 44 and 48 and right half framework 90 of Fig. 2 A at Fig. 2 A.Mathematically, available following formula describes and decomposes:
[THRU]=[TL_left1] * [Left_half] * [P_left]
-1* [Right_half] (equation 10)
Can obtain [THRU] by fast fetching from the measurement result of virtual test framework 160, and virtual test framework 95 and 100 can be used and use mathematical operation to calculate [P_left], and [P_left] can be calculated to be [TL_l1] * [p_right]
-1or [P_left] * [M_1].Therefore, [Left_half] and [Right_half] may be untied.
Because obtain [Left_half] and [Right_half], user's formula 1, wherein [A]=[Left_half]
-1* [A '] * [Right_half]
-1, [A] (intrinsic transformation parameter of DUT30) can be untied.The intrinsic transformation parameter of the DUT30 untied represents the actual transmissions characteristic of DUT30, has nothing to do in coupling DUT30 and contributes to the pad of external device (ED) and the parasitic animal and plant of transmission line.
Use test structure 40,95,100 and 160, the summary that the sequence integration solution of following action is embedded:
1) scattering matrix of the transmission line 115 of length 120, the transmission line 135 of length 140, test structure 160 and test structure is measured.
2) scattering matrix of converting transmission length 115 and 135 and test structure 160 and 40 is respectively abcd matrix [M_1], [M_2l], [THRU] and [A].
3) calculate work and survey the abcd matrix of testing cushion 44,48 and right side testing cushion 46,50 to try to achieve [P_left] and [P_right] respectively.
4) abcd matrix of transmission line 52 and 54 is calculated to try to achieve [Thru_left] and [Thru_right] respectively.
5) the intrinsic transformation parameter of abcd matrix [A] in the hope of DUT30 is calculated.
In the present embodiment, test structure 40,95,100 is formed on same semiconductor wafer with 160.Similar technology and technique (for example, 65nmRF-CMOS technology) manufacturing test framework 40,95,100 and 160 is used in the present embodiment.Can recognize, DUT30 may be formed along with test structure and be formed.In another embodiment, different process manufacturing test framework 40,95,100 may be used from 160 and be formed at different wafers.
Can recognize, test structure 40,95,100 and 160 may have three-dimensional architecture.In certain embodiments, parasitic animal and plant composition such as needs separate embedded transmission line and/or pad the stratum that may can not be positioned at same plane.For example, illustrated by Fig. 2 B, extended along X-axis to the transmission of some F by a D, and not only extended along X-axis by a C to the mesoporous and metal level of some D and extend along Y-axis.Because also there is width (cannot be observed by Fig. 2 B but can be observed by Fig. 2 A) by the transmission line of a D to some F, be two dimensional character by the transmission line of a D to some F.Because comprising extra dimension (Y-axis) by a C to a transmission line of F (transmission line 54), transmission line 54 is three-dimensional features.Tradition is separated embedded method and is difficult to separate embedded three-dimensional feature, the transmission line 54 that such as Fig. 2 B shows, but said method and framework can be used to overcome such difficulty.
In certain embodiments, co-plane waveguide (CPW) is used in the various transmission lines of test structure 40,95,100 and 160.As aforementioned, semiconductor device may comprise metal layer between multiple stratum.These CPW features may put any one deck as metal layer between stratum.Measure the layout error hiding between the direct parasitic animal and plant that perform the measurement preventing the embedded virtual architecture of special solution (such as test structure 40) in CPW feature of (such as S-parameter) possibility.This technology allows more accurate transmission line model.For example, Table I, lists the transmission line of several spendable different shape.
Table I
Be do not have shielded co-plane waveguide transmission line at the CPW of table 1, FSCPW1-FSCPW3 is the transmission line with slot form floating shield, and GSCPW1-GSCPW3 has the earth-shielded transmission line of slot form.With reference to figure 5A and Fig. 5 B, the slow wave CPW transmission line with slot form floating shield and the stereographic map with slot form earth-shielded slow wave CPW transmission line are described.At Fig. 5 A, may with to be periodically positioned on CPW framework or under the design of slot form floating shield there is the slow wave CPW transmission line of slot form floating shield, and slot form floating shield is reversed and navigates to CPW framework.In one embodiment, for all transmission lines of Table I, CPW framework is formed in the 8th layer of metal level (M8), and the shielding of slot form is based upon the 7th (M7) or second (M2) metal level.The CPW part of framework has the signal/ground wire width of 10/um/10um, has 20um interval between signal and ground wire.Shielding of reaching the standard grade has static line length (SL) and the 2um fixed length interval (SS) of 2um, and shielding of rolling off the production line has variable SL and variable SS.SL may be designed to be minimum length to reach the high-performance having and minimize eddy current losses.At the 0.1um that the minimum length of M7 and M2 is 65nmCMOS technology.Lower slot form floating shield is 0.1um with following space compartmentalized design (1) at the SL of M7, and adjoint SS is 0.1um or 0.9um, and (2) are 0.1um and adjoint SS is that 0.1um.um. is at Fig. 5 B at the SL of M2, for ground connection slow wave CPW transmission line, to be similar to the above-mentioned architecture design with the slow wave CPW transmission line of floating shield, but the shielding of slot form is connected to ground connection.In one embodiment, above-mentioned all test structures have the length of same 500um and the width of 80um.
With reference to figure 6, the method for separating embedded 200 is described according to the embodiment disclosed.Method 200, by step 202, in step 202, forms test structure, and the test structure comprising device being tested (DUT) is couple to left signal pad by the first transmission, and is couple to right line signal pad by the second transmission line.
In step 204, form multiple virtual test framework, at least one virtual test framework is short virtual test framework.Form short virtual test framework to comprise ground shield in surface, at least binary signal testing cushion, and the 3rd signal transmssion line to be arranged at above ground shield and between binary signal testing cushion.3rd signal transmssion line is conductively coupled to ground shield, and total length is less than the total length of the first transmission line, DUT and the second transmission line.
According to the embodiment disclosed, 3rd signal transmssion line may be formed at above ground shield, 3rd signal transmssion line may be formed into the total length of the pattern length of about first transmission line and the second transmission line, and/or the 3rd signal transmssion line may be formed as comprising multiple mesoporous and multiple conductive layer, wherein the 3rd signal transmssion line is mesoporously conductively coupled to ground shield by least one.
In step 206, measure test structure and comprise the transformation parameter of virtual test framework of short virtual test framework.Method also comprises the intrinsic transformation parameter using the transformation parameter of test structure and multiple virtual test framework to determine DUT.According to the various embodiments of this disclosure, embedding technique in open, short solution, open, short-separate the intrinsic transformation parameter of the useful short virtual test framework decision DUT of this disclosures of embedded combine with technique through embedding technique in separating or various other may be used.In various solution, embedding technique is described in U.S. patent application case US12/037333, and above-mentioned listed references entirety all quotes the disclosure as this instructions.
With reference to figure 7A to Fig. 7 C and Fig. 8 A to Fig. 8 C, the vertical view of the test structure 300,320,350 and 400,420,450 of various correspondence is described according to the embodiment of this disclosure.With reference to figure 9A and Fig. 9 B, skeleton view and the cut-open view of short virtual test framework is described according to the embodiment disclosed respectively.In an embodiment, these test structures may be used for the solution embedded method of Fig. 6.
Fig. 7 A and Fig. 8 A illustrates the vertical view of test structure 300 and 400 respectively, and test system 301 and 401 is embedded in test structure respectively.Test structure 300 and 400 may be similar to the test structure 400 of Fig. 2 A-Fig. 2 B, and may comprise the like with similar functions.In an embodiment, DUTs301 and 401 may comprise active or passive RF (RF) device.For example, DUT may be radio frequency integrated circuit (RFIC) device.
Proving installation 300 and 400 comprises tests electric 302a and 302b, 304 and 304b, and 306a and 306b.Testing cushion 304a, 304b comprise signal testing pad, and testing cushion 302a, 302b and 306a, 306b comprise earthing test pad.In the present embodiment, testing cushion 302a, 304a, 306a and 302b, 304b and 306b are arranged in ground-signal-ground (GSG) configuration respectively, wherein earthing test pad 302a, 302b and 306a, 306b approach signal testing cushion 304a, 304b.In another embodiment, test structure 300 and 400 may be implemented with other configurations of testing cushion, such as ground, signal (G-S), ground-signal-ground-signal-ground (GSGSG) and/or other test configurations be applicable to.
At Fig. 7 A, signal testing pad 304a and 304b is conductively coupled to transmission line 310 and 311 respectively.Transmission line 310 and 311 is also couple to DUT30.Therefore, the electrical connection between DUT301 and external device (ED) may be set up.Transmission line 310,311 may also become signal transmssion line or signal pins.Earthing test pad 302a and 302b and earthing test pad 306a and 306b couples mutually via wire 308 and 312, and transmission line also may be called ground wire or grounding leg.Earthing test pad 302a, 302b and 306a, 306b and ground wire 308,312,314,315 provide the reference point electrical ground of DUT301.Testing cushion 302a-306a and 302b-306b, transmission line 310 and 311 and ground wire 308,312,314 and 315 comprise conductive material, such as aluminium, copper, Al-zn-mg-cu alloy, aluminium alloy, aldary, other metals, polysilicon and/or its combination.In an embodiment, signal testing pad and earthing test pad may have approximate dimension and material.Can recognize that testing cushion 302a-306a and 302b-306b may be couple to external device (ED), such as tester, be electrically connected so may set up between DUT301 with external port device.Transmission line 10 and 311 may comprise part 310a, 310b and 311a, 311b respectively, and part 310a, 311a are adjacent to signal testing electricity 304a, 304b, and the adjacent DUT301 of part 310b, 311b.In an embodiment, part 310a and 311a may be greater than part 310b and 311b by width.
Similarly, at Fig. 8 A, signal testing pad 304a and 304b is conductively coupled to transmission line 410 and 411 respectively.Transmission line 410 and 411 is also couple to DUT30.Therefore, the electrical connection between DUT401 and external device (ED) may be set up.Transmission line 410,411 may also become signal transmssion line or signal pins.Earthing test pad 302a and 302b and earthing test pad 306a and 306b couples mutually via wire 308 and 312, and transmission line also may be called ground wire or grounding leg.Earthing test pad 302a, 302b and 306a, 306b and ground wire 308,312,414,415 provide the reference point electrical ground of DUT401.Testing cushion 302a-306a and 302b-306b, transmission line 410 and 411 and ground wire 308,312,414 and 415 comprise conductive material, such as aluminium, copper, Al-zn-mg-cu alloy, aluminium alloy, aldary, other metals, polysilicon and/or its combination.In an embodiment, signal testing pad and earthing test pad may have approximate dimension and material.Can recognize that testing cushion 302a-306a and 302b-306b may be couple to external device (ED), such as tester, be electrically connected so may set up between DUT401 with external port device.Transmission line 410 and 411 may comprise part 410a, 410b and 411a, 411b respectively, and part 410a, 411a are adjacent to signal testing electricity 304a, 304b, and the adjacent DUT401 of part 410b, 411b.In an embodiment, part 410a and 411a may be greater than part 410b and 411b by width.
Except the DUT geometry that is couple to the corresponding transmission line of the signal testing pad of DUT and length, test structure 300 and 400 is similar.In the present embodiment, relative y direction, at the DUT301 in x direction longer (Fig. 7 A), and relative x direction, at the DUT401 in y direction longer (Fig. 8 A).Therefore, according to embodiment, the length of transmission line 410,411 is greater than the length of transmission line 310,311.At Fig. 7 A and Fig. 8 A, transmission line 310 and 410 is between plane A and B, and DUT301 and 401 is between plane B and C, and transmission line 411 and 411 is between plane C and F.In these two cases, use conventional short-circuit virtual test framework may occur to separate embedded mistake in x direction or y direction.
DUT301 and 401 has the intrinsic transformation parameter of the actual physics/electric characteristics representing DUT.When DUT301 or 401 measures these intrinsic transformation parameters, be couple to the assembly of DUT301 or 401, such as signal testing pad (such as 302a-306a and 302b-306b) and transmission line (such as 310,311 and 410,411) contribute the parasitic animal and plant comprising dead resistance, stray capacitance and stray inductance to measurement result, therefore affect the degree of accuracy of the measurement of DUT negatively.Therefore, various " separating embedded " method is for being captured the intrinsic transformation parameter of DUT by DUT measurement result.But when test frequency increases, the parasitic animal and plant contribution being couple to the assembly of DUT becomes large, may make solution for the current embedded method out of true.For example, solution for the current embedded method prevailing utilizes " open, short-through " mode, separating an embedded aspect, DUT is removed by test structure, and extra electrical short connection is positioned between the plane B of test structure and plane C.Because electrical short connects and may comprise metal and may comprise resistance and inductance, should be unable to be embedded by solution.But " open, short-pass " is separated embedded method and can not be considered this and effectively separate the embedded electrical short from measurement result to connect.Therefore, the intrinsic transformation parameter using " open, short-pass " solution embedded method to obtain DUT is more coarse.This phenomenon is called " short circuit is excessively separated embedded ", mean separate embedded period the resistance value that removes and inductance value higher than the correct value that should be removed.When high frequency, " short circuit is excessively separated embedded " problem becomes remarkable especially, for example, when frequency equals to be greater than 50GHz.When electrical short connect become longer time ", separate embedded short circuit " problem also becomes worse.
In order to overcome the restriction of type solution embedded method, the present embodiment use the multiple testing framework comprising favourable short circuit virtual test framework obtain DUT301,401 the precise results of intrinsic transformation parameter.These multiple testing frameworks may comprise following or above-mentioned test structure 300,320,350,400,420,450 and 500.
Fig. 7 B illustrates the corresponding open circuit virtual test framework 320 with the test structure 300 of DUT301, and Fig. 8 B illustrates the corresponding open circuit virtual test framework 420 with the test structure 400 of DUT401.Open circuit virtual test framework 320 and 420 comprises and earthing test pad, signal testing pad and ground wire like the similar framework and similar functions and so on of above-mentioned associated diagram 7A and Fig. 8 A.But DUT301 and 401 is removed the gap that formed between the transmission line of 310,311 and 410,411 respectively by virtual test framework 320 and 420 of opening a way, whereby, the open circuit signaling transmission line comprising line 310 and 311 is formed.
Fig. 7 C and Fig. 8 C illustrate the vertical view of the effective short virtual test framework 350 and 450 of corresponding test structure 300 and 400 according to the every aspect of this disclosure.Fig. 9 A and Fig. 9 B illustrate skeleton view and the cut-open view of the short circuit virtual test framework 550 of corresponding test structure 300 or 400.
Short circuit virtual test framework 350,405,550 is included in the ground shield 351,451,551 of surface.The short circuit virtual test framework 350 of Fig. 7 C also comprises at least binary signal testing cushion 304a, 304b and at ground shield 350 and the signal transmssion line between binary signal testing cushion 304a, 304b 354.The short circuit virtual test framework 450 of Fig. 8 c also comprises at least binary signal testing cushion 304a, 304b and the signal transmssion line above ground shield 451 and between binary signal testing cushion 304a, 304b 454, and wherein signal transmssion line is conductively coupled to ground shield 451.The short circuit virtual test framework 550 of Fig. 9 A-Fig. 9 B also comprises at least binary signal testing cushion 304a, 304b and the signal transmssion line above ground shield 551 and between binary signal testing cushion 304a, 304b 554, and wherein signal transmssion line 554 is conductively coupled to ground shield 551.
According to various aspect of the present invention, ground shield 351,451,551 may comprise metal such as aluminium or copper and may have various width and thickness.According to an embodiment, ground shield 351,451,551 is positioned under the entire length of signal transmssion line and ground wire.In other words, according to the various aspects of this disclosure, signal transmssion line 354,454,554 may be arranged at above ground shield 351,451,551 respectively.Advantageously, in one embodiment, such substrate-shield technology design and manufaction short circuit virtual test framework 350,450,550 is used, so reduce the potential electromagnetic field radiation leaking into semiconductor substrate (not shown).By substrate shield technology, short circuit virtual test framework 350,450,550 is manufactured on substrate, and comprises the bottom metal plane being grounding to shielding silicon substrate.The feature implemented is that test structure 350,450,550 may be thought separate network and need not be couple to other networks.In addition, because by ground shield shielding board, do not have substrate network to be increased to and separate embedded equivalent electrical circuit, simultaneously simple equivalent circuit and solution embedded method.
In addition, as shown in Fig. 7 A, Fig. 7 C and Fig. 8 A, Fig. 8 C and Fig. 9 A, Fig. 9 B, according to the embodiment disclosed, each total length of the signal transmssion line 354,454,554 of short virtual test framework 350,450,550 is less than the total length of the test system (DUT) of respective signal transmission line and test structure.For example, the length of the signal transmssion line 354 between plane A and the F of short circuit virtual test framework 350 is less than the total length of the DUT301 between plane A and the F of transmission line 310,311 and test structure 300 (Fig. 7 A, Fig. 7 C).Similarly, the length of the signal transmssion line 454 between plane A and the F of short circuit virtual test framework is less than the total length of the DUT401 between plane A and the F of transmission line 410,411 and test structure 400 (Fig. 8 A, Fig. 8 C).
In addition, as shown in Fig. 7 A, Fig. 7 C and Fig. 8 A, Fig. 8 C and Fig. 9 A, Fig. 9 B, according to the embodiment disclosed, the total length of the signal transmssion line 354,454,554 of short circuit virtual test framework 350,450,550 is approximately the first transmission line of test system (DUT) and the pattern length of the second transmission line that couple test structure.For example, the plane A of short circuit virtual test framework 350 and the length of plane F transmission line 354 are approximately the pattern lengths of transmission line 310 between plane A and the B of test structure (Fig. 7 A, Fig. 7 C) and the transmission line 311 between plane C and F.In an embodiment, transmission line 354 may comprise part 310a, 310b, 311a and the 311b of above-mentioned associated diagram 7A.Similarly, the length of the Signal transmissions length 454 between plane A and the F of short circuit virtual test framework 450 is approximately the pattern length of transmission line 410 between plane A and the B of test structure (Fig. 8 A, Fig. 8 C) and the transmission line 411 between plane C and F (also namely not having DUT401).In an embodiment, transmission line may comprise part 410a, 410b, 411a and the 411b of above-mentioned associated diagram 8A.
Be similar to described in above-mentioned previous test structure, short circuit virtual test framework 350,450,550 eachly comprises testing cushion 302a and 302b, 304a and 304, and 306a and 306b.Testing cushion 304a, 304b comprise signal testing pad, and testing cushion 302a, 302b and 306a, 306b comprise earthing test pad.In the present embodiment, testing cushion 302a, 304a, 306a and 302b, 304b and 306b are arranged in ground-signal-ground (GSG) configuration respectively, wherein earthing test pad 302a, 302b and 306a, 306b approach signal testing cushion 304a, 304b.In another embodiment, test structure 350,450,550 may be implemented with other configurations of testing cushion, such as ground, signal (GS), ground-signal-ground-signal-ground (GSGSG), and/or any test configuration suitably.
At Fig. 7 C, signal testing pad 304a and 304b is via transmission limit 354 electric property coupling mutually.Earthing test pad 302a and 302b and earthing test pad 306a and 306b couples mutually via the wire 352 and 356 being also transmission line respectively, and may be called ground wire.Earthing test pad 302a, 302b and 306a, 306b and ground wire 352,356 provide pad property ground connection reference point.Testing cushion 302a-306a and 302b-306b, transmission line 354 and ground wire 352,356 all may comprise conductive material, such as aluminium, copper, aluminium copper, aluminium alloy, aldary, other metals, polysilicon and/or its combination.In the present embodiment, signal testing pad and earthing test pad may have similar dimension and material.Can recognize that testing cushion 302a-306a and 302b-306b may be couple to external device (ED), such as tester, so the measurement of short circuit virtual test framework 350 may be determined.
Similarly, at Fig. 8 C, signal testing pad 304a and 304b is via transmission limit 454 electric property coupling mutually.Earthing test pad 302a and 302b and earthing test pad 306a and 306b couples mutually via the wire 452 and 456 being also transmission line respectively, and can be described as ground wire.Earthing test pad 302a, 302b and 306a, 306b and ground wire 452,456 provide pad property ground connection reference point.Testing cushion 302a-306a and 302b-306b, transmission line 454 and ground wire 452,456 all may comprise conductive material, such as aluminium, copper, aluminium copper, aluminium alloy, aldary, other metals, polysilicon and/or its combination.In the present embodiment, signal testing pad and earthing test pad may have similar dimension and material.Can recognize that testing cushion 302a-306a and 302b-306b may be couple to external device (ED), such as tester, so the measurement of short circuit virtual test framework 450 may be determined.
Similarly, at Fig. 9 A-Fig. 9 B, signal testing pad 304a and 304b via transmission limit 554 mutually electric property coupling.Earthing test pad 302a and 302b and earthing test pad 306a and 306b couples mutually via the wire (such as line 452) and 456 being also transmission line respectively, and may be called ground wire or grounding leg.Earthing test pad 302a, 302b and 306a, 306b and ground wire (such as line) 552 provide electrical ground reference point.Testing cushion 302a-306a and 302b-306b, transmission line 554 and ground wire (such as line 552) all may comprise conductive material, such as aluminium, copper, aluminium copper, aluminium alloy, aldary, other metals, polysilicon and/or its combination.In the present embodiment, signal testing pad and earthing test pad may have similar dimension and material.Can recognize that testing cushion 302a-306a and 302b-306b may be couple to external device (ED), such as tester, so the measurement of short circuit virtual test framework 550 may be determined.
Illustrate further at Fig. 9 A-Fig. 9 B, the signal transmssion line 554 of short circuit virtual test framework comprises multiple mesoporous 556 and 558, and the multiple conductive layers 554 (comprising conductive layer 554a, 554b, 554c) and 557 above screen layer 551, all elements are all above substrate 500.Conductive layer may be (inter-level) metal layer between the well known stratum that there is multiple semiconductor device.In one embodiment, conductive layer and mesoporously comprise conductive material, such as metal, for example, aluminium, copper, aluminium copper, tungsten or its combination.In one embodiment, conductive layer 554b is conductively coupled to ground shield 551 by least one mesoporous 558, whereby via conductive layer 557 with mesoporous 556 electric property coupling conductive layer 554a, 554c to ground shield 551.Conductive layer 554 and 557 may have various width and thickness.Although three metal levels 557 are shown in Fig. 9 B, signal transmssion line 554 is not limited to such number, and may more or less metal level 557 (and correspondence is mesoporous).In other words, the conductive layer of various stratum may comprise signal transmssion line 554.
According to the embodiment disclosed, ground wire (such as 552) and earthing test pad 302a, 302b and 306a, 306b comprise by the mesoporous multiple metal levels coupled.One of multiple metal level may be included in the upper metal level on intermediate metal layer.According to another aspect disclosed, the bottom metal layer of ground wire and/or earthing test pad may be conductively coupled to ground shield 551.
In one embodiment, substrate 500 is semiconductor substrates, and may comprise silicon, maybe may comprise SiGe, gallium arsenide or other suitable semiconductor materials.Substrate also may comprise the active region and other features that mix, such as buried regions and/or epitaxial loayer (epitaxylayer).In addition, substrate may be that insulation covers semiconductor, such as silicon-on-insulator (SOI).In other embodiments, semiconductor substrate may comprise the epitaxial loayer, gradient (gradient) semiconductor layer that mix and/or also may comprise semiconductor layer and covers other semiconductor layers of different shape, and germanium-silicon layer such as, cover silicon.In other embodiments, composite semiconductor substrate may comprise multilayer silicon framework or a silicon substrate may comprise MULTILAYER COMPOSITE semiconductor framework.Active region configuration may become NMOS device (such as nFET) or PMOS device (such as pFET).Formed during semiconductor substrate may be included in previous process steps or may afterwards processing step formed underlying layer, device, knot and other feature (not shown)s.
Although do not show, in example, dielectric layer, such as oxide layer may be deposited on transmission line conductive layer, mesoporous between and/or between substrate and ground shield 551.
In an embodiment, test structure 300,320,350,400,4720,450 and/or 550 is formed at same semiconductor wafer.Also similar technology and technique (for example, 65nmRF-CMOS technology) manufacturing test framework may be used.Can recognize, DUT may be formed along with the formation of test structure.In another embodiment, different process manufacturing test framework may be used and/or be formed at different chips.
Advantageously, the unnecessary metal wire in x or the y direction of traditional short circuit virtual test framework is removed, and the transmission line retained is combined with the length of transmission line reducing signal and ground wire, the excessive solution that the short circuit virtual test framework that formation has the improvement of ground shield on substrate is whereby reduced in x and/or y direction with essence Shangdi is embedded.
With reference to Figure 10, according to the embodiment disclosed, equivalent electrical circuit 600 shows the ghost effect of test structure (such as test structure 300,400) with embedded by solution.Y
1, Y
2with Y
3between the pad representing the first port 602 (such as input port) respectively and grounded shield, between the pad of the second port 604 (such as output port) and grounded shield, and the coupling capacitance C between the first port and the second port
1, C
2with C
3.Y
4, Y
5with Y
6represent between left signal pin (such as signal transmssion line 310,410) and grounded shield, between the pad of right signal pin (such as signal transmssion line 311,411) and grounded shield respectively, and the coupling capacitance C between left signal pin and right signal pin
4, C
5with C
6.Z
1with Z
2represent the left signal pin from the first port 602 and the second port 604 and right signal pin series impedance, and Z
3represent the series impedance being connected to the grounding leg of ground connection.
According to embodiment, electric capacity (C
n) open circuit virtual measurement and the area ratio (A of pad can be taken from
x/ A
y+ A
z)) and connect, and resistance (R
n) and inductance (L
n) open circuit and the matrix manipulation of short circuit virtual measurement may be taken from, utilize example equation shown below.[Y
o] and [Y
s] represent open circuit virtual test framework and the Y parameter of short circuit virtual test framework respectively.
C
1+C
4＝(1/ω)imag(Y
110+Y
120)
C
2+C
5＝(1/ω)imag(Y
220+Y
120)
C
1＝(C
1+C
4)*A
1/(A
1+A
4)
C
4＝(C
1+C
4)*A
4/(A
1+A
4)
C
2＝(C
2+C
5)*A
2/(A
2+A
5)
C
4＝(C
2+C
5)*A
5/(A
2+A
5)
C
3＝C
6＝0.5*(-1/ω)imag(Y
120)
R
1＝real(Z
11SO-Z
12SO)
L
1＝(1/ω)imag(Z
11SO-Z
12SO)
R
2＝real(Z
22SO-Z
12SO)
L
2＝(1/ω)image(Z
22SO-Z
12SO)
R
3＝real(Z
12SO)
L
3＝(1/ω)image(Z
12SO)
With reference to Figure 11, according to the embodiment disclosed, block scheme description obtains the system 700 of the inherent characteristic of DUT.DUT is positioned at the test structure 705 of the substrate being manufactured in wafer 703.Test structure 704 (such as short circuit Virtual test equipment) is also positioned on wafer 703.Probe 706 and 707 is for obtaining S parameter data by framework 704 and framework 705.Probe operation becomes to be couple to the automatic network analyzer 709 of correction.By the software control network analyser 709 of workstation 711.Software may be downloaded by the Storage Media (such as hard disk) of the server 715 of workstation 711.In other embodiments, software may be positioned at the hard disk of personal computer system or be downloaded by removable media (such as CD-Rom).Workstation 711 executive software removes control analysis instrument 709, performs one or more method described here whereby.
Figure 12 illustrates the block scheme of workstation 711 according to the embodiment disclosed.Workstation 711 comprises processor 802, storer 804 and analyser interface 806.Processor 802 can access memory 804.In addition, analyser interface 806 is connected to processor 802.
Processor 802 can be microprocessor, controller or other can perform the processor of a series of instruction.Storer is computer fetch medium, such as random access memory (RAM), nonvolatile memory, such as flash memory or hard disk and analog thereof.Storer 804 storage comprises the instruction of one group of Operation Processor 802 to implement one or more method disclosed here.For example, program 805 possible operation processor 802 control analysis instrument interface 806 and may be used for storing data, comprises test result.By analyser interface 806, processor 802 control analysis instrument 709 (Figure 11) determines the inherent characteristic of test system, as described in.Inherent characteristic can be stored in storer 804.The cognizable system to other forms be can be used for other embodiments to perform one or more method described here.
The method and apparatus that this disclosure provides various useful solution embedded.The wider form of this disclosure comprises short circuit virtual test framework.Short circuit virtual test framework comprises ground shield, at least the binary signal testing cushion of surface and the signal transmssion line above ground shield and between binary signal testing cushion, and wherein signal transmssion line is conductively coupled to ground shield.In an embodiment, the length of signal transmssion line is less than the total length of the test system of corresponding signal transmssion line and proving installation.
Another form of this disclosure comprises separates embedded device, separate embedded device and comprise test structure, test structure comprises and couples left signal pad by the first transmission line and be couple to the test system (DUT) of right signal pad by the second transmission line, and short circuit virtual test framework.Short circuit virtual test framework is included in ground shield, at least the binary signal testing cushion of surface and the 3rd signal transmssion line between ground shield and binary signal testing cushion.3rd signal transmssion line is conductively coupled to ground shield and total length is less than the total length of the first transmission line, DUT and the second transmission line.
Another generalized form of this disclosure comprises separates embedded method, separate embedded method and comprise formation test structure, test structure comprises and couples left signal pad by the first transmission line and be couple to the test system (DUT) of right signal pad by the second transmission line, and forms multiple virtual test framework.At least one virtual test framework is short circuit virtual test framework, short circuit virtual test framework is included in ground shield, at least the binary signal testing cushion of surface and the 3rd signal transmssion line between ground shield and binary signal testing cushion, and wherein the 3rd signal transmssion line is conductively coupled to ground shield and total length is less than the total length of the first transmission line, DUT and the second transmission line.Method also comprises the transformation parameter of the virtual test framework measured test structure and comprise short circuit virtual test framework, and uses test structure to determine the intrinsic transformation parameter of DUT with the transformation parameter of the multiple virtual test frameworks comprising short circuit virtual test framework.
Advantageously, the unnecessary metal wire in x or the y direction of traditional short circuit virtual test framework is removed, and the transmission line retained is combined with the length of transmission line reducing signal and ground wire, the excessive solution that the short circuit virtual test framework that formation has the improvement of ground shield on substrate is whereby reduced in x and/or y direction with essence Shangdi is embedded.This disclosure also provides the accurate device feature of enhancing and does not need additional virtual test structure.Therefore, the mistake that this disclosure solves x and y direction simultaneously separate embedded phenomenon, complicated substrate effect and dingus solution embedded uncertainty and the complexity of separating embedded program need not be increased, whereby again high frequency time enable more accurate RF pattern.
Although the present invention discloses as above with preferred embodiment; so itself and be not used to limit the present invention; any those of ordinary skill in the art; without departing from the spirit and scope of the present invention; when doing a little change and retouching, the scope that therefore protection scope of the present invention ought define depending on appended claim is as the criterion.
Claims (12)
1. a short circuit virtual test framework, comprising:
One ground shield, is positioned at a surface;
At least binary signal testing cushion;
One test system, is coupled to this at least binary signal testing cushion by one first transmission line and one second transmission line; And
One signal transmssion line, above this ground shield and between binary signal testing cushion, wherein this signal transmssion line is conductively coupled to this ground shield;
Wherein this signal transmssion line comprises at least two upper layer signal wires and a lower layer signal wire;
Wherein this lower layer signal wire is electrically coupled to this ground shield;
Wherein this lower layer signal wire is between this at least two upper layer signal wire;
Wherein this lower layer signal wire is parallel with this at least two upper layer signal wire, and not with this at least two upper layer signal wire conllinear; And
Wherein the total length of this signal transmssion line is less than a total length of this test system, this first transmission line and this second transmission line.
2. short circuit virtual test framework as claimed in claim 1, wherein a total length of this signal transmssion line equals a pattern length of this first transmission line and this second transmission line.
3. short circuit virtual test framework as claimed in claim 1, wherein this signal transmssion line comprises multiple mesoporous between the conductive layer of multiple vertical stacking; Wherein this signal transmssion line is mesoporously conductively coupled to ground shield via at least one.
4. short circuit virtual test framework as claimed in claim 1, also comprise: multiple ground wire this signal transmssion line parallel, each ground wire to be arranged between two earthing test pads and to be conductively coupled to this ground shield, and wherein this signal testing pad and this earthing test pad are ground-signal-ground configurations.
5. separate an embedded device, comprising:
One test structure, this test structure comprises a test system and is couple to a left signal pad via one first transmission line and is couple to a right signal pad via one second transmission line;
One short circuit virtual test framework, comprising:
One ground shield, is positioned on a substrate;
At least binary signal testing cushion; And
One the 3rd signal transmssion line, in ground shield and between this binary signal testing cushion, wherein the 3rd signal transmssion line comprises at least two upper layer signal wires and a lower layer signal wire;
Wherein this lower layer signal wire is electrically coupled to this ground shield;
Wherein this lower layer signal wire is between this at least two upper layer signal wire;
Wherein this lower layer signal wire is parallel with this at least two upper layer signal wire, and not with this at least two upper layer signal wire conllinear; And
Wherein the total length of the 3rd signal transmssion line is less than the total length of this first transmission line, this test system and this second transmission line.
6. separate embedded device as claimed in claim 5, wherein a total length of the 3rd signal transmssion line is a pattern length of this first transmission line and this second transmission line.
7. separate embedded device as claimed in claim 5, wherein the 3rd signal transmssion line comprises multiple mesoporous and multiple conductive layer; Wherein the 3rd signal transmssion line is mesoporously conductively coupled to this ground shield via at least one.
8. separate embedded device as claimed in claim 5, wherein this test structure and this short circuit virtual test framework comprise multiple ground wire this first transmission line parallel, this second transmission line and the 3rd signal transmssion line, each ground wire is arranged between two earthing test pads, and wherein in this test structure and this short circuit virtual test framework, this left signal pad, right signal pad and this earthing test pad are ground-signal-ground configurations.
9. separate an embedded method, comprising:
Form a test structure, this test structure comprises a test system and is couple to a left signal pad by one first transmission line and is couple to a right signal pad by one second transmission line, wherein this test system and DUT;
Form multiple virtual test framework, at least one virtual test framework is a short circuit virtual test framework, this short circuit virtual test framework comprises a ground shield, at least the binary signal testing cushion on a substrate and one the 3rd signal transmssion line in ground shield and between this binary signal testing cushion, and wherein the 3rd signal transmssion line comprises at least two upper layer signal wires and a lower layer signal wire;
Wherein this lower layer signal wire is electrically coupled to this ground shield;
Wherein this lower layer signal wire is between this at least two upper layer signal wire;
Wherein this lower layer signal wire is parallel with this at least two upper layer signal wire, and not with this at least two upper layer signal wire conllinear; And
Wherein the total length of the 3rd signal transmssion line is less than the total length of this first transmission line, this test system and this second transmission line;
Measure the transformation parameter of this test structure and the plurality of virtual test framework; And
The transformation parameter of this test structure and the plurality of virtual test framework is used to determine the intrinsic transformation parameter of this DUT.
10. the method that solution as claimed in claim 9 is embedded, wherein a total length of the 3rd signal transmssion line is a pattern length of this first transmission line and this second transmission line.
11. as claimed in claim 9 separate embedded methods, and wherein the 3rd signal transmssion line comprises multiple mesoporous and multiple conductive layer, and wherein the 3rd signal transmssion line is mesoporously conductively coupled to this ground shield by least one.
12. as claimed in claim 9 separate embedded methods, wherein to use in an open, short solution embedding technique or an open, short-pass through embedding technique in separating to determine this intrinsic transformation parameter of this DUT.
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| US13/029,328 | 2011-02-17 | ||
| US13/029,328 US8618826B2 (en) | 2009-07-02 | 2011-02-17 | Method and apparatus for de-embedding |
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| US10797672B2 (en) | 2017-12-28 | 2020-10-06 | Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. | Signal channel expanding system based on PAD |
| CN108182898A (en) * | 2017-12-28 | 2018-06-19 | 深圳市华星光电半导体显示技术有限公司 | The system of expansion signal path based on PAD |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6211541B1 (en) * | 1999-02-01 | 2001-04-03 | Lucent Technologies, Inc. | Article for de-embedding parasitics in integrated circuits |
| US6872583B1 (en) * | 2000-02-15 | 2005-03-29 | Advanced Micro Devices, Inc. | Test structure for high precision analysis of a semiconductor |
| CN1735815A (en) * | 2002-05-16 | 2006-02-15 | 皇家飞利浦电子股份有限公司 | Method for calibrating and de-embedding, set of devices for de-embedding and vector network analyzer |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7340703B2 (en) * | 2004-08-02 | 2008-03-04 | Hazem Mahmoud Hegazy | Test structures and method for interconnect impedance property extraction |
| US7446017B2 (en) * | 2006-05-31 | 2008-11-04 | Freescale Semiconductor, Inc. | Methods and apparatus for RF shielding in vertically-integrated semiconductor devices |
-
2011
- 2011-06-13 CN CN201110165311.XA patent/CN102645625B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6211541B1 (en) * | 1999-02-01 | 2001-04-03 | Lucent Technologies, Inc. | Article for de-embedding parasitics in integrated circuits |
| US6872583B1 (en) * | 2000-02-15 | 2005-03-29 | Advanced Micro Devices, Inc. | Test structure for high precision analysis of a semiconductor |
| CN1735815A (en) * | 2002-05-16 | 2006-02-15 | 皇家飞利浦电子股份有限公司 | Method for calibrating and de-embedding, set of devices for de-embedding and vector network analyzer |
Non-Patent Citations (2)
| Title |
|---|
| Ground-shielded measuring technique for accurate on-wafer characterization of RF CMOS devices;Troels Emil Kolding et al.;《Proceedings of IEEE International Conference on Microelectronic Test Structures，2000》;20001231;第1页右栏第1段、图1，第2页左栏第1-2段，第3页图2,第4页右栏第2段，第5页左栏第1段、右栏第1-2段、图6-7 * |
| The optimization of on-wafer shield-based test fixture layout;Tero Kaija et al.;《IEEE transactions on microwave theory and techniques，2006》;20060531;第54卷(第5期);第2页左栏第3段 * |
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