CN102637690A - SRAM (Static Random Access Memory) and formation method thereof - Google Patents
SRAM (Static Random Access Memory) and formation method thereof Download PDFInfo
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- CN102637690A CN102637690A CN2012101225516A CN201210122551A CN102637690A CN 102637690 A CN102637690 A CN 102637690A CN 2012101225516 A CN2012101225516 A CN 2012101225516A CN 201210122551 A CN201210122551 A CN 201210122551A CN 102637690 A CN102637690 A CN 102637690A
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Abstract
The invention discloses an SRAM (Static Random Access Memory) and a formation method thereof. The SRAM comprises a memory cell array with multiple memory cells, and each memory cell comprises at least one pull-down NMOS (N-channel Mental-oxide-semiconductor) transistor, a transmission NMOS transistor and a pull-up PMOS (P-channel Mental-oxide-semiconductor) transistor; and a pulling stress layer is respectively formed on the surfaces of the pull-down NMOS transistor and the pull-up PMOS transistor. The method comprises the following steps of: forming the memory cell array with the multiple memory cells, wherein each memory cell comprises at least one pull-down NMOS transistor, one transmission NMOS transistor and one pull-up PMOS transistor; and forming a pulling stress layer for covering the surfaces of the pull-down NMOS transistor and the pull-up PMOS transistor. By utilizing the SRAM and the formation method thereof in the invention, the reading margin and writing margin of the SRAM are improved, and the manufacture procedure is simplified and the technology complexity is reduced.
Description
Technical field
The present invention relates to field of semiconductor fabrication, relate in particular to a kind of SRAM memory and forming method thereof.
Background technology
Static random access memory (Static Random Access Memory; SRAM) as a member in the volatile storage; Have high-speed, low-power consumption and standard technology advantage such as compatibility mutually, be widely used in PC, personal communication, consumption electronic product fields such as (smart card, digital camera, multimedia players).
Fig. 1 is the electrical block diagram of the memory cell of the SRAM memory of existing 6T structure, and said memory cell comprises: a PMOS transistor P1, the 2nd PMOS transistor P2, the first nmos pass transistor N1, the second nmos pass transistor N2, the 3rd nmos pass transistor N3 and the 4th nmos pass transistor N4.
A said PMOS transistor P1, the 2nd PMOS transistor P2, the first nmos pass transistor N1, the second nmos pass transistor N2 form bistable circuit.A said PMOS transistor P1 and the 2nd PMOS transistor P2 are for pulling up transistor; The said first nmos pass transistor N1 and the second nmos pass transistor N2 are pull-down transistor.The 3rd nmos pass transistor N3 and the 4th nmos pass transistor N4 are transmission transistor.
The source electrode of the drain electrode of the grid of the one PMOS transistor P1, the grid of the first nmos pass transistor N1, the 2nd PMOS transistor P2, the drain electrode of the second nmos pass transistor N2, the 4th nmos pass transistor N4 is electrically connected, and forms first memory node 11; The source electrode of the drain electrode of the grid of the 2nd PMOS transistor P2, the grid of the second nmos pass transistor N2, a PMOS transistor P1, the drain electrode of the first nmos pass transistor N1, the 3rd nmos pass transistor N3 is electrically connected, and forms second memory node 12.
The grid of the 3rd nmos pass transistor N3 and the 4th nmos pass transistor N4 is electrically connected with word line WL; The drain electrode of the 3rd nmos pass transistor N3 is electrically connected with the first bit line BL, and the drain electrode of the 4th nmos pass transistor N4 is electrically connected with second bit line (paratope line) BLB; The source electrode of the source electrode of the one PMOS transistor P1 and the 2nd PMOS transistor P2 is electrically connected with power line Vdd; The source electrode of the source electrode of the first nmos pass transistor N1 and the second nmos pass transistor N2 is electrically connected with ground wire Vss.
The operation principle of the memory cell of the SRAM memory of 6T structure is: when word line WL applies high level; The 3rd nmos pass transistor N3 and the 4th nmos pass transistor N4 conducting as transmission transistor; Bistable circuit by a PMOS transistor P1, the first nmos pass transistor N1 and the 2nd PMOS transistor P2, the second nmos pass transistor N2 form can be realized first memory node 11 and second memory node, 12 read or write operations to the SRAM memory from the first bit line BL, second bit line BLB output or input signal.
Prior art adopts strain engineering to change transistorized performance in the memory cell in the process of making the SRAM memory.Usually form the tension stress layer on the nmos pass transistor surface, form compressive stress layer, to improve the mobility of charge carrier rate on PMOS transistor surface.
Though existing SRAM memory construction makes that transistorized performance is improved in the memory cell, the read margin of SRAM memory with write nargin and be not improved.Therefore how to improve the read margin of SRAM memory and write nargin and just become one of those skilled in the art's problem demanding prompt solution.
More introductions about the SRAM memory please refer to the United States Patent (USP) that publication number is US2007/0241411A1.
Summary of the invention
The problem that the present invention solves provides a kind of SRAM memory and forming method thereof, with the read margin that improves the SRAM memory effectively with write nargin.
For addressing the above problem; The embodiment of the invention provides a kind of SRAM memory; Comprise: comprise the memory cell array of a plurality of memory cell, each memory cell comprises at least one pull-down NMOS transistor, transmission nmos pass transistor and one draws the PMOS transistor; Said pull-down NMOS transistor and on draw the transistorized surface of PMOS to be formed with one deck tension stress layer.
Optional, the material of said tension stress layer is one or more combination of silica, silicon nitride or silicon oxynitride.
Optional, the thickness range of said tension stress layer is 50 dusts～2000 dusts.
Optional, the stress of said tension stress layer is in the scope of 0.5Gpa～1.5Gpa.
Optional, said SRAM memory is 6T structure or 8T structure.
Optional, said SRAM memory is the 6T structure, its each memory cell comprises respectively: a PMOS transistor, the 2nd PMOS transistor, first nmos pass transistor, second nmos pass transistor, the 3rd nmos pass transistor and the 4th nmos pass transistor; A said PMOS transistor and the 2nd PMOS transistor draw the PMOS transistor on being; Said first nmos pass transistor and second nmos pass transistor are the pull-down NMOS transistor; Said the 3rd nmos pass transistor and the 4th nmos pass transistor are transmission transistor;
Said word line is electrically connected with the grid of the 3rd nmos pass transistor and the 4th nmos pass transistor;
Said bit line comprises first bit line and second bit line, and first bit line and second bit line are electrically connected with the source electrode of the 3rd nmos pass transistor, the source electrode of the 4th nmos pass transistor respectively;
Transistorized source electrode of the one PMOS and the transistorized source electrode of the 2nd PMOS are electrically connected with power line;
The drain electrode of the drain electrode of first nmos pass transistor and second nmos pass transistor is electrically connected with ground wire;
The source electrode of the grid of the transistorized grid of the one PMOS, first nmos pass transistor, the 2nd PMOS transistor drain, second nmos pass transistor, the drain electrode of the 4th nmos pass transistor are electrically connected; The source electrode of the grid of the transistorized grid of the 2nd PMOS, second nmos pass transistor, a PMOS transistor drain, first nmos pass transistor, the drain electrode of the 3rd nmos pass transistor are electrically connected.
The present invention also provides a kind of formation method of SRAM memory; Said method comprises: form the memory cell array comprise a plurality of memory cell, each memory cell comprises at least one pull-down NMOS transistor, transmission nmos pass transistor and one draws the PMOS transistor; Form to cover said pull-down NMOS transistor and on draw the tension stress layer on PMOS transistor surface.
Optional, the material of said tension stress layer is one or more combination of silica, silicon nitride, silicon oxynitride.
Optional, the thickness range of said tension stress layer is 50 dusts～2000 dusts; The stress of said tension stress layer is in the scope of 0.5Gpa～1.5Gpa.
Optional, form said tension stress layer through chemical vapor deposition method.
Compared with prior art, technical scheme of the present invention has the following advantages at least:
1) in the SRAM memory pull-down NMOS transistor of memory cell with on draw the transistorized surface of PMOS to form one deck tension stress layer, and do not form the tension stress layer on the surface of transmission nmos pass transistor.
Said tension stress layer can improve the channel region mobility of charge carrier rate of nmos pass transistor, improves the saturated source-drain current value of nmos pass transistor; Said tension stress layer also can suppress PMOS transistor channel region mobility of charge carrier rate simultaneously, reduces the transistorized saturated source-drain current value of PMOS.So, in the present invention, draw on said the transistorized saturated source-drain current value of PMOS to reduce; The transistorized saturated source-drain current value of said pull-down NMOS improves; The saturated source-drain current value of said transmission nmos pass transistor is constant.
Because the read margin of SRAM memory equals the ratio between the transistorized saturated source-drain current value of pull-down NMOS and the saturated source-drain current value of transmitting nmos pass transistor; The SRAM memory write nargin equal to transmit nmos pass transistor saturated source-drain current value and on draw the ratio between the transistorized saturated source-drain current value of PMOS.
Therefore, in the present invention, the read margin of said SRAM memory can improve owing to the raising of the transistorized saturated source-drain current value of pull-down NMOS; Its write nargin then can owing on draw the reduction of the transistorized saturated source-drain current value of PMOS to improve.
2) in the present invention, only the pull-down NMOS transistor, on draw the transistorized surface of PMOS to form one deck tension stress layer.With respect to forming stressor layers (tension stress layer and compressive stress layer) in the prior art in two steps, simplified processing step, reduced the complexity of technology.
Description of drawings
Fig. 1 is the electrical block diagram of the memory cell of existing SRAM memory;
Fig. 2 is the schematic flow sheet of a kind of embodiment of SRAM memory formation method of the present invention;
Fig. 3～Fig. 5 is the cross-sectional view of the forming process of SRAM memory of the present invention.
Embodiment
The read-write stability of SRAM memory mainly through read margin with write these two parameters of nargin and weigh.In general, read margin is with to write nargin high more, and the read-write stability of SRAM memory is good more.Wherein, write nargin equal to transmit nmos pass transistor saturated source-drain current value and on draw the ratio between the transistorized saturated source-drain current value of PMOS; Read margin equal the transistorized saturated source-drain current value of pull-down NMOS and the transmission nmos pass transistor saturated source-drain current value between ratio.
The inventor finds in the process of existing manufacturing SRAM memory; Existing SRAM memory forms the tension stress layer on the nmos pass transistor surface; Form compressive stress layer on PMOS transistor surface, though can improve mobility of charge carrier rate in nmos pass transistor and the PMOS transistor, the improvement that writes nargin and read margin is very limited; And form tension stress layer and compressive stress layer and will form the manufacture craft relative complex step by step.
The inventor proposes a kind of SRAM memory and forming method thereof for this reason; Form the tension stress layer than prior art nmos pass transistor surface; Form compressive stress layer on PMOS transistor surface, only need to form one deck tension stress layer on last PMOS transistor and the transistorized surface of pull-down NMOS of drawing.Like this, not only improve the read margin of SRAM memory and write nargin, but also simplified processing procedure, reduced the complexity of technology.
For make above-mentioned purpose of the present invention, feature and advantage can be more obviously understandable, does detailed explanation below in conjunction with the accompanying drawing specific embodiments of the invention.
Set forth detail in the following description so that make much of the present invention.But the present invention can be different from alternate manner described here and implements with multiple, and those skilled in the art can do similar popularization under the situation of intension of the present invention.Therefore the present invention does not receive the restriction of following disclosed embodiment.
Fig. 2 is the schematic flow sheet of a kind of embodiment of SRAM memory formation method of the present invention.With reference to figure 2, said method can comprise:
Step S11 provides substrate, is formed with a plurality of memory cell that ranks are arranged in the said substrate, and each memory cell comprises at least one pull-down NMOS transistor, transmission nmos pass transistor and one draws the PMOS transistor;
Particularly, in the present embodiment, said substrate is a Semiconductor substrate, and the present invention does not limit the material of said Semiconductor substrate.
Step S12, form to cover said pull-down NMOS transistor and on draw the tension stress layer of PMOS transistor and substrate surface;
Step S13 forms dielectric layer on said tension stress layer, on dielectric layer, form interconnection layer, and said interconnection layer comprises word line, bit line, power line and ground wire, and word line, bit line, power line and ground wire are electrically connected with the corresponding crystal pipe through the connector in the dielectric layer.
Fig. 3～Fig. 5 is the cross-sectional view of the forming process of SRAM memory of the present invention.
With reference to figure 3, substrate 300 is provided, be formed with a plurality of memory cell of array arrangement in the said substrate 300, each memory cell comprises at least one pull-down NMOS transistor, transmission nmos pass transistor and one draws the PMOS transistor.
The transistorized total number of nmos pass transistor and PMOS can be 6 or 8 in each memory cell of said SRAM memory, that is to say that said SRAM memory can be 6T structure or 8T structure, and the present invention does not limit this.
In an embodiment, the transistorized total number of nmos pass transistor and PMOS is 6 in each memory cell of said SRAM memory, and promptly said SRAM memory is the 6T structure.Particularly, the memory cell of said SRAM memory comprises: a PMOS transistor, the 2nd PMOS transistor, first nmos pass transistor, second nmos pass transistor, the 3rd nmos pass transistor and the 4th nmos pass transistor.
A said PMOS transistor, the 2nd PMOS transistor, first nmos pass transistor, second nmos pass transistor form bistable circuit; And a said PMOS transistor and the 2nd PMOS transistor draw the PMOS transistor on being; Said first nmos pass transistor and second nmos pass transistor are the pull-down NMOS transistor.
Said the 3rd nmos pass transistor and the 4th nmos pass transistor are transmission transistor.
In the present embodiment, saidly comprise that the physical circuit figure of the SRAM memory of 6 transistor arrangements can be with reference to figure 1, the structure similar of SRAM memory in itself and the prior art is so repeat no more at this.
For clearer and easy elaboration the intent of the present invention, only show among Fig. 3 in the memory cell 30 of SRAM memory on the pull-down NMOS transistor 21, one and draw PMOS transistor 22 and a transmission nmos pass transistor 23.
The structure that need to prove the memory cell 30 among Fig. 3 is merely example, and it should not limit protection scope of the present invention.In an embodiment, transistorized arrangement mode can adopt existing any arrangement mode in the ranks arrangement mode of the memory cell of said SRAM memory and each memory cell, repeats no more at this.
The material of said substrate 300 can be monocrystalline silicon (Si), monocrystalline germanium (Ge) or SiGe (GeSi), carborundum (SiC); Also can be silicon-on-insulator (SOI), germanium on insulator (GOI); Perhaps can also be other material, for example III-V compounds of group such as GaAs.The material of said substrate 300 should not limit protection scope of the present invention.
Be formed with in the said substrate 300 pull-down NMOS transistor 21, on draw PMOS transistor 22 and the transmission nmos pass transistor 23.
Particularly, with reference to figure 3, said pull-down NMOS transistor 21 comprises the grid 301 that is arranged in the substrate 300 and the source region and drain region (figure does not indicate) that are positioned at grid 301 both sides substrates 300; The grid 302 that draws PMOS transistor 22 to comprise on said to be arranged in the substrate 300 and the source region and drain region (figure does not indicate) that are positioned at grid 302 both sides substrates 300; Said transmission nmos pass transistor 23 comprises the grid 303 that is positioned in the substrate 300 and the source region and the drain region (not shown) that are positioned at grid 303 both sides substrates 300.
Also be formed with isolation structure of shallow trench 304 in the said substrate 300, be used to isolate adjacent transistors.Above-mentioned each transistor (pull-down NMOS transistor 21, on draw PMOS transistor 22 and transmission nmos pass transistor 23) and the generation type of the generation type of isolation structure of shallow trench 304 and prior art are similar, so repeat no more at this.
With reference to figure 4, form to cover said pull-down NMOS transistor 21 with on draw the tension stress layer 305 on PMOS transistor 22 and substrate 300 surfaces.
Particularly, the step that forms said tension stress layer 305 can comprise: at first, form to cover said pull-down NMOS transistor 21, on draw the tension stress layer 305 on PMOS transistor 22, transmission nmos pass transistor 23 and substrate 300 surfaces; Then, the tension stress layer 305 on the said transmission nmos pass transistor of etching 23 surfaces is until exposing substrate 300.
Certainly, also can adopt other modes to form said tension stress layer 305, for example, can also comprise: the surface at said transmission nmos pass transistor 23 forms mask layer; Said pull-down NMOS transistor 21, on draw the surface of PMOS transistor 22 and substrate 300 to form tension stress layer 305; Removal is formed at the mask layer on said transmission nmos pass transistor 23 surfaces.
Above-mentioned generation type about said tension stress layer 305 is merely and illustrates, and it should not limit protection scope of the present invention.
The material of said tension stress layer 305 can be one or more combination of silica, silicon nitride, silicon oxynitride.
In the present embodiment; Form said tension stress layer 305 through chemical vapor deposition method; Said chemical vapor deposition method can be low pressure chemical vapor deposition method (LPCVD) or plasma enhanced chemical vapor deposition processes (PECVD), and it should not limit protection scope of the present invention.
In the present embodiment, said pull-down NMOS transistor 21 with on draw the surface of PMOS transistor 22 to form one deck tension stress layer 305.Said tension stress layer 305 can improve the channel region mobility of charge carrier rate of said pull-down NMOS transistor 21, improves the saturated source-drain current value of said pull-down NMOS transistor 21; Simultaneously said tension stress layer 305 can suppress the channel region mobility of charge carrier rate of drawing PMOS transistor 22 on said, reduces the saturated source-drain current value of drawing PMOS transistor 22 on said.In addition, because the surface of said transmission nmos pass transistor 23 does not form the tension stress layer, therefore, the channel region mobility of charge carrier rate of said transmission nmos pass transistor 23 and saturated source-drain current value can not change.
Well known to a person skilled in the art that the read margin of SRAM equals transistorized saturated source-drain current value of pull-down NMOS and the ratio that transmits the saturated source-drain current value of nmos pass transistor; The SRAM memory write nargin equal to transmit nmos pass transistor saturated source-drain current value and on draw the ratio between the transistorized saturated source-drain current value of PMOS.
Therefore, when the memory cell of SRAM memory was carried out read operation, because the existence of tension stress layer 305, said SRAM memory reads nargin and writes nargin all can be increased, thereby had improved the stability of SRAM memory read/write.
On the other hand, in the prior art, need usually on the PMOS transistor, to form compressive stress layer in two steps and on nmos pass transistor, form the tension stress layer.Compared with prior art, only need in the present embodiment to form one deck tension stress layer 305, thereby simplified processing step, reduced the complexity of technology.
In the present embodiment, the thickness range of said tension stress layer 305 is 50 dusts～2000 dusts, for example can be 50 dusts, 100 dusts, 200 dusts, 500 dusts, 1000 dusts, 1500 dusts and 2000 dusts.
Said tension stress layer 305 can improve the carrier mobility of nmos pass transistor, can suppress PMOS transistor mobility of charge carrier rate accordingly.But; The inventor is through repeatedly experiment discovery, if the stress of tension stress layer 305 is too high, it is too many to make that the saturated source-drain current value of drawing PMOS transistor 22 descends; Thereby draw the operate as normal of PMOS transistor 22 in the influence, and then influence the stability of SRAM memory.
In the present embodiment; The stress of said tension stress layer 305 is in the scope of 0.5Gpa～1.5Gpa; Under this stress; Tension stress layer 305 can reach comparatively ideal effect, and tension stress layer 305 can improve the saturated source-drain current value 10%～30% of pull-down NMOS transistor 21, draws the saturated source-drain current value 10%～30% of PMOS transistor 22 on reducing.
Like this, under the constant situation of saturated source-drain current value of transmission nmos pass transistor 23,, the raising of the saturated source-drain current value of pull-down NMOS transistor 21 reads nargin owing to having improved the SRAM memory.Correspondingly, under the constant situation of saturated source-drain current value of transmission nmos pass transistor 23, owing on draw the reduction of the saturated source-drain current value of PMOS transistor 22 to improve the SRAM memory to write nargin.Read margin with write under the situation that nargin improves simultaneously, the read-write stability of said SRAM memory also improves greatly.
With reference to figure 5; Continuation forms dielectric layer 306 on said tension stress 305; On dielectric layer 306, form interconnection layer 307; Said interconnection layer 307 comprises metal interconnecting wires, word line, bit line, power line and ground wire, and metal interconnecting wires, word line, bit line, power line and ground wire are electrically connected with the corresponding crystal pipe through the connector (not shown) in the dielectric layer 306.
Said word line is electrically connected with the grid of the 3rd nmos pass transistor and the 4th nmos pass transistor;
Said bit line comprises first bit line and second bit line, and first bit line and second bit line are electrically connected with the drain electrode of the 3rd nmos pass transistor, the drain electrode of the 4th nmos pass transistor respectively;
Transistorized source electrode of the one PMOS and the transistorized source electrode of the 2nd PMOS are electrically connected with power line through metal interconnecting wires;
The source electrode of the source electrode of first nmos pass transistor and second nmos pass transistor is electrically connected with ground wire through metal interconnecting wires;
The drain electrode of the grid of the transistorized grid of the one PMOS, first nmos pass transistor, the 2nd PMOS transistor drain, second nmos pass transistor, the source electrode of the 4th nmos pass transistor are electrically connected through metal interconnecting wires each other; The drain electrode of the grid of the transistorized grid of the 2nd PMOS, second nmos pass transistor, a PMOS transistor drain, first nmos pass transistor, the source electrode of the 3rd nmos pass transistor are electrically connected through metal interconnecting wires each other.
Said form dielectric layer 306 on the said tension stress 305 and on dielectric layer 306, form in step and the prior art of interconnection layer 307 corresponding step similar, so repeat no more at this.
The present invention also provides a kind of SRAM memory, and said SRAM memory comprises the memory cell array that comprises a plurality of memory cell.With reference to figure 5, it shows a memory cell 30 in the said SRAM memory.Particularly, said memory cell 30 comprises: be positioned at least one the pull-down NMOS transistor 21 in the substrate 300, one and draw PMOS transistor 22 and a transmission nmos pass transistor 23; Said pull-down NMOS transistor 21 with on draw the surface of PMOS transistor 22 to be formed with one deck tension stress layer 305.
In the present embodiment, the material of said tension stress layer 305 can be one or several combination of silica, silicon nitride, silicon oxynitride, and it should not limit protection scope of the present invention.
The thickness of said tension stress layer 305 is in the scope of 50 dusts～2000 dusts.The stress of said tension stress layer is in 0.5Gpa～1.5Gpa scope.
In the present embodiment, said SRAM memory also comprises the dielectric layer 306 that is positioned on the said tension stress layer 305, is positioned at the interconnection layer 307 on the said dielectric layer 36.
In this enforcement, total number of nmos pass transistor and PMOS pipe is 6 in the memory cell of said SRAM memory, and promptly said SRA memory is the 6T structure.Particularly, the memory cell of said SRAM memory comprises: a PMOS transistor, the 2nd PMOS transistor, first nmos pass transistor, second nmos pass transistor, the 3rd nmos pass transistor and the 4th nmos pass transistor.
A said PMOS transistor and the 2nd PMOS transistor draw the PMOS transistor on being; Said first nmos pass transistor and second nmos pass transistor are the pull-down NMOS transistor, and said the 3rd nmos pass transistor and the 4th nmos pass transistor are the transmission nmos pass transistor.
Said word line is electrically connected with the grid of the 3rd nmos pass transistor and the 4th nmos pass transistor.
Said bit line comprises first bit line and second bit line, and first bit line and second bit line are electrically connected with the source electrode of the 3rd nmos pass transistor, the source electrode of the 4th nmos pass transistor respectively.
Transistorized source electrode of the one PMOS and the transistorized source electrode of the 2nd PMOS are electrically connected with power line; The drain electrode of the drain electrode of first nmos pass transistor and second nmos pass transistor is electrically connected with ground wire; The source electrode of the grid of the transistorized grid of the one PMOS, first nmos pass transistor, the 2nd PMOS transistor drain, second nmos pass transistor, the drain electrode of the 4th nmos pass transistor are electrically connected; The source electrode of the grid of the transistorized grid of the 2nd PMOS, second nmos pass transistor, a PMOS transistor drain, first nmos pass transistor, the drain electrode of the 3rd nmos pass transistor are electrically connected.
But in other embodiments, the transistorized total number of nmos pass transistor and PMOS can also be 8 in the memory cell of said SRAM memory, and it should not limit protection scope of the present invention.
In the present embodiment; The pull-down NMOS transistor 21 of the memory cell of said SRAM memory with on draw the surface of PMOS transistor 22 to form one deck tension stress layer 305; Tension stress layer 305 can improve the channel region mobility of charge carrier rate of pull-down NMOS transistor 21, improves the saturated source-drain current value of pull-down NMOS transistor 21; The channel region mobility of charge carrier rate of drawing PMOS transistor 22 in the tension stress layer 305 meeting inhibition simultaneously, the saturated source-drain current value of drawing PMOS transistor 22 in the reduction.
Therefore when the memory cell of SRAM memory was carried out read operation, because the existence of tension stress layer 305, said SRAM memory reads nargin and writes nargin all can be increased, thereby had improved the stability of SRAM memory read/write.
In addition, owing to only need to form one deck tension stress layer 305, therefore with in the prior art need form the tension stress layer in two steps and compare with compressive stress layer, the processing procedure of SRAM memory of the present invention is simpler, has reduced its process complexity.
Though the present invention with preferred embodiment openly as above; But it is not to be used for limiting the present invention; Any those skilled in the art are not breaking away from the spirit and scope of the present invention; Can utilize the method and the technology contents of above-mentioned announcement that technical scheme of the present invention is made possible change and modification, therefore, every content that does not break away from technical scheme of the present invention; To any simple modification, equivalent variations and modification that above embodiment did, all belong to the protection range of technical scheme of the present invention according to technical spirit of the present invention.
Claims (10)
1. SRAM memory comprises: comprise the memory cell array of a plurality of memory cell, each memory cell comprises at least one pull-down NMOS transistor, transmission nmos pass transistor and one draws the PMOS transistor;
It is characterized in that, said pull-down NMOS transistor and on draw the transistorized surface of PMOS to be formed with one deck tension stress layer.
2. SRAM memory as claimed in claim 1 is characterized in that, the material of said tension stress layer is one or more combination of silica, silicon nitride, silicon oxynitride.
3. SRAM memory as claimed in claim 1 is characterized in that, the thickness range of said tension stress layer is 50 dusts～2000 dusts.
4. SRAM memory as claimed in claim 1 is characterized in that, the stress of said tension stress layer is in 0.5Gpa～1.5Gpa scope.
5. SRAM memory as claimed in claim 1 is characterized in that, said SRAM memory is 6T structure or 8T structure.
6. SRAM memory as claimed in claim 5; It is characterized in that; Said SRAM memory is the 6T structure, and its each memory cell comprises respectively: a PMOS transistor, the 2nd PMOS transistor, first nmos pass transistor, second nmos pass transistor, the 3rd nmos pass transistor and the 4th nmos pass transistor; A said PMOS transistor and the 2nd PMOS transistor draw the PMOS transistor on being; Said first nmos pass transistor and second nmos pass transistor are the pull-down NMOS transistor, and said the 3rd nmos pass transistor and the 4th nmos pass transistor are the transmission nmos pass transistor;
Said word line is electrically connected with the grid of the 3rd nmos pass transistor and the 4th nmos pass transistor;
Said bit line comprises first bit line and second bit line, and first bit line and second bit line are electrically connected with the source electrode of the 3rd nmos pass transistor, the source electrode of the 4th nmos pass transistor respectively;
Transistorized source electrode of the one PMOS and the transistorized source electrode of the 2nd PMOS are electrically connected with power line;
The drain electrode of the drain electrode of first nmos pass transistor and second nmos pass transistor is electrically connected with ground wire;
The source electrode of the grid of the transistorized grid of the one PMOS, first nmos pass transistor, the 2nd PMOS transistor drain, second nmos pass transistor, the drain electrode of the 4th nmos pass transistor are electrically connected; The source electrode of the grid of the transistorized grid of the 2nd PMOS, second nmos pass transistor, a PMOS transistor drain, first nmos pass transistor, the drain electrode of the 3rd nmos pass transistor are electrically connected.
7. the formation method of a SRAM memory is characterized in that, comprising:
Formation comprises the memory cell array of a plurality of memory cell, and each memory cell comprises at least one pull-down NMOS transistor, transmission nmos pass transistor and one draws the PMOS transistor;
Form to cover said pull-down NMOS transistor and on draw the tension stress layer on PMOS transistor surface.
8. the formation method of SRAM memory as claimed in claim 7 is characterized in that, the material of said tension stress layer is one or more combination of silica, silicon nitride or silicon oxynitride.
9. the formation method of SRAM memory as claimed in claim 7 is characterized in that, the thickness range of said tension stress layer is 50 dusts～2000 dusts; The stress of said tension stress layer is in the scope of 0.5Gpa～1.5Gpa.
10. the formation method of SRAM memory as claimed in claim 7 is characterized in that, forms said tension stress layer through chemical vapor deposition method.
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Cited By (2)
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| CN103730469A (en) * | 2014-01-07 | 2014-04-16 | 上海华虹宏力半导体制造有限公司 | SRAM (static random access memory) unit and forming method thereof |
| CN116437657A (en) * | 2023-06-14 | 2023-07-14 | 合肥晶合集成电路股份有限公司 | Method for preparing static random access memory unit |
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