CN102637059B - Time deviation processing device and processing method thereof - Google Patents
Time deviation processing device and processing method thereof Download PDFInfo
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- CN102637059B CN102637059B CN201110037327.2A CN201110037327A CN102637059B CN 102637059 B CN102637059 B CN 102637059B CN 201110037327 A CN201110037327 A CN 201110037327A CN 102637059 B CN102637059 B CN 102637059B
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Abstract
The invention discloses a time deviation processing device and a processing method thereof. The device comprises a data sending chip, and a data receiving chip and N data lines, wherein the data receiving chip comprises a sequence control unit, a command generating unit, a delayed control unit, a data grabbing unit and a data comparing unit; the command generating unit sends a command to notice the data sending chip so as to send data, and the delayed control unit comprises N adjustable delay lines; the N data lines and the N adjustable delay lines are correspondingly connected, and the data grabbing unit comprises N latches used for grabbing time delay data; and the N adjustable delay lines and the N latches are correspondingly connected, the data comparing unit comprises N comparators, and the N latches and the N comparators are correspondingly connected. The time deviation processing device provided by the invention can measure time deviation and automatically eliminate the measured time deviation, can measure time deviation in a periodicity manner and automatically eliminate the deviation, is low in cost, and is very suitable for popularization and application.
Description
Technical field
The present invention relates to the time deviation between multidigit high speed parallel interface between the chip in the communication technology, relate in particular to a kind of time deviation treating apparatus and disposal route thereof.
Background technology
Since entering 21 century, global communications industry is grown up with surprising rapidity, has shown huge potentiality and swift and violent growth momentum, and its development changes the layout of information industry just in the world.Time deviation between chip between multidigit high speed parallel interface, has important impact to the development of communication.Multidigit high speed parallel interface between chip, as shown in Figure 1, CHIP0 is that data send chip, CHIP1 is data receiver chip, CLOCK is clock, DATA LINE is the data line of N position, and under the control of clock CLOCK, N bit data sends chip (CHIP0) from data and transfers to data receiver chip (CHIP1).Such as high-speed DRAM interface (comprising DDR/DDR2/DDR3 etc.), high speed NAND Flash interface, MDDI interface at a high speed etc.
Life period deviation between each signal of data line DATA (SKEW, the i.e. different and deviation that causes of signal lag), and there are three aspects in the source of this time deviation (SKEW):
Signal sends by data the time deviation (SKEW) that chip (CHIP0) produces, i.e. tSKEW_OUT,
The SKEW that signal is produced by printed circuit board (PrintedCircuitBoard is called for short PCB), i.e. tSKEW_PCB,
The time deviation (SKEW) that signal is produced by data receiver chip (CHIP1), i.e. tSKEW_IN,
The existence of these time deviations (SKEW) causes the valid window of data DATA to diminish, as shown in Figure 2.T is the speed cycle of data DATA, and Tskew is the total SKEW between data DATA.For traditional low-rate signal, because T is very large, the impact of Tskew can be left in the basket, and along with the speed of data promotes, the impact of Tskew just cannot be left in the basket.For example suppose that Tskew is 0-1ns (how second, part per billion second); In the time that the speed of data is 50Mbps (megabit per second), T is 20ns, and now the valid window of data is 18ns, therefore can ignore the impact of Tskew; In the time that the speed of data is 500Mbps, T is 2ns, and now the valid window of data is even 0.For high-speed interface data, the control of time deviation (SKEW) is extremely important as can be seen here.
Multidigit high speed parallel interface in ideal, data send chip (CHIP0) and send long numeric data in a moment, transmit by long numeric data line, and data receiver chip (CHIP1) receives long numeric data in another moment simultaneously.In actual application, due to time deviation, the moment possibility that data receiver chip (CHIP1) receives long numeric data is different.Therefore, need to time deviation be measured and be eliminated, target be to allow make data receiver chip receive at synchronization the long numeric data that data transmission chip sends as far as possible.
Classic method is mainly that the reason producing according to time deviation (SKEW) is controlled, and for example, in order to reduce tSKEW_PCB, requires all signals to be consistent at the cabling of printed circuit board (PCB) as far as possible.The drawback of the method is the time deviation (SKEW) that will reach enough little, to chip and printed circuit board (PCB) require highly, and cannot eliminate process deviation and the individual deviation of product.
Summary of the invention
The object of the present invention is to provide a kind of time deviation treating apparatus and disposal route thereof, can Measuring Time deviation and automatically eliminated, and less demanding to chip and printed circuit board (PCB); And in the time that supply voltage and temperature change, can periodic measurement time deviation and automatically eliminated, cost is low, is highly suitable for promotion and application.
Above-mentioned purpose is achieved through the following technical solutions:
A kind of time deviation treating apparatus, comprises that data send chip, data receiver chip and N position datawire; Described data receiver chip comprises timing control unit, order generation unit, time delay regulon, data placement unit and data comparing unit; Described order generation unit, notifies described data to send chip transmission data for sending order, by described timing control unit control; Described time delay regulon comprises N adjustable delay line, and the delay value of each described adjustable delay line is by described timing control unit control; Described N position datawire is connected with N adjustable delay line is corresponding; Described data placement unit, comprises N latch, for capturing the data after time delay, by described timing control unit and clock control; Described N adjustable delay line is connected with N latch is corresponding; Described data comparing unit, comprises N comparer, by described timing control unit control; A described N latch is connected with N comparer is corresponding; Described timing control unit, control command generation unit, time delay regulon, data placement unit and data comparing unit.
Each described adjustable delay line is K level adjustable delay line, is composed in series by K delay unit, and the K of a K delay unit gating signal is respectively K-1, K-2, and K-3 ..., 0;
The deviation processing method of above-mentioned time deviation treating apparatus comprises the measuring method of time deviation, comprises the steps:
The first step: described timing control unit, by the sequence number of effective gating signal of time delay regulon (representing with m) assignment, m=K-1;
Second step: described timing control unit control time delay regulon, make m gating signal of N K level adjustable delay line effective, other gating signals are invalid;
The 3rd step: order generation unit described in described timing control unit control, sends order and notify described data send chip transmission characteristic and characteristic correspondence is sent to N comparer;
The 4th step: N latch of described timing control unit control, captures data, and be sent to N comparer by capturing data correspondence after N time delay after time delay;
The 5th step: described each comparer of timing control unit control will capture data after time delay and characteristic compares, and record whether capture data after time delay correct compared with characteristic;
The 6th step: described timing control unit judges whether m is zero;
If m is not equal to zero:, m=m-1, jumps to second step;
If m equals zero:, carry out the 7th step: described timing control unit compares K record data of each K level adjustable delay line, obtain according to comparative result the delay value that each K level adjustable delay line needs, determine the progression of the delay unit that each K level adjustable delay line need to access and be uploaded to timing control unit; And then the progression of definite N K level adjustable delay line delay unit that need to access be uploaded to timing control unit;
The 8th step: the measuring method of end time deviation.
Described time deviation disposal route comprises the removing method of time deviation, and described removing method moves after measuring method finishes; Comprise the steps:
The first step: the progression of the delay unit that each K level adjustable delay line of determining according to the measuring method of time deviation need to access, the progression of the delay unit of N K level adjustable delay line access of described timing control unit control;
Second step: order generation unit described in described timing control unit control, sends order and notify described data to send the data that chip transmission needs transmission;
The 3rd step: N K level adjustable delay line carries out respectively time delay according to the progression of the delay unit of each K level adjustable delay line access to data;
The 4th step: described timing control unit and clock control data placement unit capture the data after time delay.
Time deviation treating apparatus of the present invention and disposal route thereof, can Measuring Time deviation and automatically eliminated, and less demanding to chip and printed circuit board (PCB); And in the time that supply voltage and temperature change, can periodic measurement time deviation and automatically eliminated, cost is low, is highly suitable for promotion and application.
Brief description of the drawings
Fig. 1 is the structural representation of multidigit high speed parallel interface between chip;
Fig. 2 is the schematic diagram that the existence of time deviation causes the valid window of data to diminish;
Fig. 3 is the schematic diagram of the data receiver chip of time deviation treating apparatus of the present invention;
Fig. 4 is the schematic diagram of the adjustable delay line of time deviation treating apparatus of the present invention;
Fig. 5 is the schematic diagram of a kind of delay unit of the adjustable delay line of time deviation treating apparatus of the present invention;
Fig. 6 is the schematic diagram of the another kind of delay unit of the adjustable delay line of time deviation treating apparatus of the present invention;
Fig. 7 is the process flow diagram of the measuring method of the time deviation of time deviation disposal route of the present invention.
Embodiment
In order to make object of the present invention, technical scheme and advantage clearer, below in conjunction with drawings and Examples, time deviation treating apparatus of the present invention and disposal route thereof are further elaborated.Should be appreciated that specific embodiment described herein, only in order to explain the present invention, is not intended to limit the present invention.
Embodiment mono-
Time deviation treating apparatus of the present invention, comprises that data send chip CHIP0, data receiver chip CHIP1 and N position datawire DATA LINE, and data send chip CHIP0 from data and transfer to data receiver chip CHIP1 through N position datawire DATA LINE; N position datawire DATA LINE uses respectively the 1st position datawire, the 2nd position datawire, and the 3rd position datawire ..., N position datawire represents.Time deviation treating apparatus of the present invention comprises Measuring Time deviation and eliminates time deviation the processing of time deviation.
As shown in Figure 3, described data receiver chip CHIP1 comprises timing control unit, order generation unit, time delay regulon, data placement unit and data comparing unit.
Described order generation unit, notifies described data to send chip CHIP0 to send data for sending order, by described timing control unit control:
In the process of Measuring Time deviation, timing control unit control command generation unit sends order notification data and sends chip CHIP0 transmission characteristic (this characteristic is only for Measuring Time deviation);
In the process of elimination time deviation, timing control unit control command generation unit sends order notification data and sends the data that chip CHIP0 transmission need to be transmitted.
Described time delay regulon comprises N adjustable delay line, and the delay value of each described adjustable delay line is by described timing control unit control.
N adjustable delay line used respectively the 1st adjustable delay line, the 2nd adjustable delay line, and the 3rd adjustable delay line ..., N adjustable delay line represents.N position datawire is connected with N adjustable delay line is corresponding, and the 1st position datawire is connected with the 1st adjustable delay line, and the 2nd position datawire is connected with the 2nd adjustable delay line ..., N position datawire is connected with N adjustable delay line.
Described data placement unit comprises N latch, for capturing the data after time delay, is controlled by described timing control unit and clock CLOCK:
In the process of measurement and elimination time deviation, described timing control unit and clock CLOCK control described data placement unit and capture the data after time delay.If just, under clock CLOCK controls, the data that described data placement unit captures after time delay had both comprised that valid data also comprised invalid data; Increase described timing control unit and jointly control, select valid data, be further processed.
N latch used respectively the 1st latch, the 2nd latch, and the 3rd latch ..., N latch represents.N adjustable delay line is connected with N latch is corresponding, and the 1st adjustable delay line is connected with the 1st latch, and the 2nd adjustable delay line is connected with the 3rd latch ..., N adjustable delay line is connected with N latch.
Described data comparing unit, comprises N comparer, by described timing control unit control.
In the process of Measuring Time deviation, described data comparing unit will capture data after time delay and characteristic compares, and records whether capture data after time delay correct compared with characteristic;
In the process of elimination time deviation, the delay value that described data comparing unit needs each described adjustable delay line is uploaded to timing control unit.
N comparer used respectively the 1st comparer, the 2nd comparer, and the 3rd comparer ..., N comparer represents.N latch is connected with N comparer is corresponding, and the 1st latch is connected with the 1st comparer, and the 2nd latch is connected with the 2nd comparer ..., N latch is connected with N comparer.
Preferably, the input end of comparer is two; In the process of Measuring Time deviation, the input of comparer is respectively the data after characteristic and time delay.
Described timing control unit, control command generation unit, time delay regulon, data placement unit and data comparing unit:
In the process of Measuring Time deviation, described timing control unit control command generation unit, time delay regulon, data placement unit and data comparing unit; Characteristic is transferred to data comparing unit by timing control unit control.
In the process of elimination time deviation, described timing control unit control command generation unit, time delay regulon and data placement unit.
Preferably, described comparer is D type flip-flop (D type flip-flop, DFF).
Preferably, as shown in Figure 4, each described adjustable delay line is K level adjustable delay line, be composed in series by K delay unit (representing with DLY_CELL), K delay unit (DLY_CELL) used respectively K delay unit, (K-1) number delay unit, (K-2) number delay unit,, No. 1 delay unit represents; The K of a K delay unit gating signal is respectively K-1, K-2, and K-3 ..., 0.
Each delay unit comprises three input ends (use respectively i0, i1, s represents), 1 output terminal (representing with o) and 1 enable signal end (representing with en).Input end of each delay unit is connected with the signal (representing with i) that needs time delay, this input end of delay unit is defined as to the input end i0 of the signal that needs time delay; Another input end of each delay unit is connected with gating signal, and this input end of delay unit is defined as to gating signal end s; The 3rd input end of delay unit connected with the output terminal o of other delay unit, and this input end of delay unit is defined as to series connection end i1; The enable signal end en of each delay unit is connected with enable signal.
The time delay of each delay unit is Tdelay_cell;
In the gating signal (being K-1) of K delay unit, effectively time, K delay unit accesses adjustable delay line, and the delay value of adjustable delay line is K × Tdelay_cell; The time delay of data being carried out is K × Tdelay_cell;
In the gating signal (being K-2) of (K-1) number delay unit, effectively time, K-1 delay unit accesses adjustable delay line, and the delay value of adjustable delay line is (K-1) × Tdelay_cell; The time delay of data being carried out is (K-1) × Tdelay_cell;
…
In the gating signal of No. 1 delay unit (0) effectively time, 1 delay unit access adjustable delay line, the delay value of adjustable delay line is Tdelay_cell; The time delay of data being carried out is 1 × Tdelay_cell.
Preferably, as shown in Figure 5, each described delay unit comprise one with door (representing with and), two rejection gates (representing with nor) and one or more time delay door (representing with buf); Multiple time delay door buf series connection.Time delay Tdelay_cell=2 × Tnor+n × the Tbuf of each delay unit; (Tnor and Tbuf are respectively the gate delay of rejection gate nor and time delay door buf, and n is the number of time delay door buf).Can Tdelay_cell as required in actual use determine the number (being the size of n) of time delay door buf.
With two input ends of door and, an input end is as gating signal input end s, and another input end is as the input end i0 of signal that needs time delay; With the input as rejection gate nor of the output terminal of door and, the output of enable signal or a upper delay unit is as an input (i.e. series connection end i1) of rejection gate nor; The output of rejection gate nor is as the input of time delay door buf, and multiple time delay door buf connect; The output of time delay door buf is as the input of another rejection gate nor, and enable signal is as another input of this rejection gate nor, and the output of this rejection gate nor is as the input of next number delay unit or the output of this adjustable delay line.
When enable signal (en) is low level, adjustable delay lineman does, and when gating signal input end (s) is high level, selects to pass through.
Preferably, as shown in Figure 6, each described delay unit comprises one or (representing with or), two Sheffer stroke gates (representing with nand) and one or more time delay door (representing with buf); Multiple time delay door buf series connection.Time delay Tdelay_cell=2 × Tnand+n × the Tbuf of each delay unit; (Tnand and Tbuf are respectively the gate delay of Sheffer stroke gate nand and time delay door buf, and n is the number of time delay door buf).Can Tdelay_cell as required in actual use determine the number (being the size of n) of time delay door buf.
Or two input ends of door or, an input end is as gating signal input end s, and another input end is as the input end i0 of signal that needs time delay; Or the output terminal of door or is as an input of Sheffer stroke gate nand, the output of enable signal or a upper delay unit is as an input (i.e. i1 is held in series connection) of Sheffer stroke gate nand; The output of Sheffer stroke gate nand is as the input of time delay door buf, and the output of time delay door buf is as the input of another time delay door buf, and enable signal is as the input of this time delay door buf, and multiple time delay door buf connect; The output of time delay door buf is as the input of another Sheffer stroke gate nand, and enable signal is as another input of this Sheffer stroke gate nand, and the output of this Sheffer stroke gate nand is as the input of next number delay unit or the output of this adjustable delay line.
When enable signal (en) is high level, adjustable delay lineman does, and when gating signal input end (s) is low level, selects to pass through.
Embodiment bis-
The time deviation disposal route of embodiment mono-time deviation processing device, described time deviation disposal route comprises the measuring method of time deviation, comprises the steps:
The first step: described timing control unit, by the sequence number of effective gating signal of time delay regulon (being N K level adjustable delay line) (representing with m) assignment, m=K-1;
Second step: described timing control unit control time delay regulon (being N K level adjustable delay line), make m gating signal of N K level adjustable delay line effective, other gating signals are invalid;
The 3rd step: order generation unit described in described timing control unit control, sends order and notify described data send chip transmission characteristic and characteristic correspondence is sent to N comparer;
The 4th step: N latch of described timing control unit control, captures data, and be sent to N comparer by capturing data correspondence after N time delay after time delay;
The 5th step: described each comparer of timing control unit control will capture data after time delay and characteristic compares, and record whether capture data after time delay correct compared with characteristic;
The 6th step: described timing control unit judges whether m is zero;
If m is not equal to zero:, m=m-1, jumps to second step;
If m equals zero:, carry out the 7th step: described timing control unit compares K record data of each K level adjustable delay line, according to comparative result (to not right critical point) obtain the delay value that each K level adjustable delay line needs, determine the progression of the delay unit that each K level adjustable delay line need to access and be uploaded to timing control unit; And then the progression of definite N K level adjustable delay line delay unit that need to access be uploaded to timing control unit;
The 8th step: the measuring method of end time deviation.
Be explained for example:
N=3, N position datawire is 3 position datawires, is respectively the 1st position datawire, the 2nd position datawire, the 3rd position datawire;
N adjustable delay line is 3 adjustable delay lines, is respectively the 1st adjustable delay line, the 2nd adjustable delay line, the 3rd adjustable delay line;
N latch is 3 latchs, is respectively the 1st latch, the 2nd latch, the 3rd latch;
N comparer is 3 comparers, is respectively the 1st comparer, the 2nd comparer, the 3rd comparer;
K=5; Being that each K level adjustable delay line is 5 grades of adjustable delay lines, comprising 5 delay units, is respectively No. 5 delay units, No. 4 delay units, No. 3 delay units, No. 2 delay units, No. 1 delay unit; The gating signal of 5 delay units is respectively 4,3, and 2,1,0.
In the measuring method of time deviation, for the 1st position datawire:
The first step: described timing control unit, by the sequence number of effective gating signal of the 1st 5 grades of adjustable delay lines (representing with m) assignment, m=K-1=4;
Second step: the 1st 5 grades of adjustable delay lines of described timing control unit control, make the 4th gating signal of the 1st 5 grades of adjustable delay lines effective, other gating signals are invalid;
The 3rd step: order generation unit described in described timing control unit control, sends order and notify described data send chip transmission characteristic bit (1) and characteristic bit (1) correspondence is sent to the 1st comparer;
The 4th step: the 1st latch of described timing control unit control, captures data after time delay 5 Tdelay_cell, and be sent to the 1st comparer by capturing data after time delay 5 Tdelay_cell;
The 5th step: the 1st comparer of described timing control unit control will capture data after time delay 5 Tdelay_cell and characteristic bit (1) compares, and record whether capture data after time delay 5 Tdelay_cell correct compared with characteristic; Hypothetical record data are not right;
The 6th step: described timing control unit judges whether m is zero;
M is non-vanishing,
M=m-1=3, repeats second step to the six steps, wherein after time delay 4 Tdelay_cell, captures data; Hypothetical record data are not right;
M is non-vanishing,
M=m-1=2, repeats second step to the six steps, wherein after time delay 3 Tdelay_cell, captures data; Hypothetical record data are not right;
M is non-vanishing,
M=m-1=1, repeats second step to the six steps, wherein after time delay 2 Tdelay_cell, captures data; Hypothetical record data are not right;
M is non-vanishing,
M=m-1=0, repeats second step to the six steps, wherein after time delay 1 Tdelay_cell, captures data; Hypothetical record data pair;
In like manner, the 2nd position datawire and the 3rd position datawire are carried out to above-mentioned steps simultaneously.
M equals zero: carry out the 7th step:
Represent that by following table 3 position datawires capture the result of data correctness compared with characteristic after different delayed time:
According to comparative result, draw:
For the 1st position datawire:
Described timing control unit compares 5 record data of the 1st 5 grades of adjustable delay lines, according to comparative result (to not right critical point, be time delay 1 Tdelay_cell, the critical point of time delay 2 Tdelay_cell) obtain: delay value 1 Tdelay_cell that the 1st 5 grades of adjustable delay line needs, determines that the progression of the delay unit that the 1st 5 grades of adjustable delay lines need to access is 1 grade and is uploaded to timing control unit.
For the 2nd position datawire:
Described timing control unit compares 5 record data of the 2nd 5 grades of adjustable delay lines, according to comparative result (to not right critical point, be time delay 2 Tdelay_cell, the critical point of time delay 3 Tdelay_cell) obtain: delay value 2 Tdelay_cell that the 2nd 5 grades of adjustable delay line needs, determine that the progression of the delay unit that the 2nd 5 grades of adjustable delay lines need to access is 2 grades and is uploaded to timing control unit.
For the 3rd position datawire:
Described timing control unit compares 5 record data of the 3rd 5 grades of adjustable delay lines, according to comparative result (to not right critical point, be time delay 4 Tdelay_cell, the critical point of time delay 5 Tdelay_cell) obtain: delay value 4 Tdelay_cell that the 3rd 5 grades of adjustable delay line needs, determine that the progression of the delay unit that the 3rd 5 grades of adjustable delay lines need to access is 4 grades and is uploaded to timing control unit.
The 8th step: the measuring method of end time deviation.
Described time deviation disposal route comprises the removing method of time deviation, and described removing method moves after measuring method finishes; Comprise the steps:
The first step: the progression of the delay unit that each K level adjustable delay line of determining according to the measuring method of time deviation need to access, the progression of the delay unit of N K level adjustable delay line access of described timing control unit control;
Second step: order generation unit described in described timing control unit control, sends order and notify described data to send the data that chip transmission needs transmission;
The 3rd step: N K level adjustable delay line carries out respectively time delay according to the progression of the delay unit of each K level adjustable delay line access to data;
The 4th step: described timing control unit and clock CLOCK control data placement unit and capture the data after time delay.
In the removing method of time deviation, do not need data comparing unit.
Preferably, the measuring method cycling service of described time deviation, after the measuring method operation once of described time deviation, the removing method operation of time deviation.
Time deviation treating apparatus of the present invention and disposal route thereof, can Measuring Time deviation and automatically eliminated, and less demanding to chip and printed circuit board (PCB); And in the time that supply voltage and temperature change, can periodic measurement time deviation and automatically eliminated, cost is low, is highly suitable for promotion and application.
Finally it should be noted that obviously, those skilled in the art can carry out various changes and modification and not depart from the spirit and scope of the present invention the present invention.Like this, if these amendments of the present invention and within modification belongs to the scope of the claims in the present invention and equivalent technologies thereof, the present invention is also intended to comprise these changes and modification.
Claims (9)
1. a time deviation treating apparatus, comprises that data send chip, data receiver chip and N position datawire; It is characterized in that:
Described data receiver chip comprises timing control unit, order generation unit, time delay regulon, data placement unit and data comparing unit;
Described order generation unit, notifies described data to send chip transmission data for sending order, by described timing control unit control;
Described time delay regulon comprises N adjustable delay line, and the delay value of each described adjustable delay line is by described timing control unit control; Described N position datawire is connected with N adjustable delay line is corresponding;
Described data placement unit, comprises N latch, for capturing the data after time delay, by described timing control unit and clock control; Described N adjustable delay line is connected with N latch is corresponding;
Described data comparing unit, comprises N comparer, by described timing control unit control; A described N latch is connected with N comparer is corresponding;
Described timing control unit, control command generation unit, time delay regulon, data placement unit and data comparing unit;
In the process of Measuring Time deviation, described timing control unit control command generation unit sends order notification data and sends chip transmission characteristic;
In the process of elimination time deviation, described timing control unit control command generation unit sends order notification data and sends the data that chip transmission need to be transmitted;
In the process of Measuring Time deviation, described data comparing unit will capture data after time delay and characteristic compares, and records whether capture data after time delay correct compared with characteristic;
In the process of elimination time deviation, the delay value that described data comparing unit needs each described adjustable delay line is uploaded to timing control unit;
In the process of Measuring Time deviation, described timing control unit control command generation unit, time delay regulon, data placement unit and data comparing unit; Characteristic is transferred to data comparing unit by timing control unit control;
In the process of elimination time deviation, described timing control unit control command generation unit, time delay regulon and data placement unit; Described in timing control unit control, order generation unit sends to order and notifies described data to send the data that chip transmission needs transmission.
2. time deviation treating apparatus according to claim 1, is characterized in that:
Each described adjustable delay line is K level adjustable delay line, is composed in series by K delay unit, and the K of a K delay unit gating signal is respectively K-1, K-2, and K-3 ..., 0.
3. time deviation treating apparatus according to claim 1, is characterized in that:
The input end of described comparer is two; In the process of Measuring Time deviation, the input of comparer is respectively the data after characteristic and time delay.
4. time deviation treating apparatus according to claim 1, is characterized in that:
Described comparer is D type flip-flop.
5. time deviation treating apparatus according to claim 2, is characterized in that:
Each described delay unit comprises one and door, two rejection gates and one or more time delay door; Multiple time delay door series connection; Time delay Tdelay_cell=2 × Tnor+n × the Tbuf of each delay unit, wherein, Tnor and Tbuf are respectively the gate delay of rejection gate and time delay door, and n is the number of time delay door.
6. time deviation treating apparatus according to claim 2, is characterized in that:
Each described delay unit comprise one or, two Sheffer stroke gates and one or more time delay door; Multiple time delay door series connection; Time delay Tdelay_cell=2 × Tnand+n × the Tbuf of each delay unit, wherein, Tnand and Tbuf are respectively the gate delay of Sheffer stroke gate and time delay door, and n is the number of time delay door.
7. a time deviation disposal route for time deviation treating apparatus, described time deviation treating apparatus comprises:
Comprise that data send chip, data receiver chip and N position datawire; Described data receiver chip comprises timing control unit, order generation unit, time delay regulon, data placement unit and data comparing unit; Described order generation unit, notifies described data to send chip transmission data for sending order, by described timing control unit control; Described time delay regulon comprises N adjustable delay line, and the delay value of each described adjustable delay line is by described timing control unit control; Described N position datawire is connected with N adjustable delay line is corresponding; Described data placement unit, comprises N latch, for capturing the data after time delay, by described timing control unit and clock control; Described N adjustable delay line is connected with N latch is corresponding; Described data comparing unit, comprises N comparer, by described timing control unit control; A described N latch is connected with N comparer is corresponding; Described timing control unit, control command generation unit, time delay regulon, data placement unit and data comparing unit;
Each described adjustable delay line is K level adjustable delay line, is composed in series by K delay unit, and the K of a K delay unit gating signal is respectively K-1, K-2, and K-3 ..., 0;
Described time deviation disposal route comprises the measuring method of time deviation, it is characterized in that: comprise the steps:
The first step: described timing control unit, by the sequence number of effective gating signal of time delay regulon (representing with m) assignment, m=K-1;
Second step: described timing control unit control time delay regulon, make m gating signal of N K level adjustable delay line effective, other gating signals are invalid;
The 3rd step: order generation unit described in described timing control unit control, sends order and notify described data send chip transmission characteristic and characteristic correspondence is sent to N comparer;
The 4th step: N latch of described timing control unit control, captures data, and be sent to N comparer by capturing data correspondence after N time delay after time delay;
The 5th step: described each comparer of timing control unit control will capture data after time delay and characteristic compares, and record whether capture data after time delay correct compared with characteristic;
The 6th step: described timing control unit judges whether m is zero;
If m is not equal to zero:, m=m-1, jumps to second step;
If m equals zero:, carry out the 7th step: described timing control unit compares K record data of each K level adjustable delay line, obtain according to comparative result the delay value that each K level adjustable delay line needs, determine the progression of the delay unit that each K level adjustable delay line need to access and be uploaded to timing control unit; And then the progression of definite N K level adjustable delay line delay unit that need to access be uploaded to timing control unit;
The 8th step: the measuring method of end time deviation.
8. time deviation disposal route according to claim 7, is characterized in that:
Described time deviation disposal route comprises the removing method of time deviation, and described removing method moves after measuring method finishes; Comprise the steps:
The first step: the progression of the delay unit that each K level adjustable delay line of determining according to the measuring method of time deviation need to access, the progression of the delay unit of N K level adjustable delay line access of described timing control unit control;
Second step: order generation unit described in described timing control unit control, sends order and notify described data to send the data that chip transmission needs transmission;
The 3rd step: N K level adjustable delay line carries out respectively time delay according to the progression of the delay unit of each K level adjustable delay line access to data;
The 4th step: described timing control unit and clock control data placement unit capture the data after time delay.
9. time deviation disposal route according to claim 8, is characterized in that:
The measuring method cycling service of described time deviation, after the measuring method operation once of described time deviation, the removing method operation of time deviation.
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| CN201110037327.2A CN102637059B (en) | 2011-02-14 | 2011-02-14 | Time deviation processing device and processing method thereof |
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| CN201110037327.2A CN102637059B (en) | 2011-02-14 | 2011-02-14 | Time deviation processing device and processing method thereof |
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| KR20180005081A (en) * | 2016-07-05 | 2018-01-15 | 삼성전자주식회사 | Memory device having command window generator |
| CN112241615B (en) * | 2020-10-09 | 2021-05-18 | 广芯微电子（广州）股份有限公司 | Method and system for detecting data balance time sequence and electronic equipment |
| CN114978152B (en) * | 2022-05-10 | 2024-06-21 | 上海韬润半导体有限公司 | Latch circuit and digital-to-analog converter including the same |
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| CN100388669C (en) * | 2004-05-26 | 2008-05-14 | 华为技术有限公司 | System and method for regulating clock signal phase difference |
| CN1829129B (en) * | 2005-03-04 | 2010-12-22 | Ut斯达康通讯有限公司 | Method and apparatus for eliminating transmission delay difference in multipath synchronous data transmission |
| JP2007243735A (en) * | 2006-03-09 | 2007-09-20 | Elpida Memory Inc | Dll circuit and semiconductor device comprising the same |
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