CN102629061B - 一种阵列基板及液晶显示装置 - Google Patents
一种阵列基板及液晶显示装置 Download PDFInfo
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Abstract
本发明公开了一种阵列基板及液晶显示装置,涉及液晶显示器的制造领域,实现了一种新型的具体有增大V-T曲线的梯度,对比度,较理想的响应时间等优点的四畴电极结构的阵列基板及液晶显示装置。所述阵列基板包括:栅线、数据线,以及所述栅线和数据线限定的像素单元;其中,所述像素单元中形成有同层设置的像素电极和公共电极;所述公共电极与所述像素电极均为梳状结构,且所述公共电极的梳齿和所述像素电极的梳齿交替设置;所述梳状结构的每一梳齿由结点分为方向不同的上梳齿和下梳齿,且所有上梳齿相互平行,所有下梳齿相互平行;相邻的像素电极和公共电极,两上梳齿间的间距与两下梳齿间的间距不相等。本发明实施例适用于液晶显示器的生产。
Description
技术领域
本发明涉及液晶显示器的制造领域,尤其涉及一种阵列基板及液晶显示装置。
背景技术
液晶显示器是目前最广泛使用的一种平板显示器,具有低功耗、外形薄、重量轻以及低驱动电压等特征。随着液晶平板显示技术的发展,高端液晶显示器正向着高对比度、增大V-T(电压-透光率)曲线的梯度、快速响应等方向发展。
VA(Vertical Alignment,垂直配向技术)液晶显示面板包括:对盒成型的阵列基板和彩膜基板,以及在两基板之间的液晶层;其中,液晶层中液晶分子的排列方式为垂直状。在不加电压时,液晶分子垂直于基板表面排列;在通入开启电压时,像素电极和公共电极之间产生电场,在电场作用下使得液晶分子旋转,将转向与该电场垂直的方向排列,即使得液晶分子的排列方式由垂直态转为水平态,使得一部分光从检偏器射出,得到亮态显示。TBA(Transverse Bend Alignment,横向弯曲排列的液晶显示模式)模式是液晶显示面板中水平电场和垂直电场向混合的一种VA模式。
发明内容
本发明的实施例提供一种阵列基板及液晶显示装置,具体提供了一种新型的具体有增大V-T(电压-透光率)曲线的梯度,对比度,较理想的响应时间等优点的四畴电极结构的阵列基板及液晶显示装置。
为达到上述目的,本发明的实施例采用如下技术方案:
一种阵列基板,包括:栅线、数据线,以及所述栅线和数据线限定的像素单元;其中,所述像素单元中形成有同层设置的像素电极和公共电极;所述公共电极与所述像素电极均为梳状结构,且所述公共电极的梳齿和所述像素电极的梳齿交替设置;所述梳状结构的每一梳齿由结点分为方向不同的上梳齿和下梳齿,且所有上梳齿相互平行,所有下梳齿相互平行;相邻的像素电极和公共电极,两上梳齿间的间距与两下梳齿间的间距不相等。
一种液晶显示装置,包括:阵列基板,彩膜基板,所述阵列基板为上述阵列基板。
本发明实施例提供了一种阵列基板及液晶显示装置,通过将公共电极与像素电极设置为梳状结构,公共电极的梳齿和像素电极的梳齿交替设置,每一梳齿由结点分为上梳齿和下梳齿,所有上梳齿相互平行,所有下梳齿相互平行,并且相邻的像素电极和公共电极,两上梳齿间的间距与两下梳齿间的间距不相等,制作了一种新型的四畴电极结构,包含了这种新型的四畴电极结构的阵列基板及液晶显示装置具有增大V-T(电压-透光率)曲线的梯度,对比度,较理想的响应时间等优点。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案,下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图仅仅是本发明的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他的附图。
图1为本发明实施例提供的一种阵列基板的像素单元的结构示意图之一;
图2为本发明实施例提供的一种阵列基板的像素单元的结构示意图之二;
图3为本发明实施例提供的一种阵列基板的像素单元的结构示意图之三;
图4为本发明实施例提供的一种阵列基板的像素单元的结构示意图之四;
图5为本发明实施例提供的一种阵列基板的像素单元的结构示意图之五;
图6为本发明实施例提供的一种阵列基板的像素单元的结构示意图之六;
图7为本发明实施例提供的一种不规则结点与规则结点在同一条直线上的局部放大示意图;
图8为本发明实施例提供的一种阵列基板的像素单元的结构示意图之八;
图9为本发明实施例提供的一种阵列基板的像素单元的结构示意图之九;
图10为本发明实施例提供的一种阵列基板的像素单元的结构示意图之十;
图11为本发明实施例提供的一种阵列基板的像素单元的结构示意图之十一;
图12为本发明实施例提供的一种增大V-T(电压-透光率)曲线的梯度模拟结果的示意图;
图13为本发明实施例提供的一种增大灰度级-透过度模拟结果的示意图;
附图标记:
10-像素电极,11-公共电极,12-结点,13-上梳齿,14-下梳齿,像素电极的上梳齿-131,公共电极的上梳齿-132,像素电极的下梳齿-141,公共电极的下梳齿-142,两上梳齿间的间距-151,两下梳齿间的间距-152,两个相邻像素电极的两上梳齿间的间距-153,两个相邻公共电极的两上梳齿间的间距-154,两个相邻像素电极的两下梳齿间的间距-155,两个相邻公共电极的两下梳齿间的间距-156,规则结点-16,不规则结点-17。
具体实施方式
下面将结合本发明实施例中的附图,对本发明实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例仅仅是本发明一部分实施例,而不是全部的实施例。基于本发明中的实施例,本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例,都属于本发明保护的范围。
本发明实施例提供了一种阵列基板,如图1所示,所述阵列基板包括:栅线、数据线,以及所述栅线和数据线限定的像素单元;其中,像素单元中形成有同层设置的像素电极10和公共电极11,公共电极11与像素电极10均为梳状结构,且公共电极11的梳齿和像素电极10的梳齿交替设置;梳状结构的每一梳齿由结点12分为方向不同的上梳齿13和下梳齿14,且所有上梳齿13(包括:公共电极的上梳齿132和像素电极的上梳齿131)相互平行,所有下梳齿14(包括:公共电极的下梳齿142和像素电极的下梳齿141)相互平行。相邻的像素电极10和公共电极11,两上梳齿13间的间距151与两下梳齿14间的间距152不相等。
具体的,阵列基板是四畴电极结构,这种四畴电极结构的像素电极10和公共电极11同层设置,并且均为梳状结构,公共电极11的梳齿和像素电极10的梳齿交替设置,且均由每一梳齿的结点12将梳齿分为方向不同的上梳齿13和下梳齿14。所有上梳齿13的方向相同,且相互平行;所有下梳齿的方向相同,且相互平行。在每个相邻的像素电极10和公共电极11中,两上梳齿13间的间距151与两下梳齿14间的间距152不相等。
需要说明的是,由于公共电极和像素电极为梳齿状且每一梳齿由结点分为方向不同的上梳齿和下梳齿,所以像素电极的电极有两个方向,公共电极的电极有两个方向,所以为四畴电极。同层是指利用氧化铟锡制成的一层薄膜,同层设置是针对至少两种图案而言的,是指至少两种图案设置在同一层薄膜上的结构,具体的,是通过构图工艺在同种材料制成的一层薄膜上形成所述至少两种图案。在本发明实施例中,公共电极的梳状结构作为一种图案,像素电极的梳状结构作为另一种图案。
优选的,参考图5所示,两上梳齿13间的间距151与两下梳齿14间的间距152不相等具体为:两上梳齿13间的间距151为第一间距值,两下梳齿14间的间距152为第二间距值;或者,两上梳齿13间的间距151为第二间距值,两下梳齿14间的间距152为第一间距值;其中,第一间距值与第二间距值不相等。
具体的,如图5所示,例如第一间距值为a,第二间距值为b,参考图2所示,若两上梳齿13间的间距151为a,则相应的,两下梳齿14间的间距152为b。若两上梳齿13间的间距151为b,则相应的,两下梳齿14间的间距152为a。
需要说明的是,a与b为任意不相等的两个正实数。
一种情况,如图2所示,两个相邻公共电极11的两上梳齿132间的间距154与两个相邻像素电极10的两上梳齿131间的间距153不相等;两个相邻的公共电极11的下梳齿142间的间距156与两个相邻像素电极10的下梳齿141间的间距155不相等。
具体的,两个相邻公共电极11的两上梳齿132间的间距154是公共电极11和其相邻的像素电极10的两上梳齿13间的间距与此像素电极10和其相邻的另一公共电极11的两上梳齿13间的间距之和。两个相邻像素电极10的两上梳齿131间的间距153是像素电极10和其相邻的公共电极11的两上梳齿13间的间距与此公共电极11和其相邻的另一像素电极10的两上梳齿13间的间距之和。相邻的两个上梳齿13之间的间距151可以相等,也可以不相等,但是两个相邻公共电极11的两上梳齿132间的间距154与两个相邻像素电极10的两上梳齿131间的间距153不相等。两个相邻公共电极11的两下梳齿142间的间距156是公共电极11和其相邻的像素电极10的两下梳齿14间的间距与此像素电极10和其相邻的另一公共电极11的两下梳齿14间的间距之和。两个相邻像素电极10的两下梳齿141间的间距155是像素电极10和其相邻的公共电极11的两下梳齿14间的间距与此公共电极11和其相邻的另一像素电极10的两下梳齿14间的间距之和。相邻的两个下梳齿14间的间距152可以相等,也可以不相等,但是两个相邻的公共电极11的下梳齿142间的间距156与两个相邻像素电极10的下梳齿141间的间距155不相等。
需要说明的是,相邻的两个上梳齿之间的间距可以相等也可以不相等,且相邻的两个下梳齿间的间距可以相等也可以不相等。
优选的,参考如图5所示,所有相邻上梳齿13间的间距151按照第一间距值,第二间距值,第二间距值,第一间距值的循环依次排列,相应的,所有相邻下梳齿14间的间距152按照第二间距值,第一间距值,第一间距值,第二间距值的循环依次排列。或者,所有相邻上梳齿13间的间距151按照第一间距值,第一间距值,第二间距值,第二间距值的循环依次排列,相应的,所有相邻下梳齿14间的间距152按照第二间距值,第二间距值,第一间距值,第一间距值的循环依次排列。
具体的,参考图5所示,根据上述例子,第一间距值为a,第二间距值为b,所有相邻上梳齿13间的间距151按照a,b,b,a的顺序循环依次排列,相应的,所有相邻下梳齿14间的间距152按照b,a,a,b的顺序循环依次排列。或者,所有相邻上梳齿13间的间距151按照a,a,b,b,的顺序循环依次排列,相应的,所有相邻下梳齿14间的间距152按照b,b,a,a,的顺序循环依次排列。
下面以所有相邻上梳齿13间的间距151按照a,b,b,a的顺序循环依次排列,相应的,所有相邻下梳齿14间的间距152按照b,a,a,b的顺序循环依次排列为例进行说明,参考图5所示。
在阵列基板的像素单元中的相邻的公共电极11和像素电极10,最后四个相邻上梳齿13间的间距151按照a,b,b,a的顺序循环排列到最后一个相邻上梳齿13间的间距151可以刚好是个完整的循环,即最后四个上梳齿13间的间距为a,b,b,a。则相应的,最后四个相邻下梳齿14间的间距152按照b,a,a,b的顺序循环排列到最后一个相邻下梳齿13间的间距152也是个完整的循环,即最后四个下梳齿14间的间距为b,a,a,b。当然,最后四个相邻上梳齿13间的间距151按照a,b,b,a的顺序循环排列到最后一个相邻上梳齿13间的间距151可以不是个完整的循环,即最后四个上梳齿13间的间距为a,a,b,b,或者是b,a,a,b,或者是b,b,a,a;相应的,最后四个相邻下梳齿14间的间距152按照b,a,a,b的顺序循环排列到最后一个相邻下梳齿13间的间距152也不是一个完整的循环,可以是,b,b,a,a,或者是,a,b,b,a,或者是a,a,b,b。
需要说明的是,上述按照第一间距值,第二间距值,第二间距值,第一间距值的循环依次排列是所有相邻像素电极与公共电极间的两上梳齿的间距按照第一间距值,第二间距值,第二间距值,第一间距值的顺序排列,当这个完整顺序排列完成后,就会重新开始从这个完整顺序的一个值开始排列,例如,第一到第四个上梳齿的间距顺序为第一间距值,第二间距值,第二间距值,第一间距值,则第五到第八个上梳齿的间距顺序为第一间距值,第二间距值,第二间距值,第一间距值,往后依次重新开始按照第一间距值,第二间距值,第二间距值,第一间距值的顺序循环依次排列。
进一步的,所有结点都为规则结点16,且所有结点不都在同一条直线上。或者,所有结点分为规则结点16和不规则结点17,且所有结点都在同一条直线上。
具体的,由于两上梳齿13间的间距151和两下梳齿14间的间距152不相等,且两个相邻公共电极11的两上梳齿13间的间距154与两个相邻像素电极10的两上梳齿13间的间距153不相等;两个相邻的公共电极11的下梳齿14间的间距156与两个相邻像素电极10的下梳齿14间的间距155不相等,所以,所有规则结点16不都在同一条直线上,如图3所示。当然,在满足上述条件的前提下,将部分结点制作为不规则的结点17,便可以使得所有结点都在同一条直线上,如图4所示。例如,根据上述例子,所有相邻上梳齿13间的间距151按照a,b,b,a的顺序循环依次排列,相应的,所有相邻下梳齿14间的间距152按照b,a,a,b的顺序循环依次排列。所有规则结点可分为三类A,B,C,且这三类结点不在同一条直线上,如图5所示。当然,在满足上述条件的前提下,以A类结点的位置为准,将B类结点和C类结点的位置调整到与A类结点的位置在同一条直线上,这时需将B类结点和C类结点制作为不规则结点,如图6所示。如图7所示,不规则结点17比规则结点16窄。
其中,在此,并不限定必须以A类结点的位置为准,也可以以B类结点的位置或C类结点的位置为准,本发明实施例对此并不做限定。
需要说明的是,规则结点是公共电极或像素电极的上梳齿或下梳齿的上下宽度一致,没有凹曲部分。不规则结点是公共电极或像素电极的上梳齿或下梳齿的上下宽度不一致,有凹曲部分。上述的窄是指因需要将结点所在的公共电极或像素电极的梳齿制作成有凹曲部分的梳齿,窄便指的是此凹曲部分。
另一种情况,如图8所示,相邻的两个上梳齿13之间的间距151不相等,且相邻的两个下梳齿14间的间距152不相等。
具体的,相邻的两个上梳齿13间的间距151是两个不相等的间距值,并且相邻的两个下梳齿14间的间距152也是两个不相等的间距值。
进一步的,如图9所示,两个相邻公共电极11的两上梳齿13间的间距154与两个相邻像素电极10的两上梳齿13间的间距153相等。两个相邻的公共电极11的下梳齿14间的间距156与两个相邻像素10电极的下梳齿14间的间距155相等。
具体的,相邻的两个上梳齿13之间的间距151不相等,但是两个相邻公共电极11的两上梳齿13间的间距154与两个相邻像素电极10的两上梳齿13间的间距153是相等的,相邻的两个下梳齿14间的间距152不相等,但是两个相邻的公共电极11的下梳齿14间的间距156与两个相邻像素10电极的下梳齿14间的间距155是相等的。
优选的,参考图9所示,所有相邻上梳齿13间的间距151按照第一间距值,第二间距值的循环依次排列,相应的,所有相邻下梳齿14间的间距152按照第二间距值,第一间距值的循环依次排列。
具体的,参考图9所示,根据上述例子,第一间距值为a,第二间距值为b,所有相邻上梳齿13间的间距151按照a,b的顺序循环依次排列。相应的,所有相邻下梳齿14间的间距152按照b,a的循环依次排列。
进一步的,所有结点12都为规则结点16,且所有结点12不都在同一条直线上。或者,所有结点12分为规则结点16和不规则结点17,且所有结点12都在同一条直线上。
具体的,由于两上梳齿13间的间距151和两下梳齿14间的间距152不相等,且两个相邻公共电极11的两上梳齿13间的间距154与两个相邻像素电极10的两上梳齿13间的间距153不相等;两个相邻的公共电极11的下梳齿14间的间距156与两个相邻像素电极10的下梳齿14间的间距155不相等,所以,所有规则结点16不都在同一条直线上,如图10所示。当然,在满足上述条件的前提下,将部分结点制作为不规则的结点17,便可以使得所有结点都在同一条直线上,如图11所示。其中,参考图7所示,不规则结点17比规则结点16窄。
本发明实施例提供的一种阵列基板,具有增大V-T(电压-透光率)曲线的梯度,对比度,快速的响应时间等优点。
下面以6/8间隔的电极的模拟结果为例进行说明。
其中,6/8间隔表示电极的第一间距值为6,第二间距值为8。
具体的,SIMPLE_6_8表示现有技术中的二畴6/8间隔的电极设计,以下简称S_6_8。TWSIT_6_8表示本发明实施例中电极的部分规则结点和部分不规则结点在同一条直线上,以下简称T_6_8。No_line_6_8表示本发明实施例中的电极的所有规则结点不在同一条直线上,以下简称N_6_8。
提高对比度的模拟结果如下,
S_6_8 | T_6_8 | N_6_8 | |
CR(max) | 25047.6 | 24925.5 | 25308.1 |
由此可知,本分明实施例中的对比度的最大值为25308.1,而现有技术中的二畴6/8间隔的电极S_6_8的对比度的最大值为25047.6,本发明实施例具有提高对比度的优点且比现有技术中的更好。
减小色差的模拟结果可通过各个色域值间的比较看出,具体比较结果如下,
S_6_8-T_6_8=2.37,
N_6_8-T_6_8=2.09,
S_6_8-N_6_8=0.28,
由此可知,本发明实施例中的现有技术中的S_6_8的色域值与T_6_8的色域值之差为2.37;N_6_8的色域值与T_6_8的色域值之差为2.09;现有技术中的S_6_8的色域值与N_6_8的色域值之差为0.28;通过上述差值结果可以看出,各个色域值(Gamut value)比较结果为S_6_8>N_6_8>T_6_8,所以本发明实施例具有减小色差的优点,且效果比现有技术中的更好。
增大V-T(电压-透过率)曲线的梯度的模拟结果如图12所示:
从图12可看出,本发明实施例中的电极的部分规则结点和部分不规则结点在同一条直线上T_6_8的情况和电极的所有规则结点不在同一条直线上N_6_8的情况比现有技术中的二畴6/8间隔的电极S_6_8到达到某一电压值透过率最大值U1的用时更少,且需要的电压更小,本发明的T_6_8和N_6_8两种情况的最高电压值比现有技术中的S_6_8的最高电压值更大,并且本发明的T_6_8和N_6_8两种情况从某一透过率值到电压透过率最大值在持续跨度比现有技术中的S_6_8得更长,所以本发明实施例具有增大V-T(电压-透光率)曲线的梯度的优点,且效果比现有技术中的更好。
提高灰度级-透过度的模拟结果如图13所示:
从图13可看出,本发明实施例中的电极的部分规则结点和部分不规则结点在同一条直线上T_6_8的提高灰度级-透过度效果更好,且在提高灰度级-透过度方面,本发明实施例中的电极的所有规则结点不在同一条直线上N_6_8的情况与现有技术中的二畴6/8间隔的电极S_6_8在提高灰度级-透过度的效果基板相同,本发明实施例具有提高灰度级-透过度的优点,且效果比现有技术中的更好。
本发明实施例还具有改善失真偏移等其他优点,在此不再全部列举模拟结果说明。
需要说明的是,本发明实施例的模拟都是与二畴6/8间隔的电极S_6_8相比较,因为在现实技术中,二畴6/8间隔的电极S_6_8相对于四畴6/8间隔的电极S_6_8更具有普遍性,模拟结果更能说明问题。
本发明实施例还提供了一种液晶显示装置,包括阵列基板,彩膜基板,所述阵列基板为上述阵列基板。
需要说明的是,液晶显示装置可以是液晶显示面板,液晶显示器,本发明对此不做限制。
本发明实施例提供了一种阵列基板及液晶显示装置,通过将公共电极与像素电极设置为梳状结构,公共电极的梳齿和像素电极的梳齿交替设置,每一梳齿由结点分为上梳齿和下梳齿,所有上梳齿相互平行,所有下梳齿相互平行,并且相邻的像素电极和公共电极,两上梳齿间的间距与两下梳齿间的间距不相等,制作了一种新型的四畴电极结构,包含了这种新型的四畴电极结构的阵列基板及液晶显示装置具有增大V-T(电压-透光率)曲线的梯度,对比度,较理想的响应时间等优点。
以上所述,仅为本发明的具体实施方式,但本发明的保护范围并不局限于此,任何熟悉本技术领域的技术人员在本发明揭露的技术范围内,可轻易想到变化或替换,都应涵盖在本发明的保护范围之内。因此,本发明的保护范围应以所述权利要求的保护范围为准。
Claims (10)
1.一种阵列基板,包括:栅线、数据线,以及所述栅线和数据线限定的像素单元;其中,所述像素单元中形成有同层设置的像素电极和公共电极;所述公共电极与所述像素电极均为梳状结构,且所述公共电极的梳齿和所述像素电极的梳齿交替设置;所述梳状结构的每一梳齿由结点分为方向不同的上梳齿和下梳齿,且所有上梳齿相互平行,所有下梳齿相互平行;其特征在于,相邻的像素电极和公共电极,两上梳齿间的间距与两下梳齿间的间距不相等。
2.根据权利要求1所述的阵列基板,其特征在于,两个相邻公共电极的两上梳齿间的间距与两个相邻像素电极的两上梳齿间的间距不相等;两个相邻的公共电极的下梳齿间的间距与两个相邻像素电极的下梳齿间的间距不相等。
3.根据权利要求1所述的阵列基板,其特征在于,相邻的两个上梳齿之间的间距不相等,且相邻的两个下梳齿间的间距不相等。
4.根据权利要求3所述的阵列基板,其特征在于,两个相邻公共电极的两上梳齿间的间距与两个相邻像素电极的两上梳齿间的间距相等;两个相邻的公共电极的下梳齿间的间距与两个相邻像素电极的下梳齿间的间距相等。
5.根据权利要求1~4任一项所述的阵列基板,其特征在于,所述两上梳齿间的间距与两下梳齿间的间距不相等具体为:所述两上梳齿间的间距为第一间距值,所述两下梳齿间的间距为第二间距值;或者,所述两上梳齿间的间距为第二间距值,所述两下梳齿间的间距为第一间距值;其中,所述第一间距值与第二间距值不相等。
6.根据权利要求5所述的阵列基板,其特征在于,所有相邻上梳齿间的间距按照第一间距值,第二间距值,第二间距值,第一间距值的循环依次排列,相应的,所有相邻下梳齿间的间距按照第二间距值,第一间距值,第一间距值,第二间距值的循环依次排列;或者,所有相邻上梳齿间的间距按照第一间距值,第一间距值,第二间距值,第二间距值的循环依次排列,相应的,所有相邻下梳齿间的间距按照第二间距值,第二间距值,第一间距值,第一间距值的循环依次排列。
7.根据权利要求5所述的阵列基板,其特征在于,所有相邻上梳齿间的间距按照第一间距值,第二间距值的循环依次排列,相应的,所有相邻下梳齿间的间距按照第二间距值,第一间距值的循环依次排列。
8.根据权利要求1~4、6~7任一项所述的阵列基板,其特征在于,所有结点都为规则结点,且所有结点不都在同一条直线上;或者,
所有结点分为规则结点和不规则结点,且所有结点都在同一条直线上。
9.根据权利要求8所述的阵列基板,其特征在于,所述不规则结点比所述规则结点窄。
10.一种液晶显示装置,包括:阵列基板,彩膜基板,其特征在于,所述阵列基板为权利要求1~9任一项所述的阵列基板。
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