CN102624401A - Compatible structure and unstructured low density parity check (LDPC) decoder and decoding algorithm - Google Patents
Compatible structure and unstructured low density parity check (LDPC) decoder and decoding algorithm Download PDFInfo
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Abstract
The invention provides a high-efficiency low density parity check (LDPC) decoder structure and a data conflict solution. The decoder adopts a universal serial processing mode, and an LDPC decoding algorithm and a hardware architecture are specially optimized. The classical turbo decoding message passing (TDMP) algorithm cannot be applied to unstructured LDPC codes such as LDPC codes in digital video broadcasting-satellite-second generator (DVB-S2) and China mobile multimedia broadcasting (CMMB). If the TDMP algorithm is directly adopted, a data conflict can be caused, and the performance of LDPC codes can be lowered. The TDMP algorithm is optimized, so that the TDMP algorithm can be well applied to the unstructured LDPC codes. The conventional reading-writing of external information is finished at a time, and a large memory space is required; and improvement is made, so that the memory space required by the decoder is effectively reduced. In terms of a processing unit, the recovery of the external information and the update operation of prior information and posterior information are also optimized. Moreover, in order to achieve compatibility with structured and unstructured LDPC codes, a main decoding time sequence is optimized. By the optimization measures, the hardware utilization efficiency of the decoder is improved.
Description
Technical field
The invention belongs to communication technical field, be specifically related to the decoding algorithm and the decoder architecture of forward error correction-LDPC sign indicating number, mainly comprise compatibility, decoder hardware architecture and the timing optimization of TDMP optimization Algorithm, structuring and destructuring LDPC decoding.
Background technology
R.Gallager has at first proposed LDPC sign indicating number (Low Density Parity Check Codes low density parity check code) in 1962; But because at that time calculated level and people are to the insufficient recognition of this sign indicating number, the LDPC sign indicating number did not come into one's own in decades after this.After 1993, people such as MacKay have rediscovered the LDPC sign indicating number.The performance of this yard is very excellent, even when code length is longer, can approach the Shannon limit, and LDPC also has less decoding error probability and lower decoding complexity.Since the nineties in last century; The world has got into information-based, digitlization Rapid development stage; Various communication systems constantly occur; Like the IEEE 802.11n (WLAN) and the IEEE 802.16e (WiMAX) in broadband wireless access field, the European DTV satellite transmits standard (DVB-S2) in DMB field, China Digital TV ground transmission standard (DTMB) and be applicable to China Mobile multimedia broadcasting standard (CMMB) of handheld mobile device etc.Because the outstanding performance of LDPC sign indicating number, most communication standards have all adopted the LDPC sign indicating number as its forward error correction.
LDPC is divided into two kinds with regard to its structure: structuring and destructuring LDPC sign indicating number.It is great in one submatrix that its difference is whether to contain in the check matrix row.LDPC sign indicating number among structurized LDPC sign indicating number such as DTMB and the IEEE 802.16m does not comprise this type submatrix in its check matrix, then comprise this type submatrix among non-structured LDPC sign indicating number such as CMMB and the DVB-S2.
The decoding algorithm of LDPC mainly contains two kinds: TPMP (Two Phase Message Passing) algorithm or TDMP (Turbo Decoding Message Passing) algorithm.The difference of two types of algorithms is ranks, and more new sequences is different.In the TPMP algorithm, all row and leu preface are upgraded, and just carry out the renewal of column or row after promptly all row or row upgrade and are over.And the way of TDMP algorithm to be row and the leu preface of part upgrade, the row that normally carries out a certain layer earlier upgrades, then the related row renewal of the row of layer therewith.Generally speaking, TDMP convergence of algorithm speed is faster, and storage resources takies also still less.But TDMP will run into the problem of data collision when handling destructuring LDPC, the induced loss of energy, especially in the check matrix of LDPC row great in one submatrix number more for a long time.
Owing to need use different communication standard in different occasions in people's daily life, people use usually needs different equipment to meet the different needs, very inconvenient.A kind of trend of following hardware designs is restructuralization for this reason, promptly same hardware configurable to different mode to satisfy different needs.So ldpc decoder also should be supported various standard, and because the difference of LDPC structure makes classical efficiently TDMP algorithm can not be applied to the decoding of destructuring LDPC sign indicating number.And there are some difference between destructuring and the structurized LDPC sign indicating number, make configurable decoder on hardware is realized, have certain degree of difficulty.
Summary of the invention
The object of the present invention is to provide a kind of algorithm the convergence speed fast, ldpc decoder structure and decoding algorithm that hardware availability ratio is high.
The ldpc decoder that the present invention proposes adopts general serial process mode, and LDPC decoding algorithm and hardware structure has all been carried out special optimization, makes ldpc decoder compatible structureization and destructuring LDPC sign indicating number fully.The TDMP optimization Algorithm has improved the algorithm the convergence speed of configurable ldpc decoder, the optimization and improvement of the storage policy of ldpc decoder, main sequential and processing unit the hardware availability ratio of decoder.
One, decoding algorithm
Shown in accompanying drawing 1 (a), each LDPC sign indicating number is all defined by the parity matrix of a M x N.Each row is represented a check-node, and each row is represented an information node.The check matrix major part all is 0, and on behalf of corresponding information node and check-node, each 1 on Tanner schemes, annexation is arranged, shown in accompanying drawing 1 (b).
The present invention proposes
Decoding algorithmConcrete steps following:
(1) initialization
(2) precedingly test information updating
A. the row when submatrix heavily is for the moment:
B. when the row of submatrix heavily was two, when carrying out formula (2), information of extra generation was suc as formula shown in (3):
(3) external information is upgraded:
（4）
(4) posterior information is upgraded
A. the row when submatrix heavily is for the moment, then upgrades by formula (5) institute formula:
B. when the row of submatrix heavily is two, then upgrade by formula (6) and (7) institute formula:
(5) repeating step (2) and step (4) are all accomplished renewal up to all layers;
(6) hard decision
(7) when reaching maximum iteration time or
; Accomplish iteration; And output
, otherwise k add 1 and repeating step (2) to step (6);
Wherein,
is the intrinsic information through information node V behind the channel; The posterior information that
is information node V in the k time iteration;
is check-node C to the external information of information node V in the k time iteration;
information node V tests information before check-node C is in the k time iteration;
is normalization factor;
is the set that all and check-node C have the information node of annexation;
is the set that all and information node V have the check-node of annexation;
is to remove symbol,
to be information node V in the k time iteration declare the result firmly.
As comparing, based on normalization the least factor algorithm, classical TDMP algorithm can be expressed as:
1) initialization
2) check-node upgrades
（10）
3) information node upgrades:
4) repeating step 2) and step 3) all accomplish renewal up to all layers;
5) hard decision
6) when reaching maximum iteration time or
; Accomplish iteration; And output
, otherwise k add 1 and repeating step 2) to step 6).
Classical TDMP algorithm can run into the data collision problem when decoding destructuring LDPC.As when deciphering like accompanying drawing 1 (a); When lastest imformation node
, two posterior informations will take place suc as formula shown in (14) and (15) according to formula (10).And because decoder adopts is serial structure, one of them value will be replaced by another value, causes the loss of information, finally causes the loss of decoding performance.
In order to address this problem; Application number is to have adopted the SIMD structure to support TPMP algorithm and TDMP algorithm simultaneously in " a kind of multi-standard LDPC encoder circuit based on the SIMD structure " technical scheme of 200910054350; When the non-structured LDPC sign indicating number of decoding, select the TPMP algorithm for use, to avoid this data collision problem.But reduced the degree of convergence like this, with the power consumption that increases hardware, and owing to adopt the SIMD structure, hardware need be supported various instructions, will consume the additional hardware resource.The present invention adjusts the TDMP algorithm of classics for this reason.When carrying out the external information renewal, still undertaken by formula (10) and (11); But when before carrying out, testing information updating by information of extra generation shown in the formula (3)
; For the LDPC sign indicating number shown in accompanying drawing 1 (a), its result is suc as formula shown in (16).Then carry out posterior information when upgrading suc as formula shown in (6) and the formula (7).For the LDPC sign indicating number shown in accompanying drawing 1 (a), just its result is suc as formula shown in (17) and (18).
（17）
Optimization of the present invention makes TDMP can effectively decipher non-structured LDPC sign indicating number; In order to verify feasibility of the present invention; We verify that based on the LDPC sign indicating number of CMMB and DTMB accompanying drawing 2 has shown the error rate (Bit Error Ratio, BER) contrast of curve and traditional algorithm.AWGN (Additive White Gaussian Noise) channel and BPSK (Binary Phase Shift Keying) modulation system have all been adopted in all emulation.Normalization factor is 0.75, in fixed point emulation posterior information with before test information and be quantified as 8 bits, external information is quantified as 6 bits.Algorithm wherein of the present invention has only used iteration 15 times, and classical algorithm has used iteration 25 times.No matter from figure, can see, be in floating-point or fixed-point simulation, and the performance of algorithm of the present invention all is higher than classical TDMP algorithm.
Two, decoder architecture
In order to show decoder architecture of the present invention, the present invention has designed a decoder with CMMB and DTMB standard for example, and its main block diagram is shown in accompanying drawing 3.This decoder by master controller, posterior information memory module, precedingly test information storage module, recovery and accumulation process unit, external information memory module, normalization processing unit, configurable shifting processing unit and parity check and output module is formed; Wherein:
(1) said master controller is made up of some logical circuits, is used to realize the controlled function of whole decoder, mainly comprises the control of input and output, the coordination of each module etc.
(2) said posterior information memory module; Form by two memory blocks and a local controller; Be responsible for reading and writing of posterior information, comprise input suc as formula the intrinsic information shown in (1), carry out suc as formula the corresponding posterior information before testing information updating before shown in (2) read and accomplish suc as formula (5) or formula (7) suc as formula after the writing of the intact posterior information of renewal.
(3) test information storage module before said; Form by some memories and a local controller, be responsible for accomplishing suc as formula the storage of testing information before (2) or (3) renewal and before the posterior information renewal of carrying out suc as formula (5) or formula (6) and read testing information before corresponding.
(4) the renewal operation suc as formula (2), (3), (5), (6) and (7) is responsible for accomplishing in said recovery and accumulation process unit, its structure shown in accompanying drawing 4.
(5) said external information memory module; Form by some memories and a local controller; Be responsible for to accomplish suc as formula before (2), (3), (5), (6) and (7) said operation to the reading of corresponding external information, accomplish writing suc as formula the corresponding external information after the external information renewal of (4).Its read-write sequence is shown in accompanying drawing 5.
(6) said normalization processing unit, its structure shown in accompanying drawing (6), be responsible for from recover with the accumulation process unit read after the renewal before test information, accomplish then to upgrade and operate suc as formula the external information shown in (4).
(7) said configurable shifting processing unit, its structure are responsible for when handling submatrix corresponding posterior information or the preceding cyclic shift of testing information shown in accompanying drawing (7).
(8) said parity check and output module are responsible for completing steps (6) and step (7), the i.e. output of hard decision, parity check and corresponding hard decision information.
The calculating of perfect (2), (3), (5), (6) and (7) is responsible in said recovery and accumulation process unit.Owing to adopt normalization minimum with (external information can divide minimum value, sub-minimum, minimum value position and all sign bits into for Normalized Min Sum, NMS) algorithm.Therefore when carrying out algorithm computation, traditional way is that the numeral that these values revert to a complement form is carried out the calculating suc as formula (2), (3), (5), (6) and (7) again.But this recovery is with as broad as long with the exchange of the addition and subtraction in the formula, and in order to reduce the consumption of hardware resource, the decoder among the present invention has only adopted a kind of accumulator, and supports addition and subtraction.
For this reason in decoder of the present invention; The recovery of external information is carried out with before testing in the same processing unit of being updated in of information and posterior information; Its structure is shown in accompanying drawing 4; Be made up of some selectors, comparator, XOR unit, finite field adder, it is input as minimum value, sub-minimum, outer information symbol, minimum value index and current index.Selector extracts symbol according to current index value from outer information symbol.When current index was identical with the minimum value index, absolute value was got sub-minimum, did not then get minimum value simultaneously.When sign bit and computation schema Cal_mode (1 is subtraction, and 0 is addition) not simultaneously, when promptly deducting a negative or adding a positive number, signal Hsub_Ladd will be 0, signal temp will take absolute value, the finite field adder will be accomplished normal add operation.And sign bit is when identical with computation schema Cal_mode, and in the time of promptly will subtracting a positive number or add negative, signal Hsub_Ladd will be 1, and signal temp will be the step-by-step inverted value of absolute value, and the finite field adder will be accomplished subtraction.Decoder just can be operated the recovery of external information with before testing in the same processing unit of being updated in of information or posterior information like this, has saved the use of hardware, has improved hardware efficiency and can reduce power consumption.
Said normalization processing unitBe responsible for the calculating of perfect (4), its structure is made up of absolute value device, multiplier, overflow check module and two comparators shown in accompanying drawing 6.Current test information and accomplish renewal suc as formula (2) after, just be passed to this module.Test the absolute value of information before obtaining earlier, and then be multiplied by normalization factor
.Because before testing information is 8, its absolute value is 7, and external information has only 6, and its absolute value is 5, so taking advantage of after normalization factor, still need carry out overflow check, so that cut position is arrived the needed bit wide of external information.Be that the value behind the cut position is compared with current minimum value earlier at last, wherein minimum value is as the output minimum value, and sub-minimum is wherein then done comparison with current sub-minimum, and wherein minimum value is as the output sub-minimum.
Said configurable cyclic shifterThe configurable cyclic shift network of employing shown in accompanying drawing 7 adopted three grades of flowing water semi-parallel architectures, and each level all is made up of some selectors, is responsible for the displacement of a location number respectively.Because the submatrix of LDPC check matrix is a cyclic shift matrix; And the storage of external information is carried out according to natural order; So when before carrying out, testing the renewal of information or posterior information; Need corresponding posterior information or the preceding information of testing be carried out certain displacement ability with external information is corresponding one by one accordingly, so need cyclic shifter.Because the LDPC numeral matrix size of various criterion is different, and the cyclic shift ordinal number of submatrix is different, and cyclic shifter need be supported different widths and displacement ordinal number, so this shift unit must be configurable.
Configurable cyclic shift network of the present invention has adopted three grades of flowing water semi-parallel architectures.Its displacement width can be arranged to different value according to the standard of decoding, realizes the configurable of width.Approve of in right shift P-m position to the m position that moves to left, so cyclic shifter can only be supported a direction.And displacement ordinal number offset is divided into three parts: offset [2:0], offset [5:3], offset [7:6] originally as 8.The first order is responsible for being shifted a=offset [2:0], and the second level is responsible for being shifted b=8 x offset [2:0], and afterbody is responsible for being shifted c=64 x offset [2:0].
Description of drawings
Fig. 1 LDPC check matrix sketch map.
Fig. 2 algorithm performance comparison diagram.
Fig. 3 decoder overall construction drawing.
Fig. 4 recovers and the accumulator module sketch map.
Fig. 5 external information storage sequential chart.
Fig. 6 normalization processing unit structure chart.
The configurable cyclic shifter of Fig. 7.
Fig. 8 is capable, and sketch map divided in great submatrix in.
Fig. 9 master's sequential chart.
Figure 10 decoder rear end domain.
Embodiment
According to the solution that provides in the summary of the invention, adopt classical TDMP algorithm during with decoding architecture LDPC sign indicating number, when decoding destructuring LDPC sign indicating number, adopted of the present invention through adjusted TDMP decoding algorithm.The present invention has also optimized the external information storage policy.Down outer will introduce respectively external information storage policy of the present invention, main sequential and with the comparison of other decoders.
The external information storage policy
Usually decoder can be accomplished the read-write operation of the external information of certain one deck in one-period, but the check matrix structure before the different code checks of various criterion is different.Subordinate list 1 has been listed the major parameter of CMMB and DTMB China and foreign countries information stores.If adopt traditional storage policy, relevant parameter need adopt each code check maximum before so, is 36 x, 128 x 42=193,536 bits.This will greatly waste memory space.
The present invention is divided into several cycles with the storage of external information for this reason, and each external information is only handled some bits in phase weekly, and sequential chart is shown in accompanying drawing 5.When CMMB code check 1/2 and DTMB code check 2/5, need three cycles like this, need four cycles when CMMB code check 3/4 and DTMB code check 3/5, need 6 cycles during DTMB code check 4/5.The degree of depth of memory will be taken advantage of in the required cycle for the number of plies like this, and maximum is 36 x 3=108.The bit of each period treatment is 7 x 128=896.The memory space that needs altogether is 108x896=96, and 768 bits are merely the half the of conventional store strategy.
Decipher main sequential
About the check matrix of CMMB, can provide 2 statements: it is great in one submatrix 1) only possibly to contain a row in certain one deck; 2) going great submatrix in can be divided into a standard cell battle array and a cyclic shift matrix.The check matrix of accompanying drawing 1 has similar characteristics, and it can be divided into the submatrix shown in the accompanying drawing 8, and wherein submatrix 0 is shared identical posterior information with submatrix 1.To be that example is explained the main sequential of decoding of the present invention with the LDPC sign indicating number shown in the accompanying drawing 1 below.
Great during in one submatrix when going in the layer, like the LDPC among the DTMB, then hardware is operated by the TDMP algorithm of classics, and its main sequential is shown in the accompanying drawing 9 (a).
When 1, before carrying out, testing the renewal of information and external information; Decoder at first reads corresponding posterior information from the posterior information memory module (the reading and write of external information is divided into several cycles; In accompanying drawing 9, do not show), and from Hrom, read out corresponding displacement ordinal number.Configurable then cyclic shifter will be accomplished the displacement to posterior information.After displacement is accomplished, recovery and accumulation process unit will read the posterior information after the displacement, and accomplish and before shown in (2), test information updating.Last normalization processing unit will read after the renewal before test information and accomplish suc as formula the external information shown in (4) and upgrade, test before after meanwhile upgrading and test information storage module before information will be deposited in.
2, when carrying out the posterior information renewal, decoder will be tested information before will testing at first in the past and reading out accordingly in the information storage module.The information of testing before recovery and accumulation process unit will read then will be accomplished suc as formula the posterior information shown in (5) and upgrade.Posterior information after the renewal will be shifted back original order in configurable cyclic shift network.Last corresponding posterior information will be deposited in the posterior information memory module.
When there being row great during in one submatrix in the layer, like the LDPC among the CMMB, then hardware is operated by the modified model TDMP algorithm shown in the right one, and its main sequential is shown in the accompanying drawing 9 (b).
When 3, before carrying out, testing the renewal of information and external information, the operation of submatrix 1 is the same with the operation of the submatrix 0 shown in Fig. 9 (a).And decoder can clock once can accomplish antithetical phrase 0 before test information updating, and need not pass through cyclic shift, because submatrix 0 is a standard cell battle array.At clock two, test information before the submatrix 0 and will in configurable circular shift module, accomplish displacement then.Then at clock three, recover with the accumulation process unit will according to test before the submatrix 0 after the displacement information completion suc as formula shown in (16) to the generation of extraneous information
.
will test information stores to preceding testing in the information storage module before clock four is treated as at last.
4, when carrying out the posterior information renewal, decoder will be tested at first in the past and read out extraneous information
in the information storage module.Then at clock 6, recover and the accumulation process unit will read
will accomplish the generation suc as formula
shown in (17).At clock 7,
will be moved back to normal sequence in configurable cyclic shifter.Then at clock 8,
that recovery and accumulation process unit will read after the displacement accomplishes suc as formula the renewal to posterior information
shown in (18).Last corresponding posterior information will be deposited in the posterior information memory module.
In above-mentioned embodiment; Adopt adjusted algorithm provided by the invention, decoder can use same hardware cell to accomplish the decoding of structuring and destructuring LDPC, does not need extra processing unit; Save hardware resource, improved hardware availability ratio.And can realize configurableization of decoder, improve the flexibility of decoder.
The result relatively
In order to verify the present invention program's efficient, based on the SMIC0.13um standard CMOS process, we have designed the ldpc decoder of all code checks of a support destructuring CMMB and structuring DTMB.Its rear end domain is shown in accompanying drawing 10.The kernel area of this decoder is 2.16x2.20mm
2. maximum operating frequency can reach 200MHz, and maximum gulps down rate can reach 365.7Mbps.Under 5 iterated conditionals, the back imitative power consumption of chip is that 48.4mW is when being operated in 25MHz and CMMB standard, when 130.9mW is operated in 50MHz and DTMB standard.Subordinate list 2 has compared the hardware result of decoder of the present invention and some documents; From table, can find out; Of the present invention can the completion supports the ldpc decoder of CMMB and DTMB to have the littler chip area of ldpc decoder of supporting single standard (CMMB or DTMB) than other, this shows the high efficiency of decoder of the present invention.
The major parameter of the external information storage of table 1 CMMB and DTMB
The ratio of table 2 decoder of the present invention and other decoders
With reference to selected works:
[1]Kai?Zhang,?Xinming?Huang,?Zhongfeng?Wang,?"An?Area-Efficient?LDPC?Decoder?Architecture?and?Implementation?for?CMMB?Systems",?in?PROC.IEEE?ASAP,?pp.?235-238,July.?2009.
[2]Kai?Zhang,?Xinming?Huang,?Zhongfeng?Wang,?"A?dual-rate?LDPC?decoder?for?china?multimedia?mobile?broadcasting?systems",?IEEE?Transactions?on?Consumer?Electronices,?vol.?56,?pp.?399-407,?May.?2010
[3]Bo?Xiang,?Rui?Shen?,?An?pan,?Dan?Bao,?Xiaoyang?Zeng,?"An?Area-Efficient?and?Low-Power?Multirate?Decoder?for?Quasi-Cyclic?Low-Density?Parity-Check?Codes",?IEEE?Transactions?on?Very?Large?Scale?Integration?(VLSI)?Systems?,vol.18,?pp.?1447-1460,?Oct.?2010
[4]M.?M.?Mansour?and?N.?R.?Shanbhag,?"A?640-Mb/s?2048-bit?programmable?LDPC?decoder?chip,"?IEEE?J.?Solid-State?Circuits,?vol.?41,?pp.?634-698,?March.?2006。
Claims (2)
1. a follow-on TDMP algorithm is characterized in that carrying out special processing to non-structured LDPC sign indicating number, and its concrete steps are following:
(1) initialization:
(2) precedingly test information updating:
When the row of submatrix heavily is for the moment:
When the row of submatrix heavily was two, when carrying out formula (2), information of extra generation was suc as formula shown in (3):
（3）
(3) external information is upgraded:
(4) posterior information is upgraded
When the row of submatrix heavily is for the moment, then upgrade by formula (5) institute formula:
When the row of submatrix heavily is two, then upgrade by formula (6) and (7) institute formula:
(5) repeating step (2) and step (4) are all accomplished renewal up to all layers;
(6) hard decision
（8）
(7) when reaching maximum iteration time or
; Accomplish iteration; And output
, otherwise k add 1 and repeating step (2) to step (6);
Wherein,
is the intrinsic information through information node V behind the channel; The posterior information that
is information node V in the k time iteration;
is check-node C to the external information of information node V in the k time iteration;
information node V tests information before check-node C is in the k time iteration;
is normalization factor;
is the set that all and check-node C have the information node of annexation;
is the set that all and information node V have the check-node of annexation;
is to remove symbol,
to be information node V in the k time iteration declare the result firmly.
2. one kind based on the compatible structureization of the described modified model TDMP of claim 1 algorithm and the decoder of destructuring LDPC sign indicating number, it is characterized in that by master controller, posterior information memory module, precedingly tests information storage module, recovery and accumulation process unit, external information memory module, normalization processing unit, configurable shifting processing unit and parity check and output module is formed; Wherein:
(1) said master controller is made up of some logical circuits, is used to realize the controlled function of whole decoder, mainly comprises the control of input and output, the coordination of each module;
(2) said posterior information memory module; Form by two memory blocks and a local controller; Be responsible for reading and writing of posterior information, comprise the intrinsic information shown in the formula (1) input, carry out shown in the formula (2) before reading of corresponding posterior information
and writing of posterior information that renewal after perfect (5) or formula (7) is intact before testing information updating;
(3) test information storage module before said; Be made up of some memories and a local controller, the storage of testing information before responsible perfect (2) or formula (3) renewal reaches before the posterior information of carrying out formula (5) or formula (6) is upgraded reads testing information before corresponding;
(4) the renewal operation of perfect (2), (3), (5), (6) and (7) is responsible in said recovery and accumulation process unit;
(5) said external information memory module; Form by some memories and a local controller; Be responsible for to accomplish suc as formula before (2), (3), (5), (6) and (7) said operation to the reading of corresponding external information, the writing of the corresponding external information after the external information renewal of perfect (4);
(6) said normalization processing unit, be responsible for from recover with the accumulation process unit read after the renewal before test information, the external information shown in the perfect (4) is upgraded and is operated then;
(7) said configurable shifting processing unit is responsible for when handling submatrix corresponding posterior information or the preceding cyclic shift of testing information;
(8) said parity check and output module are responsible for accomplishing step (6) and step (7), the i.e. output of hard decision, parity check and corresponding hard decision information of said method.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108337070A (en) * | 2018-03-21 | 2018-07-27 | 上海交通大学 | A kind of LDPC code channel decoder and its coding/decoding method |
| CN111384970A (en) * | 2018-12-29 | 2020-07-07 | 电信科学技术研究院有限公司 | Decoding method, device and communication equipment |
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