CN102623385A - Manufacturing method of three-dimensional array grid-last type Si-NWFET (Nanowire Field Effect Transistor) based on SOI (Silicon On Insulator) - Google Patents

Manufacturing method of three-dimensional array grid-last type Si-NWFET (Nanowire Field Effect Transistor) based on SOI (Silicon On Insulator) Download PDF

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CN102623385A
CN102623385A CN2012100941932A CN201210094193A CN102623385A CN 102623385 A CN102623385 A CN 102623385A CN 2012100941932 A CN2012100941932 A CN 2012100941932A CN 201210094193 A CN201210094193 A CN 201210094193A CN 102623385 A CN102623385 A CN 102623385A
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silicon
layer
grid
soi
nwfet
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黄晓橹
刘格致
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Shanghai Huali Microelectronics Corp
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Shanghai Huali Microelectronics Corp
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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y40/00—Manufacture or treatment of nanostructures
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H01L29/0669—Nanowires or nanotubes
    • H01L29/0673—Nanowires or nanotubes oriented parallel to a substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H01L29/42392—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor fully surrounding the channel, e.g. gate-all-around
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66439—Unipolar field-effect transistors with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/775—Field effect transistors with one dimensional charge carrier gas channel, e.g. quantum wire FET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel

Abstract

The invention discloses a manufacturing method of a three-dimensional array grid-last type Si-NWFET (Silicon-Nanowire Field Effect Transistor) based on an SOI (Silicon On Insulator). The manufacturing method comprises the following steps of: alternatively growing silicon layers and germanium-silicon layers on the SOI, forming a fin-shaped active region, forming silicon nanowires in the fin-shaped active region, depositing amorphous carbon in a groove as a virtual isolating layer, then carrying out a grid-last process, and finally and simultaneously carrying out deposition on a groove isolating medium and an interlayer isolating medium. The manufacturing method disclosed by the invention has the advantages that due to existence of an oxygen embedding layer in the SOI, the isolating effect between a grid and an SOI substrate is effectively improved, and the adoption of the grid-last process is beneficial to the control of the profile of the grid and the electrical property of a device; the utilization of the amorphous carbon as the virtual isolating layer is beneficial to the control of the profiles of the grid and the grid groove; and in addition, the silicon-nanowire field effect transistor (Si-NWFET) structure is designed by adopting a three-dimensional array silicon-nanowire structure, so that the number of the nanowires is increased, and the current driving capability of the device is improved.

Description

Based on grid type Si-NWFET manufacturing approach behind the SOI three-dimensional array type
Technical field
The present invention relates to integrated circuit and make the field, particularly a kind of based on grid type Si-NWFET manufacturing approach behind the SOI three-dimensional array type.
Background technology
Through dwindle transistorized size improve chip operating rate and integrated level, to reduce chip power-consumption density be the target that microelectronics industry development is pursued always.In in the past 40 years, Moore's Law is being followed in the microelectronics industry development always.Current; The physical gate of field-effect transistor is long near 20nm; Gate medium also only has the thickness of several oxygen atomic layers; Improve performance through the size of dwindling conventional field effect transistor and faced some difficulties, this mainly is to have destroyed transistorized switch performance because of short-channel effect under the small size and grid leakage current.
Nano-wire field effect transistor (NWFET, Nano-Wire MOSFET) is expected to solve the problem of short-channel effect and grid leakage current.On the one hand; Channel thickness among the NWFET and width are all less, make grid more approach the various piece of raceway groove, help enhance transistor grid modulation capability; And most of transistors all adopt and enclose the grid structure; Grid is modulated raceway groove from a plurality of directions, has further strengthened the modulation capability of grid, improves the subthreshold value characteristic.Therefore, NWFET can suppress short-channel effect well, makes transistor size be able to further dwindle.On the other hand, NWFET utilizes the rill road of self and encloses the grid structure and improve the grid modulation forces and suppress short-channel effect, has alleviated the requirement of attenuate grid medium thickness, is expected to reduce grid leakage current.In addition, nanowire channel can undope, and has reduced impurity discrete distribution and Coulomb scattering in the raceway groove.For the 1-dimention nano wire channel, because quantum limitation effect, charge carrier so carrier transport receives surface scattering and channel laterally influence little, can obtain higher mobility away from surface distributed in the raceway groove.Based on above advantage, NWFET more and more receives scientific research personnel's concern.Because Si material and technology are occupied dominant position in semi-conductor industry, compare the easier and current process compatible of the making of silicon nanowires field-effect transistor (Si-NWFET) with other materials.
The critical process of NWFET is the making of nano wire, can be divided into from top to bottom and two kinds of process routes from bottom to top.For the making of Si nano wire, top-down making mainly utilizes photoetching and etching technics, and making from bottom to top is mainly based on the gas-liquid-solid growth mechanism of metal catalytic, in the growth course with catalyst granules as nucleating point.At present, the silicon nanowires of process route preparation from bottom to top not too is fit to the preparation of Si-NWFET owing to its randomness, and the Si-NW in the therefore present silicon nanowires field-effect transistor mainly is through top-down process route preparation.
At present; Field-effect transistor (MOSFET) its preparation process research based on single silicon nanowires is relatively more popular; To be 200710098812.4 disclosure of the Invention like application number a kind of based on the process that approach from top to bottom realizes the bulk silicon nano line structure of passing through of body silicon, effectively suppressed the self-heating effect of device.And a kind of MOSFET preparation method based on silicon nanowires is disclosed in the paper " Fabrication and Characterization of Gate-All-Around Silicon Nanowires on Bulk Silicon "; But along with dwindling of silicon nanowires sectional area; The current driving ability of device can receive the restriction of nano wire sectional area; Make the application of Si-NWFET in simulation or radio circuit be restricted; Therefore, the someone begins one's study and adopts many nano wires as transporting raceway groove, to address this problem.
People such as W.W.Fang are at IEEE ELECTRON DEVICE LETTERS; VOL.28; NO.3 has proposed a kind of vertical method for preparing silicon nanowires in the paper of delivering on the MARCH 2007 " Vertically Stacked SiGe Nanowire Array Channel CMOS Transistors ", makes the silicon nanowires FET device at vertical integrated many silicon nanowires; Thereby make the current driving ability of device increase exponentially, integration density is unaffected simultaneously.Not only can keep the advantage of planar structure field-effect transistor (FET) but also strengthened the grid modulation capability.Its process is to go up alternately growth (Ge/Si Ge)/Si/ (Ge/SiGe)/Si layer at SOI (Silicon on Insulator); And define fin-shaped (Fin) structure above that; Carry out 750 ℃ of dry-oxygen oxidations then; Because the SiGe layer has faster oxidation rate so that SiGe layer oxidized fully than the Si layer, Ge gets into contiguous Si laminar surface and forms the SiGe alloy in the oxidizing process, erodes and obtains three-dimensional pile up, Si nano wire that the surface is wrapped with the SiGe alloy behind the oxidized fully SiGe layer.Carry out thermal oxidation then, form Si on silicon nanowires (SiNW) surface 1-XGe XO 2As grid oxic horizon, unformed silicon of deposit or polysilicon form grid through photoetching and etching at last again.This method can realize vertical stack type silicon nanowires field-effect transistor structure, but has a shortcoming: in SiGe layer oxidizing process, Ge can be concentrated to the surface of Si layer, behind the removal SiO2, is wrapped with the SiGe alloy after one deck concentrates at surface of silicon nanowires.Because GeO2 is water-soluble, it makes subsequent technique face huge inconvenience, and in addition, the dielectric constant of GeO2 is little than SiO2, and the interfacial state of GeO2 and Si is bigger, is not suitable for the gate oxide as field-effect transistor (FET).
Summary of the invention
It is a kind of based on grid type Si-NWFET manufacturing approach after the SOI vertical stack formula that the present invention provides; Be convenient to device electrically, the profile control of grid and gate trench; And make in the device isolation effect of grid and SOI substrate better, realize the conventional grid oxic horizon structure of silicon nanowires field-effect transistor simultaneously.
For solving the problems of the technologies described above, it is a kind of based on grid type Si-NWFET manufacturing approach behind the SOI three-dimensional array type that the present invention provides, and comprising: SOI is provided substrate, and said SOI substrate is followed successively by end silicon layer from bottom to top, insulator layer and top layer silicon;
Said SOI substrate is handled, said top layer silicon is converted into initial germanium silicon layer;
At said initial silicon germanium layer surface alternating growth silicon layer and follow-up germanium silicon layer, said initial germanium silicon layer and said follow-up germanium silicon layer constitute the germanium silicon layer jointly;
Said germanium silicon layer and silicon layer are carried out etching, form the fin-shaped active area;
In the fin-shaped active area, form silicon nanowires, said silicon nanowires three-dimensional array type vertical stack;
Form amorphous carbon in the raceway groove on said SOI substrate and carry out injection of source-drain area ion and annealing process;
Form grid oxic horizon on said SOI substrate, silicon nanowires and source-drain area surface;
On said SOI substrate, form grid;
Form alloy-layer at said grid and source-drain area surface;
Remove said amorphous carbon, in said raceway groove, fill the spacer medium layer, carry out the zone isolation dielectric deposition simultaneously.
Preferable, said SOI substrate surface to be handled, the concrete operations that said SOI substrate top layer silicon is converted into the germanium silicon layer are:
Deposit a germanium layer at said SOI substrate surface;
To said germanium layer oxidation processes, the germanium oxidation concentrates the silicon shape with said SOI substrate top layer in the said germanium layer
Become the germanium silicon layer, said germanium silicon surface is SiO 2Layer;
Wet method is removed said SiO 2Layer.
Preferable, said silicon layer is at least one deck, and said germanium silicon layer manys one deck than said silicon layer.
Preferable, after said silicon layer and germanium silicon layer alternating growth, carry out Si-NWFET device channel ion and inject.
Preferable, said silicon nanowires diameter is between 1 nanometer～1 micron.
Preferable, the cross sectional shape of said silicon nanowires is circular, horizontal track shape or vertical track shape.
Preferable, before forming grid oxic horizon on said silicon nanowires, SOI substrate and the source-drain area, also comprise: said silicon nanowires is carried out thermal oxidation; Etch away the silicon dioxide that said thermal oxidation forms.
Preferable, the material of said grid oxic horizon is silicon dioxide, silicon oxynitride or high K medium.
Preferable, said high K medium is HfO 2, Al 2O 3, ZrO 2In a kind of or its combination in any.
Preferable, the material of said grid is a polysilicon, amorphous silicon, the combination in any of metal or said polysilicon, unformed silicon and metal.
Preferable, said spacer medium is a silicon dioxide.
Preferable, said etching adopts time normal pressure chemical gas phase etching method.
Preferable, said time normal pressure chemical gas phase etching method adopts hydrogen and chlorine hydride mixed gas body, and wherein the temperature of hydrogen and chlorine hydride mixed gas body is between 600 ℃～800 ℃, and wherein the dividing potential drop of hydrogen chloride is greater than 300Torr.
Compared with prior art, compared with prior art, grid type silicon nanowires field-effect transistor structure has the following advantages behind the three-dimensional array type of the present invention:
1, based on the SOI substrate, because the existence of insulator layer (for example being oxygen buried layer) in the SOI substrate has effectively increased the isolation effect between grid and the SOI substrate;
2, on silicon nanowires, forming the gate oxidation layer process is independently to carry out, thereby can adopt conventional grid oxic horizon, gets final product like silicon dioxide;
3, being formed on after injection of source-drain area ion and the annealing process step of grid is the back grid technology, is beneficial to the electrical control of gate profile and device;
4, at first in raceway groove, form amorphous carbon; Then carry out the back grid technology; After accomplishing, removes back grid technology amorphous carbon; Promptly adopt amorphous carbon as the virtual separator of back in the grid technology,, be beneficial to the control of grid and gate trench profile because amorphous carbon has high etching selection ratio and high absorptive and is easy to ashing;
5, carry out channel isolation medium and zone isolation dielectric deposition simultaneously, simplify technology;
6, adopt the three-dimensional array type silicon nanowire structure to come design of Si nano-wire field effect transistor (SiNWFET) structure, the nanometer number of lines increases, and the device current driving force increases.
Description of drawings
Fig. 1 for SOI substrate X-X ' in the present invention's one specific embodiment to generalized section;
Fig. 2 for deposition germanium layer or germanium silicon layer in the present invention's one specific embodiment after X-X ' to generalized section;
Fig. 3 for germanium layer in the present invention's one specific embodiment or the oxidation of germanium silicon layer after X-X ' to generalized section;
Fig. 4 for X-X ' after removing silicon dioxide in the present invention's one specific embodiment to generalized section;
Fig. 5 for alternating deposit silicon layer in the present invention's one specific embodiment and germanium silicon layer after X-X ' to generalized section;
Fig. 6 when raceway groove being carried out ion implantation technology in the present invention's one specific embodiment X-X ' to generalized section;
Fig. 7 is for forming Y-Y ' behind the fin-shaped active area in the present invention's one specific embodiment to generalized section;
Fig. 8 A～8B be respectively X-X ' that etching in the present invention's one specific embodiment removes device behind the germanium silicon layer to and Y-Y ' to generalized section;
Fig. 8 C is for forming the schematic perspective view of device behind the silicon nanowires in the present invention's one specific embodiment;
Fig. 9 is silicon nanowires cross sectional shape sketch map in the present invention's one specific embodiment;
Figure 10 A～10B for deposition amorphous carbon in the present invention's one specific embodiment after the X-X ' of device to generalized section and stereogram;
Figure 11 A～11B be respectively in the present invention's one specific embodiment remove behind the unnecessary amorphous carbon device X-X ' to and Y-Y ' to generalized section;
Device X-X ' was to generalized section when Figure 12 injected for carrying out the source-drain area ion in the present invention's one specific embodiment;
Figure 13 A～13B be respectively in the present invention's one specific embodiment form behind the gate trench device X-X ' to and Y-Y ' to generalized section;
Figure 14 A～14B is respectively in the present invention's one specific embodiment behind the gate oxidation process device X-X ' to generalized section and perspective view;
Figure 15 A～15B be respectively in the present invention's one specific embodiment after the deposition of gate material device X-X ' to and Y-Y ' to generalized section;
Figure 16 A～16B be respectively in the present invention's one specific embodiment form behind the grid device X-X ' to and Y-Y ' to generalized section;
Figure 16 C is for forming device perspective view behind the grid in the present invention's one specific embodiment;
Figure 17 A～17C be respectively in the present invention's one specific embodiment accomplish after autoregistration silicon, germanium silicon metal alloy (Salicidation) technology device X-X ' to and Y-Y ' to generalized section, and schematic perspective view;
Figure 18 A～18B be respectively in the present invention's one specific embodiment remove behind the amorphous carbon device X-X ' to and Y-Y ' to generalized section;
Figure 18 C is for removing device perspective view behind the amorphous carbon in the present invention's one specific embodiment;
Figure 19 A～19B be respectively in the present invention's one specific embodiment behind the deposit medium X-X ' to and Y-Y ' to generalized section;
Figure 19 C for deposit medium in the present invention's one specific embodiment after the device perspective view;
Figure 20 A～20B be respectively in the present invention's one specific embodiment after the metal interconnected technology device X-X ' to and Y-Y ' to generalized section;
Figure 21 is silicon nanowires field-effect transistor perspective view in the present invention's one specific embodiment;
Figure 22 is silicon nanowires field-effect transistor schematic top plan view in the present invention's one specific embodiment.
Embodiment
For make above-mentioned purpose of the present invention, feature and advantage can be more obviously understandable, does detailed explanation below in conjunction with the accompanying drawing specific embodiments of the invention.
At first, shown in figure 22, for clearer description present embodiment, the length direction of the silicon nanowires of definition fin-shaped active area or follow-up formation is X-X ' to, X-X ' to running through grid and source-drain area, perpendicular to X-X ' to be Y-Y ' to.The manufacture method based on the three-dimensional array type Si-NWFET of body silicon below in conjunction with the detailed description one embodiment of the invention of Fig. 1 to 22 specifically comprises:
Please with reference to Fig. 1, SOI is provided substrate, the bottom of said SOI substrate is the silicon lining 11 that is used to provide mechanical support; It on the silicon lining 11 insulator layer; The present invention adopts oxygen buried layer (BOX) 12 as insulator layer, and oxygen buried layer 12 upper stratas are the top layer of SOI just, and top layer is a silicon layer 13.
Then, said SOI substrate surface is handled, the top layer of said SOI substrate is converted into initial germanium silicon layer 15 '; Specifically comprise: at first,, form a germanium layer 14 (germanium layer can be substituted by the germanium silicon layer) at the SOI substrate surface please with reference to Fig. 2; Then, please with reference to Fig. 3, the SOI substrate surface is carried out oxidation processes, germanium layer 14 forms initial germanium silicon layer 15 ' because oxidation concentrates to be seeped in the top layer, and the silicon of initial germanium silicon layer 15 ' upper surface is oxidized into silicon dioxide layer 16; Then, please with reference to Fig. 4, adopt wet etching to remove the silicon dioxide layer 16 of SOI substrate surface, at this moment, the top layer of SOI substrate is converted into initial germanium silicon layer 15 ' by silicon layer 13.
Please with reference to Fig. 5, on the SOI substrate, alternately form silicon layer 13 and follow-up germanium silicon layer 15 ", at first go up epitaxial growth silicon layer 13; the follow-up germanium silicon layer 15 of epitaxial growth again at initial germanium silicon layer 15 ' ", be convenient the description, with initial germanium silicon layer 15 ' and follow-up germanium silicon layer 15 " be referred to as germanium silicon layer 15; by that analogy, wherein the number of silicon layer 13 is at least one deck, and germanium silicon layer 15 is than silicon layer one deck more than 13; promptly, and the below is initial germanium silicon layer 15 ', the top be follow-up germanium silicon layer 15 ".The present invention is an example with three layers silicon layer 13.
Please with reference to Fig. 6; The SOI substrate channel region is carried out ion to be injected; Be specially: at first, on germanium silicon layer 15, carry out photoetching process, cover the zone of photoresist 20 in follow-up formation source electrode 203 (please with reference to Figure 22) and drain electrode 204 (please with reference to Figure 22); Then carry out ion and inject, remove the photoresist 20 on source electrode 203 and drain electrode 204 surfaces after ion injects and accomplishes.Need to prove that this step is an optional step, electrically require to omit under the permission situation according to device.
Please with reference to Fig. 7, to said germanium silicon layer 15 and silicon layer 13 etching processing, form fin-shaped active area 201 (please with reference to Figure 22), remaining areas is as source-drain area, i.e. source electrode 203 and drain electrode 204 zones; Optical lithography (Photolithography) or electron beam lithography (electron beam lithography) be can adopt, fin-shaped active area unnecessary germanium silicon layer 15 and silicon layer 13 etched away on every side, until exposing oxygen buried layer 12 surfaces.
Please, in said fin-shaped active area, form silicon nanowires 131, said silicon nanowires 131 three-dimensional array type vertical stacks with reference to Fig. 8 A～8C; Be specially; Selective etch is removed the germanium silicon layer 15 in the fin-shaped active area 201; Optional, utilize time normal pressure chemical gas phase etching method to carry out selective etch, can adopt H2 and HCL mist under 600～800 degrees centigrade; Wherein the dividing potential drop of HCL is greater than 300Torr, till the germanium silicon layer 15 of selective etch step in fin-shaped active area 201 all removed;
Then, oxidation is carried out on fin-shaped active area 201, SOI substrate and source-drain area surface, the controlled oxidation time, utilized wet processing to remove the SiO on fin-shaped active area 201, SOI substrate and source-drain area surface 2Thereby, form silicon nanowires 131 (please with reference to Fig. 8 C).Further, if described thermal oxidation is furnace oxidation (Furnace Oxidation), then the oxidization time scope is 1 minute to 20 hours; If rapid thermal oxidation (RTO), then the oxidization time scope is 1 second to 30 minutes.Remove the silicon dioxide that above-mentioned steps forms through wet processing on silicon nanowires 131 and oxygen buried layer 12 and source-drain area surface then.Silicon nanowires 131 diameters that form at last are between 1 nanometer～1 micron.
Because the thickness and fin-shaped active area 201 lateral dimensions of silicon layer 13 vary in size; The cross sectional shape of silicon nanowires 131 is also different; Please with reference to Fig. 9, the cross sectional shape of silicon nanowires 131 comprises circle 301, laterally track shape 302 and vertically track shape 303; Preferred cross-sections of the present invention is shaped as circular 301 silicon nanowires 131; Through more advanced figure transfer technology, can more accurately control fin-shaped active area (Fin) physical dimension, thereby more help the Shape optimization of silicon nanowires 131 and the diameter of accurately controlling silicon nanowires 131.
Please, form amorphous carbon 17 in the raceway groove on said SOI substrate and carry out injection of source-drain area ion and annealing process with reference to Figure 10 A～11B; Be specially: at first, please with reference to Figure 10 A～10B, at SOI substrate, source electrode 203 and 204 region surface that drain deposition agraphitic carbon 17; Then, please with reference to Figure 11 A～11B, utilize cmp (CMP) to remove source electrode 203 and the unnecessary agraphitic carbon 17 of drain electrode 204 region surface.
Need to prove that because the existence of amorphous carbon among the present invention, all correlation step from Figure 10 A to Figure 17 C can not occur all that dry method is removed photoresist and cineration technics, and need to adopt wet processing, with the pattern of protection amorphous carbon in this process.
Please with reference to Figure 12, source and drain areas is carried out ion inject, at first carry out photoetching process, photoresist 20 ' the covering source electrode 203 and 204 zones that drain are removed photoresist 20 ' and are carried out source-drain area annealing after ion injects and accomplishes with exterior portions.
Please with reference to Figure 13 A～13B, carry out photoetching, the unnecessary amorphous carbon 17 of selective etch removal, form gate trench, said gate trench is used for follow-up formation grid 201.
Please with reference to Figure 14 A～14B, SOI substrate in said fin-shaped active area 201 and silicon nanowires 131 surfaces form grid oxic horizon 18; What said grid oxic horizon 18 adopted is conventional grid oxic horizon material.Therefore, grid oxic horizon 18 can be for adopting the SiO of technique for atomic layer deposition (ALD) deposition 2, SiON (need be under the nitrogen atmosphere and could form) or high K medium (high dielectric radio medium), high K medium is HfO 2, Al 2O 3, ZrO 2In a kind of or its combination in any.Need to prove,, all be not suitable for the present invention like furnace oxidation, rapid thermal oxidation because the existence of amorphous carbon among the present invention can not adopt thermal oxidation technology to carry out the gate oxidation layer process.
Then, please with reference to Figure 15 A～16C, on said SOI substrate, form grid 202.Be specially: please with reference to Figure 15 A～15B; SOI substrate in gate trench and source-drain area surface deposition grid material 19; Please with reference to Figure 16 A～16C, cmp is removed the unnecessary grid material 19 in source-drain area surface, makes grid material and source-drain area upper surface be in same horizontal plane.
Please, carry out autoregistration alloy (S alicidation) technology, form silicon, germanium silicon metal alloy layer 21 at grid 202, source electrode 203 and 204 region surface that drain with reference to Figure 17 A～17C.
Please remove said amorphous carbon 17, carry out channel isolation medium and zone isolation dielectric deposition simultaneously with reference to Figure 18 A～20B.Be specially:
Please with reference to Figure 18 A～18C, cineration technics (Ashing) is removed amorphous carbon 17 in the raceway groove;
Please with reference to Figure 19 A～19C; SOI substrate in said raceway groove and alloy-layer surface deposition spacer medium 22; Because silicon alloy technology is accomplished; Therefore channel isolation medium and zone isolation dielectric deposition can be carried out simultaneously, and this also is the effect of amorphous carbon 17 as virtual separator, can simplify technology; Then spacer medium 22 is carried out planarization;
With reference to Figure 20 A～21, draw each port of CMOSFET through the metal interconnected technology in road, back at last, said port comprises drain electrode port 23, gate port 24 and source electrode port 25.
In sum, in conjunction with Figure 21～22, compared with prior art, grid type silicon nanowires field-effect transistor structure has the following advantages behind the three-dimensional array type of the present invention:
1, based on the SOI substrate, because the existence of insulator layer (for example being oxygen buried layer) in the SOI substrate has effectively increased the isolation effect between grid and the SOI substrate;
2, on silicon nanowires, forming the gate oxidation layer process is independently to carry out, thereby can adopt conventional grid oxic horizon, gets final product like silicon dioxide;
3, being formed on after injection of source-drain area ion and the annealing process step of grid is the back grid technology, is beneficial to the electrical control of gate profile and device;
4, at first in raceway groove, form amorphous carbon; Then carry out the back grid technology; After accomplishing, removes back grid technology amorphous carbon; Promptly adopt amorphous carbon as the virtual separator of back in the grid technology,, be beneficial to the control of grid and gate trench profile because amorphous carbon has high etching selection ratio and high absorptive and is easy to ashing;
5, carry out channel isolation medium and zone isolation dielectric deposition simultaneously, simplify technology;
6, adopt the three-dimensional array type silicon nanowire structure to come design of Si nano-wire field effect transistor (SiNWFET) structure, the nanometer number of lines increases, and the device current driving force increases.
Obviously, those skilled in the art can carry out various changes and modification to invention and not break away from the spirit and scope of the present invention.Like this, if of the present invention these revise and modification belongs within the scope of claim of the present invention and equivalent technologies thereof, then the present invention also is intended to comprise these change and modification.

Claims (13)

1. one kind based on grid type Si-NWFET manufacturing approach behind the SOI three-dimensional array type, it is characterized in that, comprising:
SOI is provided substrate, and said SOI substrate is followed successively by end silicon layer from bottom to top, insulator layer and top layer silicon;
Said SOI substrate is handled, said top layer silicon is converted into initial germanium silicon layer;
At said initial silicon germanium layer surface alternating growth silicon layer and follow-up germanium silicon layer, said initial germanium silicon layer and said follow-up germanium silicon layer constitute the germanium silicon layer jointly;
Said germanium silicon layer and silicon layer are carried out etching, form the fin-shaped active area;
In the fin-shaped active area, form silicon nanowires, said silicon nanowires three-dimensional array type vertical stack;
Form amorphous carbon in the raceway groove on said SOI substrate and carry out injection of source-drain area ion and annealing process;
SOI substrate in said fin-shaped active area and surface of silicon nanowires form grid oxic horizon;
On said SOI substrate, form grid;
Form alloy-layer at said grid and source-drain area surface;
Remove said amorphous carbon, carry out channel isolation medium and zone isolation dielectric deposition simultaneously.
2. as claimed in claim 1ly it is characterized in that based on grid type Si-NWFET manufacturing approach behind the SOI three-dimensional array type said SOI substrate surface is handled, and the step that said SOI substrate top layer silicon is converted into initial germanium silicon layer comprises:
Deposit a germanium layer or germanium silicon layer at said SOI substrate surface;
To said germanium layer or germanium silicon layer oxidation processes, in said germanium layer or the germanium silicon layer germanium oxidation concentrate with said SOI substrate top layer silicon in silicon form initial germanium silicon layer, the upper surface of said initial germanium silicon layer is SiO 2Layer;
Wet method is removed said SiO 2Layer.
3. as claimed in claim 1 based on grid type Si-NWFET manufacturing approach behind the SOI three-dimensional array type, it is characterized in that said silicon layer is at least one deck.
4. as claimed in claim 1ly it is characterized in that, after alternating growth silicon layer and the germanium silicon layer, carry out Si-NWFET device channel ion and inject based on grid type Si-NWFET manufacturing approach behind the SOI three-dimensional array type.
5. as claimed in claim 1ly it is characterized in that the diameter of said silicon nanowires is between 1 nanometer～1 micron based on grid type Si-NWFET manufacturing approach behind the SOI three-dimensional array type.
6. as claimed in claim 1ly it is characterized in that the cross sectional shape of said silicon nanowires is circular, laterally track shape or vertical track shape based on grid type Si-NWFET manufacturing approach behind the SOI three-dimensional array type.
7. as claimed in claim 1ly it is characterized in that based on grid type Si-NWFET manufacturing approach behind the SOI three-dimensional array type,
Said silicon nanowires is carried out thermal oxidation;
Etch away the silicon dioxide that said thermal oxidation forms.
8. as claimed in claim 1 based on grid type Si-NWFET manufacturing approach behind the SOI three-dimensional array type, it is characterized in that the material of said grid oxic horizon is silicon dioxide, silicon oxynitride or high K medium.
9. as claimed in claim 8 based on grid type Si-NWFET manufacturing approach behind the SOI three-dimensional array type, it is characterized in that said high K medium is HfO 2, Al 2O 3, ZrO 2In a kind of or its combination in any.
10. as claimed in claim 1ly it is characterized in that based on grid type Si-NWFET manufacturing approach behind the SOI three-dimensional array type material of said grid is a kind of or its combination in any in polysilicon, amorphous silicon, the metal.
11. as claimed in claim 1 based on grid type Si-NWFET manufacturing approach behind the SOI three-dimensional array type, it is characterized in that the material of said spacer medium layer is a silicon dioxide.
12. as claimed in claim 1ly it is characterized in that said etching adopts time normal pressure chemical gas phase etching method based on grid type Si-NWFET manufacturing approach behind the SOI three-dimensional array type.
13. it is as claimed in claim 1 based on grid type Si-NWFET manufacturing approach behind the SOI three-dimensional array type; It is characterized in that; Said time normal pressure chemical gas phase etching method adopts hydrogen and chlorine hydride mixed gas body; Wherein the temperature of hydrogen and chlorine hydride mixed gas body is between 600 ℃～800 ℃, and wherein the dividing potential drop of hydrogen chloride is greater than 300Torr.
CN2012100941932A 2012-03-31 2012-03-31 Manufacturing method of three-dimensional array grid-last type Si-NWFET (Nanowire Field Effect Transistor) based on SOI (Silicon On Insulator) Pending CN102623385A (en)

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CN107731895B (en) * 2012-10-10 2021-02-09 三星电子株式会社 Semiconductor device with a plurality of transistors
CN106158633A (en) * 2015-03-26 2016-11-23 中芯国际集成电路制造(上海)有限公司 The forming method of nano-wire field effect transistor
CN106158633B (en) * 2015-03-26 2019-07-02 中芯国际集成电路制造(上海)有限公司 The forming method of nano-wire field effect transistor
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US10056254B2 (en) 2015-10-12 2018-08-21 International Business Machines Corporation Methods for removal of selected nanowires in stacked gate all around architecture
CN107017295A (en) * 2015-10-19 2017-08-04 三星电子株式会社 Semiconductor devices with many raceway grooves
CN107017295B (en) * 2015-10-19 2020-07-14 三星电子株式会社 Semiconductor device with multiple channels
CN109461740A (en) * 2018-10-26 2019-03-12 长江存储科技有限责任公司 A kind of three-dimensional storage part and preparation method thereof
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