CN102623360B - 半导体装置的制造方法 - Google Patents

半导体装置的制造方法 Download PDF

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CN102623360B
CN102623360B CN201110364928.4A CN201110364928A CN102623360B CN 102623360 B CN102623360 B CN 102623360B CN 201110364928 A CN201110364928 A CN 201110364928A CN 102623360 B CN102623360 B CN 102623360B
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lead frame
semiconductor device
resin
manufacture method
burr
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CN102623360A (zh
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坂本健
鹿野武敏
田中贡
佐佐木太志
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Mitsubishi Electric Corp
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Abstract

本发明的目的在于得到一种半导体装置的制造方法,能够容易地除去树脂飞边,并且,能够抑制引线框架的端子间的放电。使用具有封装外部区域(5)和封装内部区域(6)的引线框架(1)。在引线框架(1)的侧面的上端设置有毛刺面(7),在侧面的上端附近设置有断裂面(8)。在封装外部区域(5),对引线框架(1)的侧面的上端进行倒角加工。在封装内部区域(6),将半导体元件(10)搭载在引线框架(1)上,用模塑树脂(12)进行密封。在倒角加工以及树脂密封之后,在封装外部区域(5),将在引线框架(1)的侧面设置的树脂飞边(13)除去。

Description

半导体装置的制造方法
技术领域
本发明涉及进行传递模塑的树脂密封型的半导体装置的制造方法。
背景技术
利用级进模(progressive die)从金属板进行冲压,从而形成引线框架。此时,在引线框架的侧面设置有毛刺面、断裂面、塌角面。由于该断裂面等,树脂飞边(burr)与引线框架的粘着力(adhesion)被强化,所以,树脂飞边的除去变得困难。
因此,提出了如下方法:在挡板(dam)部附加与模塑树脂的粘着性较低的物质,提高树脂飞边的除去性(例如,参照专利文献1的图11)。但是,利用该方法也不能够容易地将树脂飞边除去。此外,存在花费工夫和成本并且在现实的生产工序中难以采用这样的问题。
相对于此,提出了如下方法:垂直地对引线框架的侧面进行修整加工,由此,将毛刺面或断裂面除去(例如,参照专利文献2)。由此,能够容易地除去树脂飞边。
[专利文献1]:日本特开平4-164356号公报;
[专利文献2]:日本特开平2-202045号公报。
伴随装置的小型化,存在如下问题:引线框架的端子间的距离(空间距离)变小,产生引线框架的端子间的放电。在垂直地对引线框架的侧面进行修整加工的方法中,也存在放电的问题。
发明内容
本发明是为了解决上述课题而提出的,其目的在于得到一种半导体装置的制造方法,能够容易地除去树脂飞边,并且,能够抑制引线框架的端子间的放电。
本发明提供一种半导体装置的制造方法,该半导体装置使用具有封装外部区域和封装内部区域并且在侧面的上端设置有毛刺面且在所述侧面的上端附近设置有断裂面的引线框架,其特征在于,具有如下工序:在所述封装外部区域,对所述引线框架的所述侧面的所述上端进行倒角加工;在所述封装内部区域,在所述引线框架上搭载半导体元件,用树脂进行密封;在倒角加工以及树脂密封之后,在所述封装外部区域,将在所述引线框架的所述侧面设置的树脂飞边除去。
根据本发明,能够容易地除去树脂飞边,并且,能够抑制引线框架的端子间的放电。
附图说明
图1是示出在本发明的实施方式1中所使用的引线框架的俯视图。
图2是示出图1的引线框架的引线端子的剖面图。
图3是用于对本发明的实施方式1的半导体装置的制造方法进行说明的剖面图。
图4是用于对本发明的实施方式1的半导体装置的制造方法进行说明的俯视图。
图5是用于对本发明的实施方式1的半导体装置的制造方法进行说明的俯视图。
图6是用于对本发明的实施方式1的半导体装置的制造方法进行说明的剖面图。
图7是用于对处于引线端子间的最短距离的引线端子的侧面的面积进行说明的剖面图。
图8是用于对本发明的实施方式1的半导体装置的制造方法的变形例1进行说明的剖面图。
图9是用于对本发明的实施方式1的半导体装置的制造方法的变形例2进行说明的剖面图。
图10是用于对本发明的实施方式2的半导体装置的制造方法进行说明的剖面图。
图11是用于对本发明的实施方式3的半导体装置的制造方法进行说明的俯视图。
图12是将图11的一部分放大后的剖面图。
图13是用于对本发明的实施方式4的半导体装置的制造方法进行说明的剖面图。
具体实施方式
参照附图,对本发明的实施方式的半导体装置的制造方法进行说明。对相同或者对应的结构要素标注相同的附图标记,有时省略重复说明。
实施方式1
参照附图,对本发明的实施方式1的半导体装置的制造方法进行说明。图1是示出在本发明的实施方式1中所使用的引线框架的俯视图。引线框架1具有下垫板(die pad)2、引线端子3、连杆4。引线框架1的区域分为在以后的工序中不进行树脂密封的封装外部区域5和在以后的工序中被树脂密封的封装内部区域6。
图2是示出图1的引线框架的引线端子的剖面图。利用级进模从金属板进行冲压,从而形成引线框架1。此时,在引线框架1的侧面的上端设置有毛刺面7,在侧面的上端附近设置有断裂面8,在侧面的下端设置有塌角面9。在引线框架1的侧面,剪切面(shear  surface)是框架厚度的约70%,断裂面8是框架厚度的约30%。
图3、6是用于对本发明的实施方式1的半导体装置的制造方法进行说明的剖面图。图4、5是用于对本发明的实施方式1的半导体装置的制造方法进行说明的俯视图。
首先,如图3所示,在封装外部区域5,对有引线框架1的设置有毛刺面7和断裂面8的部分进行倒角加工(C面加工)。但是,在封装内部区域6,使毛刺面7、断裂面8以及塌角面9原样保留。
能够进行倒角加工的角度θ为3°~87°。但是,能够最容易进行倒角加工的角度θ为45°。作为具体的倒角加工的方法,存在利用引线模具进行的引线框架1的角部的切割、利用引线模具的夹持压力(clamp pressure)所进行的引线框架1的角部的变形、修整、利用锉刀进行的磨削等。
然后,如图4所示,在封装内部区域6,利用焊料将IGBT(Insulated Gate Bipolar Transistor)或二极管等半导体元件10搭载在引线框架1的下垫板2上。并且,利用导线11将半导体元件10和引线端子3连接。然后,如图5以及图6所示,用模塑树脂12将半导体元件10以及导线11密封。此时,在封装外部区域5,在引线框架1的侧面设置有树脂飞边13。
然后,通过碱性溶液中的电解剥离或喷射高压的水,由此,除去树脂飞边13。利用以上结构,制造出本实施方式的半导体装置。
如上述那样,在本实施方式中,在封装外部区域5,对引线框架1的设置有毛刺面7和断裂面8的部分进行倒角加工。由此,树脂飞边13的挂住起点消失,所以,能够利用电解飞边去除或水压飞边去除容易地将树脂飞边13除去。因此,能够使引线端子3的成型性提高,使外装焊料电镀层的不附着部减少。
此外,在封装内部区域6成为使毛刺面7等原样保留的状态,由此,模塑树脂12的挂住性或粘着性提高,能够抑制将引线框架1和模塑树脂12的界面作为起点的树脂裂纹或剥离。
此外,图7是用于对处于引线端子间的最短距离的引线端子的侧面的面积进行说明的剖面图。附图上侧是实施方式1、附图下侧是比较例。在实施方式1中进行倒角加工,但是,在比较例中没有进行倒角加工。面积S是处于引线端子3间的最短距离的引线端子3的侧面的面积。在实施方式1中,与比较例相比,能够使面积S减小。因此,即便使引线端子3间的距离变窄,也能够抑制引线端子3间的放电。所以,能够使装置小型化。
图8是用于对本发明的实施方式1的半导体装置的制造方法的变形例1进行说明的剖面图。当倒角加工精度较差时,存在在倒角加工后断裂面8残留的情况。在该情况下,如果使断裂面8残存的侧面的上下方向的宽度W为框架厚度T的10%以下,则能够在接下来的工序中容易地除去树脂飞边13。
图9是用于对本发明的实施方式1的半导体装置的制造方法的变形例2进行说明的剖面图。在用模塑树脂12进行密封之后对引线框架1的设置有毛刺面7和断裂面8的部分进行倒角加工也可以。利用倒角加工将树脂飞边13的与引线框架1较强地粘着的部分除去,由此,能够在接下来的工序中容易地除去残留的树脂飞边13。
实施方式2
图10是用于对本发明的实施方式2的半导体装置的制造方法进行说明的剖面图。在本实施方式中,在封装外部区域5,也对引线框架1的设置有塌角面9的部分进行倒角加工。由此,与实施方式1相比,能够使处于引线端子3间的最短距离的引线端子3的侧面的面积减小。因此,能够进一步抑制引线端子3间的放电。
实施方式3
图11是用于对本发明的实施方式3的半导体装置的制造方法进行说明的俯视图,图12是将其一部分放大后的剖面图。
在用模塑树脂12进行密封时,使用作为模塑模具的上模具14和下模具15。首先,将引线框架1放置在下模具15上。然后,用上模具14和下模具15夹着引线框架1。在该模塑模具夹紧时,将上模具14的突起部16向引线框架1的角部按压,使角部变形,由此,同时进行倒角加工。然后,从横浇口17向上模具14和下模具15之间注入模塑树脂12。
这样,在进行树脂密封的同时进行倒角加工,由此,能够削减中间产物、工时数、时间,所以,能够降低加工成本。但是,为了实施本实施方式,不对半导体元件10产生影响、引线框架1的对位充分以及利用突起部16进行的倒角加工容易是必要的。
实施方式4
图13是用于对本发明的实施方式4的半导体装置的制造方法进行说明的剖面图。与实施方式1~3同样地,在进行倒角加工以及树脂密封之后,对在引线框架1的侧面设置有树脂飞边13的部分进行弯曲加工。由此,在附着于引线框架1的侧面的树脂飞边13中产生应力,所以,树脂飞边13的除去变得容易。
附图标记说明:
1 引线框架
5 封装外部区域
6 封装内部区域
7 毛刺面
8 断裂面
9 塌角面
10 半导体元件
12 模塑树脂(树脂)
13 树脂飞边
14 上模具(模塑模具)
15 下模具(模塑模具)。

Claims (4)

1.一种半导体装置的制造方法,该半导体装置使用具有封装外部区域和封装内部区域并且在侧面的上端设置有毛刺面且在所述侧面的上端附近设置有断裂面的引线框架,该半导体装置的制造方法的特征在于,具有如下工序:
在所述封装外部区域,对所述引线框架的设置有所述毛刺面和所述断裂面的部分进行倒角加工;
在所述封装内部区域,将半导体元件搭载在所述引线框架上,用树脂进行密封;
在倒角加工以及树脂密封之后,在所述封装外部区域,将在所述引线框架的所述侧面所设置的树脂飞边除去。
2.如权利要求1所述的半导体装置的制造方法,其特征在于,
还具有对所述引线框架的所述侧面的下端进行倒角加工的工序。
3.如权利要求1或2所述的半导体装置的制造方法,其特征在于,
在用所述树脂进行密封时,使用模塑模具,
也同时利用所述模塑模具进行所述倒角加工。
4.如权利要求1或2所述的半导体装置的制造方法,其特征在于,
在进行所述倒角加工并且用所述树脂进行密封之后,且在去除所述树脂飞边之前,对在所述引线框架的所述侧面设置有所述树脂飞边的部分进行弯曲加工。
CN201110364928.4A 2011-01-31 2011-11-17 半导体装置的制造方法 Expired - Fee Related CN102623360B (zh)

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Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6597393B2 (ja) * 2016-02-29 2019-10-30 住友電装株式会社 樹脂成形品とその製造方法
JP6472568B2 (ja) * 2016-03-07 2019-02-20 三菱電機株式会社 半導体装置の製造方法
US10930523B2 (en) * 2016-03-29 2021-02-23 Mitsubishi Electric Corporation Method for manufacturing resin-sealed power semiconductor device
EP3471220A1 (en) * 2017-10-16 2019-04-17 TE Connectivity Germany GmbH Bent electric contact element with chamfered edges and method for its manufacture
EP3544394A1 (en) * 2018-03-24 2019-09-25 Melexis Technologies SA Integrated circuit lead frame design and method
US11543466B2 (en) 2018-03-24 2023-01-03 Melexis Technologies Sa Magnetic sensor component and assembly

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5886397A (en) * 1996-09-05 1999-03-23 International Rectifier Corporation Crushable bead on lead finger side surface to improve moldability

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60123047A (ja) * 1983-12-07 1985-07-01 Toshiba Corp 半導体装置
JPS60261163A (ja) * 1984-06-07 1985-12-24 Shinko Electric Ind Co Ltd リードフレームの製造方法
JPS62198143A (ja) * 1986-02-26 1987-09-01 Shinko Electric Ind Co Ltd リ−ドフレ−ム
JPS62247553A (ja) * 1986-04-18 1987-10-28 Mitsubishi Electric Corp 半導体装置の製造方法
JPS63151056A (ja) 1986-12-16 1988-06-23 Matsushita Electronics Corp リ−ドフレ−ムの製造方法
JPS63197363A (ja) 1987-02-12 1988-08-16 Goto Seisakusho:Kk 半導体装置の製造方法
JP2606736B2 (ja) * 1989-01-31 1997-05-07 株式会社三井ハイテック リードフレームの製造方法
JPH03275224A (ja) 1990-03-23 1991-12-05 Hitachi Cable Ltd 順送金型によるリードフレームの打抜き加工方法
JPH0442565A (ja) * 1990-06-08 1992-02-13 Seiko Epson Corp 半導体パッケージ
JPH04164356A (ja) 1990-10-29 1992-06-10 Nec Corp リードフレーム
JPH06291244A (ja) * 1993-03-31 1994-10-18 Kawasaki Steel Corp リードフレームおよび半導体装置
US5637914A (en) 1994-05-16 1997-06-10 Hitachi, Ltd. Lead frame and semiconductor device encapsulated by resin
GB2312785B (en) * 1995-01-05 1999-08-11 Int Rectifier Co Ltd Electrode configuration in surface-mounted devices
JPH09276952A (ja) 1996-04-15 1997-10-28 Apic Yamada Kk リードフレーム打ち抜き用プレス加工金型
DE19736895A1 (de) 1996-09-05 1998-04-16 Int Rectifier Corp Gehäuse für Halbleiterbauteile
US5939775A (en) 1996-11-05 1999-08-17 Gcb Technologies, Llc Leadframe structure and process for packaging intergrated circuits
JP3862410B2 (ja) * 1998-05-12 2006-12-27 三菱電機株式会社 半導体装置の製造方法及びその構造
TW428295B (en) * 1999-02-24 2001-04-01 Matsushita Electronics Corp Resin-sealing semiconductor device, the manufacturing method and the lead frame thereof

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5886397A (en) * 1996-09-05 1999-03-23 International Rectifier Corporation Crushable bead on lead finger side surface to improve moldability

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
JP特许昭62247553A 1987.10.28

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