CN102623058B - Erasing voltage generation circuit and method of nonvolatile memory - Google Patents
Erasing voltage generation circuit and method of nonvolatile memory Download PDFInfo
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Abstract
The application discloses erasing voltage generation circuit and method of a nonvolatile memory. The erasing voltage generation circuit of the nonvolatile memory comprises an analog-digital conversion unit, a logic control unit, a voltage control unit and a voltage generation unit, wherein the analog-digital conversion unit is used for monitoring supply voltage and converting the supply voltage into a corresponding logic control signal according to preset rules; the logic control unit is used for acquiring the variation difference of the supply voltage when the logic control signal changes and generating an erasing voltage control signal according to the difference; the voltage control unit is used for outputting a corresponding controlled voltage value according to the erasing voltage control signal; and according to the controlled voltage value, the voltage generation unit is used for outputting the final word line voltage and the P-well voltage, which are required during erosion. According to the application, the problem of un-erased PWELL-STRESS of the nonvolatile memory unit can be reduced and even avoided, and the erased threshold voltage of the nonvolatile memory unit is surely distributed within the expectant range.
Description
Technical field
The application relates to semiconductor memory technologies field, and the erasing voltage particularly relating to a kind of nonvolatile memory produces circuit, a kind of nonvolatile memory, and, a kind of erasing voltage production method of nonvolatile memory.
Background technology
Along with developing rapidly and widespread use of various electronic installation and embedded system, as computing machine, personal digital assistant, mobile phone, digital camera etc., a large amount of needs one can repeatedly be programmed, capacity is large, read-write, wipe quick and easy, simple, peripheral components is few, the memory device of cheap non-volatile (still can keep stored data message under powering-off state).Nonvolatile semiconductor memory member arises at the historic moment under this background demand.A nonvolatile memory is also a metal-oxide-semiconductor usually, has a source electrode (source), a drain electrode (drain), a grid (gate), also has a floating grid (floating gate) in addition.Visible, its structure is slightly different with general metal-oxide-semiconductor, and many floating grids, this floating grid insulated body isolates from other parts.
For flash memory (Flash Memory), it is a kind of nonvolatile memory of based semiconductor, internal information, the online functional characteristics such as erasable still can be retained after there is system power failure, flash memory injects mechanism by thermoelectron and realizes device programming, adopt tunnel effect (Fower-Nordheim tunneling, FN mechanism) realize erasing, the erasing of flash memory is that unit carries out with a sector (sector) or several sector.Tunnel effect refers to, grid adds a higher negative voltage, at PWELL (P trap, P substrate) on add a higher positive voltage, so just make the electric field that between floating grid and PWELL, existence one is very strong, this electric field can change by enable band, and then provides the path that arrives PWELL to the electronics on floating grid, thus completes the erase operation to cell (storage unit).
In the erase period, word-line (wordline) voltage preparing the non-volatile memory cells of erasing is a negative pressure (as-8V), (in flash, the way of cell is PWELL voltage, first a dark N trap is done, a P trap is done again inside dark N trap, namely PWELL voltage be applied to the voltage on this P trap, and last cell is made in this P trap) and source voltage connect malleation (as+8V) together; And the word-line voltage of the non-volatile memory cells be not wiped free of is supply voltage, PWELL voltage and source voltage connect malleation equally.When chip operation, supply voltage allows the scope of change comparatively large, and the nonvolatile memory of such as 1.8V, supply voltage allows variation range to be 1.4V to 2.5V.Like this, the word-line voltage and the PWELL voltage that prepare the non-volatile memory cells of erasing are all determine voltage, can not have problems; But for the non-volatile memory cells be not wiped free of, because word-line is with mains voltage variations, PWELL-STRESS problem will be there is.
Specifically, PWELL-STRESS problem refers to, because in flash, the erasing of cell is carried out in units of sector, multiple sector constitutes a large physics block (block), and they are made in same P trap.Like this when wiping some sector, be applied to the P trap voltage on this sector, equally also can be applied on other sector, and this condition can produce more weak erasure effect to the cell in other sector, finally may change the storing value of user, therefore must avoid.
In the nonvolatile memory that supply voltage is lower, such as, be in the product of 1.8V at supply voltage, along with the change of supply voltage, the non-volatile memory cells be not wiped free of not only can meet with PWELL-STRESS problem, and supply voltage is lower, and the voltage difference between PWELL and word-line is larger, the impact of PWELL-STRESS is also more remarkable, thus the threshold voltage of these memory cells may be caused to change.
Therefore, the technical matters needing those skilled in the art urgently to solve at present is exactly: the erasing voltage generation mechanism that how innovatively can propose a kind of nonvolatile memory, in order to weaken the PWELL-STRESS problem of the non-volatile memory cells even avoiding not being wiped free of, and ensure that the threshold voltage of the non-volatile memory cells be wiped free of can be distributed in desired extent.
Summary of the invention
The circuit that the erasing voltage that technical problems to be solved in this application are to provide a kind of nonvolatile memory produces and method, and a kind of nonvolatile memory, in order to weaken the PWELL-STRESS problem of the non-volatile memory cells even avoiding not being wiped free of, and ensure that the threshold voltage of the non-volatile memory cells be wiped free of can be distributed in desired extent.
In order to solve the problems of the technologies described above, the erasing voltage that the embodiment of the present application discloses a kind of nonvolatile memory produces circuit, comprising:
AD conversion unit, for monitoring supply voltage, and is converted to corresponding logic control signal by described supply voltage by preset rules;
Logic control element, for when described logic control signal changes, obtains the change difference of supply voltage, and generates erasing voltage adjustment signal according to this difference;
Voltage-adjusting unit, for according to described erasing voltage adjustment signal, exports and adjusts magnitude of voltage accordingly;
Voltage generating unit, the final word line voltage needed during for exporting erase operation according to described adjustment magnitude of voltage and P trap voltage.
Preferably, described supply voltage is simulating signal, and described logic control signal is digital signal; Described preset rules is the supply voltage of at least two numerical intervals and the one-to-one relationship of at least two Different Logic control signals.
Preferably, described erasing voltage adjustment signal comprises reference voltage and multiple parameter, and described voltage-adjusting unit comprises:
Magnitude of voltage generates subelement, adjusts magnitude of voltage accordingly for generating according to described reference voltage and multiple parameter;
Voltage exports subelement, for exporting described adjustment magnitude of voltage.
Preferably, described adjustment magnitude of voltage is positive voltage value or negative value, and described voltage generating unit comprises:
First regulates subelement, for when described adjustment magnitude of voltage is positive voltage value, on the basis of initial word line voltage and P trap voltage, increase word line voltage and the P trap voltage of storage unit according to described adjustment magnitude of voltage, the final word line voltage needed when generating erase operation and P trap voltage also export;
Second regulates subelement, for when described adjustment magnitude of voltage is negative value, on the basis of initial word line voltage and P trap voltage, reduce word line voltage and the P trap voltage of storage unit according to described adjustment magnitude of voltage, the final word line voltage needed when generating erase operation and P trap voltage also export.
Preferably, described AD conversion unit is an analog to digital converter.
The embodiment of the present application also discloses a kind of nonvolatile memory, and described nonvolatile memory comprises the erasing voltage be connected with storage unit and produces circuit, and described erasing voltage produces circuit and comprises:
AD conversion unit, for monitoring supply voltage, and is converted to corresponding logic control signal by described supply voltage by preset rules;
Logic control element, for when described logic control signal changes, obtains the change difference of supply voltage, and generates erasing voltage adjustment signal according to this difference;
Voltage-adjusting unit, for according to described erasing voltage adjustment signal, exports and adjusts magnitude of voltage accordingly;
Voltage generating unit, the final word line voltage needed during for exporting erase operation according to described adjustment magnitude of voltage and P trap voltage.
Preferably, described supply voltage is simulating signal, and described logic control signal is digital signal; Described preset rules is the supply voltage of at least two numerical intervals and the one-to-one relationship of at least two Different Logic control signals.
Preferably, described erasing voltage adjustment signal comprises reference voltage and multiple parameter, and described voltage-adjusting unit comprises:
Magnitude of voltage generates subelement, adjusts magnitude of voltage accordingly for generating according to described reference voltage and multiple parameter;
Voltage exports subelement, for exporting described adjustment magnitude of voltage.
Preferably, described adjustment magnitude of voltage is positive voltage value or negative value, and described voltage generating unit comprises:
First regulates subelement, for when described adjustment magnitude of voltage is positive voltage value, on the basis of initial word line voltage and P trap voltage, increase word line voltage and the P trap voltage of storage unit according to described adjustment magnitude of voltage, the final word line voltage needed when generating erase operation and P trap voltage also export;
Second regulates subelement, for when described adjustment magnitude of voltage is negative value, on the basis of initial word line voltage and P trap voltage, reduce word line voltage and the P trap voltage of storage unit according to described adjustment magnitude of voltage, the final word line voltage needed when generating erase operation and P trap voltage also export.
The embodiment of the present application also discloses a kind of erasing voltage production method of nonvolatile memory, comprising:
Monitoring supply voltage, and described supply voltage is converted to corresponding logic control signal by preset rules;
When described logic control signal changes, obtain the change difference of supply voltage, and generate erasing voltage adjustment signal according to this difference;
Export according to described erasing voltage adjustment signal and adjust magnitude of voltage accordingly;
The final word line voltage needed when exporting erase operation according to described adjustment magnitude of voltage and P trap voltage.
Preferably, described supply voltage is simulating signal, and described logic control signal is digital signal; Described preset rules is the supply voltage of at least two numerical intervals and the one-to-one relationship of at least two Different Logic control signals.
Preferably, described voltage adjustment signal comprises reference voltage and multiple parameter, and the described step according to erasing voltage adjustment signal output corresponding adjustment magnitude of voltage comprises:
Generate according to described reference voltage and multiple parameter and adjust magnitude of voltage accordingly;
Export described adjustment magnitude of voltage.
Preferably, described adjustment magnitude of voltage is positive voltage value or negative value, and the described step according to adjusting final word line voltage and the P trap voltage needed when magnitude of voltage exports erase operation comprises:
When described adjustment magnitude of voltage is positive voltage value, on the basis of initial word line voltage and P trap voltage, increase word line voltage and the P trap voltage of storage unit according to described adjustment magnitude of voltage, the final word line voltage needed when generating erase operation and P trap voltage also export;
When described adjustment magnitude of voltage is negative value, on the basis of initial word line voltage and P trap voltage, reduce word line voltage and the P trap voltage of storage unit according to described adjustment magnitude of voltage, the final word line voltage needed when generating erase operation and P trap voltage also export.
Compared with prior art, the application has the following advantages:
The application regulates word-line voltage and the PWELL voltage of the non-volatile memory cells be not wiped free of according to supply voltage, make when mains voltage variations, PWELL voltage between erasing period also changes accordingly, and PWELL voltage is consistent with the change direction of supply voltage, constant to guarantee both differences, the PWELL-STRESS of the non-volatile memory cells be not wiped free of is weakened.In the erase period simultaneously, the word-line voltage of the non-volatile memory cells be wiped free of and PWELL voltage also need to do corresponding adjustment, its change direction is consistent with the direction of supply voltage, constant to ensure the difference of PWELL voltage and word-line voltage, the threshold voltage being wiped free of memory cell like this can be distributed in desired extent.
Moreover, in the nonvolatile memory that supply voltage is higher, be such as in the nonvolatile memory chip of 3.3V at supply voltage, chip internal has a regulator (voltage adjuster), a lower slightly burning voltage (about 2.0V) can be produced according to supply voltage, this magnitude of voltage substantially constant, do not change with the fluctuation of supply voltage, this voltage adds on the word-line of not selected non-volatile memory cells in the erase period, therefore may not there is serious PWELL-STRESS problem at the nonvolatile memory product that supply voltage is higher.But, in the nonvolatile memory that supply voltage is lower, such as, be in the nonvolatile memory chip that 1.8V is even lower at supply voltage, the integrated regulator of chip internal produces the burning voltage complicated technology realization of 2V, and cost can be made greatly to improve.Adopt the embodiment of the present application, the word line voltage of storage unit and P trap voltage can be made all to follow the change of supply voltage, and the voltage difference between them remains unchanged substantially, thus the threshold voltage being wiped free of memory cell is distributed in desired extent, and weaken the PWELL-STRESS problem of the non-volatile memory cells even avoiding not being wiped free of.
Accompanying drawing explanation
Fig. 1 is the structured flowchart of the erasing voltage generation circuit embodiments of a kind of nonvolatile memory of the application;
Fig. 2 is the schematic diagram of the realizing circuit example of a kind of A/D converter of the application;
Fig. 3 is the flow chart of steps of the erasing voltage production method embodiment of a kind of nonvolatile memory of the application.
Embodiment
For enabling above-mentioned purpose, the feature and advantage of the application more become apparent, below in conjunction with the drawings and specific embodiments, the application is described in further detail.
At present, there is the problem of PWELL-STRESS in the erase operation of flash memory, when namely wiping some sectors of flash memory, needs to add negative pressure to grid, add certain malleation to source electrode and P trap.The electric field that added voltage is formed causes a potential barrier, and it provides one is arrived P trap path by floating grid to the electronics in floating grid, thus changes the logic state of storage unit (cell), realizes erasing.
Owing to generally including multiple sector (sector) in a storage block (block), but the malleation that P trap adds can be added on all cell in storage block, in this case, added voltage can produce interference for the cell do not done in other sector of erase operation, thus affects stability and the reliability of data in cell.Preventing when carrying out erase operation to target sector, to the interference do not done other sectors of wiping in same storage block and produce, improving stability and the reliability of data in storage unit.
Such as, be in the nonvolatile memory of 1.8V at supply voltage, along with the change of supply voltage, the storage unit be not wiped free of can meet with PWELL-STRESS problem, and supply voltage is lower, voltage difference between PWELL and word-line is larger, and the impact of PWELL-STRESS is also more remarkable, thus the threshold voltage of these memory cells may be caused to change.
Therefore, for overcoming the impact of PWELL-STRESS, inventor herein proposes a kind of brand-new resolving ideas: the word-line voltage and the PWELL voltage that namely regulate the non-volatile memory cells be not wiped free of according to supply voltage, make when mains voltage variations, PWELL voltage between erasing period also changes accordingly, and PWELL voltage is consistent with the change direction of supply voltage, constant to guarantee both differences, the PWELL-STRESS of the non-volatile memory cells be not wiped free of is weakened.In the erase period simultaneously, the word-line voltage of the non-volatile memory cells be wiped free of and PWELL voltage also need to do corresponding adjustment, its change direction is consistent with the direction of supply voltage, constant to ensure the difference of PWELL voltage and word-line voltage, the threshold voltage being wiped free of memory cell like this can be distributed in desired extent.
With reference to figure 1, the erasing voltage showing a kind of nonvolatile memory of the application produces the structured flowchart of circuit embodiments, specifically can comprise as lower unit:
AD conversion unit 101, for monitoring supply voltage, and is converted to corresponding logic control signal by described supply voltage by preset rules;
Logic control element 102, for when described logic control signal changes, obtains the change difference of supply voltage, and generates erasing voltage adjustment signal according to this difference;
Voltage-adjusting unit 103, for according to described erasing voltage adjustment signal, exports and adjusts magnitude of voltage accordingly;
Voltage generating unit 104, the final word line voltage needed during for exporting erase operation according to described adjustment magnitude of voltage and P trap voltage.
In specific implementation, described AD conversion unit 101 can be an A/D converter (ADC), is well known that, A/D converter is that an input simulating signal is converted to a digital signal exported.In the embodiment of the present application, described A/D converter can be connected with voltage offset electric circuit (not shown), and input is the supply voltage as simulating signal, and output is the logic control signal as digital signal.In actual applications, described A/D converter will monitor the change of supply voltage VDD continuously, according to different supply voltage values, produces the output of corresponding logic control signal, and these logic control signals actually represent different supply voltage states.
Analog/digital conversion generally will through over-sampling, maintenance, quantification and coding 4 processes.In side circuit, some process merges carries out, and as sampling and maintenance, quantizes and be coded in transfer process to realize simultaneously.Quantification is that simulating signal range is divided into many discrete magnitudes, and determines the magnitude belonging to input signal.Coding distributes unique numerical code to each magnitude, and determine the code corresponding with input signal.Prevailing code system is scale-of-two, and it has a n power magnitude (n is figure place) of 2, can number one by one successively.
Analog-to-digital method is a lot, divides can be divided into direct method and the large class of indirect method two from transfer principle.Direct method directly voltage transitions is become digital quantity.A set of reference voltage that it exports with digital-to-analogue network, repeatedly compares with tested voltage by turn from a high position, until the two reaches or close balance.Steering logic can realize the control of dichotomous search, and its comparative approach is weighed as balance.First make the most significant digit Dn-1=1 of binary system number, after analog to digital conversion, obtain the analog voltage VS of a whole range half, compared with input voltage vin, if Vin > is VS, then retain this position; If Vin < Vs, then Dn-1=0.Then next bit Dn-2=1 is made, with the result of last time together after analog to digital conversion compared with Vin, repeat this process, until make D0=1, again compared with Vin, determined whether retaining this position by Vin > VS or Vin < VS.Through n time relatively after, the state of n bit register is the data after conversion.
With reference to being a kind of schematic diagram of A/D converter shown in figure 2, the input voltage IN of comparer is collected through power supply potential-divider network (resistance R0, R1, R2, R3, R4 are only shown), compare respectively by comparer I0, I1, I2 with reference voltage V REF from high-order n, obtain output signal OUT, in output logic, carry out analog/digital conversion control according to this output signal OUT, obtain final digital signal.
Be understandable that, in the embodiment of the present application, namely described preset rules refers to the supply voltage of at least two numerical intervals and the one-to-one relationship of at least two Different Logic control signals, in practice, can be determined by the precision arranging A/D converter conversion.The precision of A/D converter conversion, usually with the figure place of the digital signal of output number represent.For 2bit, corresponding relation can be as shown in the table:
| Supply voltage | Logic control signal VO<1:0> |
| vdd＜1.6V | 00 |
| 1.6V＜vdd＜1.8V | 01 |
| 1.8V＜vdd＜2.0V | 10 |
| 2.0V＜vdd | 11 |
In actual applications, the performance such as precision, speed of described A/D converter can be determined according to system index by those skilled in the art, such as, those skilled in the art can adopt the ADC of indirect method, voltage is not directly changed into numeral by this kind of ADC, but first convert a certain intermediate quantity to, then convert numeral to by intermediate quantity.Conventional has voltage-vs-time interval (V/T) type and two kinds, voltage-frequency (V/F) type, and the dual slope method (also known as double integration method) wherein in voltage-vs-time cabinet-type is used comparatively general; Or those skilled in the art can adopt the ADC of other precision, as 8,16,128 etc., the application to this without the need to being limited.
In specific implementation, along with the development of large scale integrated circuit technology, analog to digital converter volume is reduced into one piece of template, one piece of integrated circuit gradually, and therefore can't too much account for memory-aided area, cost is also lower.
When nonvolatile memory carries out erase operation, if supply voltage VDD is unstable, such as change between 1.4V to 2.3V, in order to overcome PWELL_STRESS, and reduce the distribution of cell threshold voltage, the word-line voltage of cell and PWELL voltage is needed to do corresponding adjustment, to ensure the difference constant (relevant to PWELL_STRESS) between PWELL voltage and supply voltage VDD, ensure the difference constant (distributing relevant to the threshold value of cell) between PWELL voltage and word-line voltage simultaneously.Therefore, when carrying out erase operation, change if AD conversion unit monitors supply voltage VDD, then Trigger Logic control module 102.In specific implementation, described logic control element 102 can be designed as a digital control circuit, it receives the logic control signal that AD conversion unit 101 exports, and when described logic control signal changes, obtain the change difference of supply voltage, and generate erasing voltage adjustment signal according to this difference; Such as, when the difference of the secondary supply voltage monitored and the supply voltage monitored last time, and generate erasing voltage adjustment signal according to this difference, these erasing voltages adjustment signal is by by voltage-adjusting unit 103 generation and the output that adjust magnitude of voltage, and these adjustment magnitudes of voltage and corresponding supply voltage have relation one to one.Voltage generating unit 104 will adjust the final word line voltage and P trap voltage that need when magnitudes of voltage export erase operations according to these.
In a preferred embodiment of the present application, described erasing voltage adjustment signal can comprise reference voltage and multiple parameter, and described voltage-adjusting unit 103 can comprise following subelement:
Magnitude of voltage generates subelement, adjusts magnitude of voltage accordingly for generating according to described reference voltage and multiple parameter;
Voltage exports subelement, for exporting described adjustment magnitude of voltage.
Application the present embodiment, described voltage generating unit 104 can be a charge pump circuit, charge pump, that one utilizes so-called " fast " (flying) or " pumping " electric capacity (but not inductance or transformer) to carry out the DC-DC (transducer) of energy storage. they can make input voltage raise or reduce, and also may be used for producing negative voltage.The FET switch array of its inside controls the charging and discharging of flying capacitor in a certain way, thus makes input voltage with certain factor (0.5,2 or 3 etc.) multiplication or reduce, thus obtains required output voltage.
In specific implementation, adjustment magnitude of voltage can be produced by negative-feedback circuit.This negative-feedback circuit comprises output voltage detecting circuit and comparator circuit, wherein, output voltage detecting circuit, the change of charge pump output voltage is detected for the moment, and the output voltage values of detection and reference voltage are compared by comparator circuit, whether the output signal of comparer then controls the work of charge pump circuit.
The integral multiple of the output voltage values of charge pump normally reference voltage, such as, if reference voltage is 1.2V, then output voltage is (1.2*N) V, N is integer.As can be seen here, the control module in the embodiment of the present application, under different supply voltage VDD, by logic control signal, makes negative-feedback circuit select different reference voltages and different integral multiples, can determine to produce which kind of magnitude of voltage.
Certainly, the control module of the application is also not limited to a certain specific implementation, as long as the target reached adopts the digital signal of AD conversion unit as input control signal, and then select corresponding reference voltage and integer multiple, reach this function.
In specific implementation, described adjustment magnitude of voltage is positive voltage value or negative value, and in this case, described voltage generating unit 104 can comprise following subelement:
First regulates subelement, for when described adjustment magnitude of voltage is positive voltage value, on the basis of initial word line voltage and P trap voltage, increase word line voltage and the P trap voltage of storage unit according to described adjustment magnitude of voltage, the final word line voltage needed when generating erase operation and P trap voltage also export;
Second regulates subelement, for when described adjustment magnitude of voltage is negative value, on the basis of initial word line voltage and P trap voltage, reduce word line voltage and the P trap voltage of storage unit according to described adjustment magnitude of voltage, the final word line voltage needed when generating erase operation and P trap voltage also export.
Such as, when supply voltage is 1.8V, PWELL voltage is 8V, word-line voltage is-9V; When supply voltage becomes 1.6V, PWELL voltage reduces 0.2V (i.e. 7.8V) accordingly, and word-line voltage also reduces 0.2V (i.e.-9.2V).PWELL voltage under both of these case and the difference of supply voltage are all 6.2V, and by contrast, PWELL_STRESS can not worsen; The difference of PWELL voltage and word-line voltage is all 17V simultaneously, and the variation range of this difference is narrower, and the threshold value distribution of cell also can be more concentrated.
During embody rule, in the nonvolatile memory that supply voltage is higher, be such as in the nonvolatile memory chip of 3.3V at supply voltage, chip internal has a regulator (voltage adjuster), a lower slightly burning voltage (about 2.0V) can be produced according to supply voltage, this magnitude of voltage substantially constant, do not change with the fluctuation of supply voltage, this voltage adds on the word-line of not selected non-volatile memory cells in the erase period, therefore serious PWELL-STRESS problem may not be there is at the nonvolatile memory product that supply voltage is higher.But, in the nonvolatile memory that supply voltage is lower, such as, be in the nonvolatile memory chip that 1.8V is even lower at supply voltage, the integrated regulator of chip internal produces the burning voltage complicated technology realization of 2V, and cost can be made greatly to improve.Adopt the embodiment of the present application, the word line voltage of storage unit and P trap voltage can be made all to follow the change of supply voltage, and the voltage difference between them remains unchanged substantially, thus the threshold voltage being wiped free of memory cell is distributed in desired extent, and weaken the PWELL-STRESS problem of the non-volatile memory cells even avoiding not being wiped free of.Therefore the application is particularly useful for the nonvolatile memory under low supply voltage.
The erasing voltage that the application proposes produces circuit and can be integrated in nonvolatile memory very simply, namely the application also proposed a kind of nonvolatile memory, in this nonvolatile memory, comprise the erasing voltage be connected with storage unit and produce circuit, and, described erasing voltage produces circuit can comprise the unit shown in Fig. 1, and about the related introduction reference relevant portion above of unit, the application is not repeated herein.
With reference to figure 3, show the flow chart of steps of the erasing voltage production method embodiment of a kind of nonvolatile memory of the application, specifically can comprise the steps:
Step 301, monitoring supply voltage, and described supply voltage is converted to corresponding logic control signal by preset rules;
Step 302, when described logic control signal changes, obtain the change difference of supply voltage, and generate erasing voltage adjustment signal according to this difference;
Step 303, to export according to described erasing voltage adjustment signal and adjust magnitude of voltage accordingly;
Step 304, the final word line voltage needed when exporting erase operation according to described adjustment magnitude of voltage and P trap voltage.
In specific implementation, described supply voltage is simulating signal, and described logic control signal is digital signal; Described preset rules can be the supply voltage of at least two numerical intervals and the one-to-one relationship of at least two Different Logic control signals.
In a preferred embodiment of the present application, described voltage adjustment signal comprises reference voltage and multiple parameter, and the described step according to erasing voltage adjustment signal output corresponding adjustment magnitude of voltage comprises following sub-step:
Generate according to described reference voltage and multiple parameter and adjust magnitude of voltage accordingly;
Export described adjustment magnitude of voltage.
As a kind of example of the embodiment of the present application embody rule, described adjustment magnitude of voltage is positive voltage value or negative value, in this case, describedly specifically following sub-step can be comprised according to the step of the final word line voltage that needs and P trap voltage when exporting erase operation:
Sub-step S1, when described adjustment magnitude of voltage is positive voltage value, on the basis of initial word line voltage and P trap voltage, increase word line voltage and the P trap voltage of storage unit according to described adjustment magnitude of voltage, the final word line voltage needed when generating erase operation and P trap voltage also export;
Sub-step S2, when described adjustment magnitude of voltage is negative value, on the basis of initial word line voltage and P trap voltage, reduce word line voltage and the P trap voltage of storage unit according to described adjustment magnitude of voltage, the final word line voltage needed when generating erase operation and P trap voltage also export.
In a particular application, described adjustment magnitude of voltage is identical with the change difference of supply voltage.Further, the application is particularly useful for the nonvolatile memory of low supply voltage.
It should be noted that, for aforesaid embodiment of the method, in order to simple description, therefore it is all expressed as a series of combination of actions, but those skilled in the art should know, the application is not by the restriction of described sequence of movement, because according to the application, some step can adopt other orders or carry out simultaneously.Secondly, those skilled in the art also should know, the embodiment described in instructions all belongs to preferred embodiment, and involved action and module might not be that the application is necessary.
For embodiment of the method, due to the embodiment basic simlarity of circuit shown in itself and Fig. 1, so description is fairly simple, relevant part illustrates see the part of previous embodiment.
Finally, also it should be noted that, in this article, the such as relational terms of first and second grades and so on is only used for an entity or operation to separate with another entity or operational zone, and not necessarily requires or imply the relation that there is any this reality between these entities or operation or sequentially.And, term " comprises ", " comprising " or its any other variant are intended to contain comprising of nonexcludability, thus make to comprise the process of a series of key element, method, article or equipment and not only comprise those key elements, but also comprise other key elements clearly do not listed, or also comprise by the intrinsic key element of this process, method, article or equipment.When not more restrictions, the key element limited by statement " comprising ... ", and be not precluded within process, method, article or the equipment comprising described key element and also there is other identical element.
Above circuit is produced to the erasing voltage of a kind of nonvolatile memory that the application provides, a kind of nonvolatile memory, and, a kind of erasing voltage production method of nonvolatile memory is described in detail, apply specific case herein to set forth the principle of the application and embodiment, the explanation of above embodiment is just for helping method and the core concept thereof of understanding the application; Meanwhile, for one of ordinary skill in the art, according to the thought of the application, all will change in specific embodiments and applications, in sum, this description should not be construed as the restriction to the application.
Claims (13)
1. the erasing voltage of nonvolatile memory produces a circuit, it is characterized in that, comprising:
AD conversion unit, for monitoring supply voltage, and is converted to corresponding logic control signal by described supply voltage by preset rules;
Logic control element, for when described logic control signal changes, obtains the change difference of supply voltage, and generates erasing voltage adjustment signal according to this difference;
Voltage-adjusting unit, for according to described erasing voltage adjustment signal, exports and adjusts magnitude of voltage accordingly;
Voltage generating unit, the final word line voltage needed during for exporting erase operation according to described adjustment magnitude of voltage and P trap voltage;
Wherein, in the erase period, word-line voltage and the PWELL voltage of the non-volatile memory cells be not wiped free of is regulated, and consistent with the change direction of supply voltage;
In the erase period, regulate word-line voltage and the PWELL voltage of the non-volatile memory cells be wiped free of simultaneously, and consistent with the change direction of supply voltage.
2. circuit as claimed in claim 1, it is characterized in that, described supply voltage is simulating signal, and described logic control signal is digital signal; Described preset rules is the supply voltage of at least two numerical intervals and the one-to-one relationship of at least two Different Logic control signals.
3. circuit as claimed in claim 2, is characterized in that, described erasing voltage adjustment signal comprises reference voltage and multiple parameter, and described voltage-adjusting unit comprises:
Magnitude of voltage generates subelement, adjusts magnitude of voltage accordingly for generating according to described reference voltage and multiple parameter;
Voltage exports subelement, for exporting described adjustment magnitude of voltage.
4. the circuit as described in claim 1,2 or 3, is characterized in that, described adjustment magnitude of voltage is positive voltage value or negative value, and described voltage generating unit comprises:
First regulates subelement, for when described adjustment magnitude of voltage is positive voltage value, on the basis of initial word line voltage and P trap voltage, increase word line voltage and the P trap voltage of storage unit according to described adjustment magnitude of voltage, the final word line voltage needed when generating erase operation and P trap voltage also export;
Second regulates subelement, for when described adjustment magnitude of voltage is negative value, on the basis of initial word line voltage and P trap voltage, reduce word line voltage and the P trap voltage of storage unit according to described adjustment magnitude of voltage, the final word line voltage needed when generating erase operation and P trap voltage also export.
5. circuit as claimed in claim 4, it is characterized in that, described AD conversion unit is an analog to digital converter.
6. a nonvolatile memory, is characterized in that, described nonvolatile memory comprises the erasing voltage be connected with storage unit and produces circuit, and described erasing voltage produces circuit and comprises:
AD conversion unit, for monitoring supply voltage, and is converted to corresponding logic control signal by described supply voltage by preset rules;
Logic control element, for when described logic control signal changes, obtains the change difference of supply voltage, and generates erasing voltage adjustment signal according to this difference;
Voltage-adjusting unit, for according to described erasing voltage adjustment signal, exports and adjusts magnitude of voltage accordingly;
Voltage generating unit, the final word line voltage needed during for exporting erase operation according to described adjustment magnitude of voltage and P trap voltage;
Wherein, in the erase period, word-line voltage and the PWELL voltage of the non-volatile memory cells be not wiped free of is regulated, and consistent with the change direction of supply voltage;
In the erase period, regulate word-line voltage and the PWELL voltage of the non-volatile memory cells be wiped free of simultaneously, and consistent with the change direction of supply voltage.
7. nonvolatile memory as claimed in claim 6, it is characterized in that, described supply voltage is simulating signal, and described logic control signal is digital signal; Described preset rules is the supply voltage of at least two numerical intervals and the one-to-one relationship of at least two Different Logic control signals.
8. nonvolatile memory as claimed in claim 7, is characterized in that, described erasing voltage adjustment signal comprises reference voltage and multiple parameter, and described voltage-adjusting unit comprises:
Magnitude of voltage generates subelement, adjusts magnitude of voltage accordingly for generating according to described reference voltage and multiple parameter;
Voltage exports subelement, for exporting described adjustment magnitude of voltage.
9. the nonvolatile memory as described in claim 6,7 or 8, is characterized in that, described adjustment magnitude of voltage is positive voltage value or negative value, and described voltage generating unit comprises:
First regulates subelement, for when described adjustment magnitude of voltage is positive voltage value, on the basis of initial word line voltage and P trap voltage, increase word line voltage and the P trap voltage of storage unit according to described adjustment magnitude of voltage, the final word line voltage needed when generating erase operation and P trap voltage also export;
Second regulates subelement, for when described adjustment magnitude of voltage is negative value, on the basis of initial word line voltage and P trap voltage, reduce word line voltage and the P trap voltage of storage unit according to described adjustment magnitude of voltage, the final word line voltage needed when generating erase operation and P trap voltage also export.
10. an erasing voltage production method for nonvolatile memory, is characterized in that, comprising:
Monitoring supply voltage, and described supply voltage is converted to corresponding logic control signal by preset rules;
When described logic control signal changes, obtain the change difference of supply voltage, and generate erasing voltage adjustment signal according to this difference;
Export according to described erasing voltage adjustment signal and adjust magnitude of voltage accordingly;
The final word line voltage needed when exporting erase operation according to described adjustment magnitude of voltage and P trap voltage;
Wherein, in the erase period, word-line voltage and the PWELL voltage of the non-volatile memory cells be not wiped free of is regulated, and consistent with the change direction of supply voltage;
In the erase period, regulate word-line voltage and the PWELL voltage of the non-volatile memory cells be wiped free of simultaneously, and consistent with the change direction of supply voltage.
11. methods as claimed in claim 10, it is characterized in that, described supply voltage is simulating signal, and described logic control signal is digital signal; Described preset rules is the supply voltage of at least two numerical intervals and the one-to-one relationship of at least two Different Logic control signals.
12. methods as claimed in claim 11, it is characterized in that, described voltage adjustment signal comprises reference voltage and multiple parameter, and the described step according to erasing voltage adjustment signal output corresponding adjustment magnitude of voltage comprises:
Generate according to described reference voltage and multiple parameter and adjust magnitude of voltage accordingly;
Export described adjustment magnitude of voltage.
13. methods as described in claim 10,11 or 12, it is characterized in that, described adjustment magnitude of voltage is positive voltage value or negative value, and the step of the described final word line voltage that needs when exporting erase operation according to adjustment magnitude of voltage and P trap voltage comprises:
When described adjustment magnitude of voltage is positive voltage value, on the basis of initial word line voltage and P trap voltage, increase word line voltage and the P trap voltage of storage unit according to described adjustment magnitude of voltage, the final word line voltage needed when generating erase operation and P trap voltage also export;
When described adjustment magnitude of voltage is negative value, on the basis of initial word line voltage and P trap voltage, reduce word line voltage and the P trap voltage of storage unit according to described adjustment magnitude of voltage, the final word line voltage needed when generating erase operation and P trap voltage also export.
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| CN104572324A (en) * | 2013-10-11 | 2015-04-29 | 光宝科技股份有限公司 | Solid-state storage device and control method thereof |
| CN103839586B (en) * | 2014-03-17 | 2017-04-05 | 上海华虹宏力半导体制造有限公司 | The method of adjustment of nonvolatile memory erasing voltage |
| CN117407927B (en) * | 2023-12-15 | 2024-03-22 | 山东万里红信息技术有限公司 | Hard disk data destruction method, computer equipment and storage medium |
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| US6166960A (en) * | 1999-09-24 | 2000-12-26 | Microchip Technology, Incorporated | Method, system and apparatus for determining that a programming voltage level is sufficient for reliably programming an eeprom |
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