CN102622955B - Dot-matrix VFD (Vacuum Fluorescent Display) screen protection circuit - Google Patents
Dot-matrix VFD (Vacuum Fluorescent Display) screen protection circuit Download PDFInfo
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- CN102622955B CN102622955B CN201210094402.3A CN201210094402A CN102622955B CN 102622955 B CN102622955 B CN 102622955B CN 201210094402 A CN201210094402 A CN 201210094402A CN 102622955 B CN102622955 B CN 102622955B
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Abstract
The invention discloses a dot-matrix VFD (Vacuum Fluorescent Display) screen protection circuit comprising a resistor R1, a capacitor C1, a triode Q1, a resistor R4, a capacitor C2, a resistor R5, a resistor R7 and a triode Q2. A periodical clock signal CLKA emitted by a CPU (Central Processing Unit) is subjected to direct-current blocking and coupling by the resistor R1 and the capacitor C1 to control the base electrode of the triode Q1; a +5V power supply is connected with an emitter of the triode Q1; a collector of the triode Q1 is connected with the capacitor C2 via the resistor R4; the collector of the triode Q1 is connected with a base electrode of the triode Q2 via the resistor R4 and the resistor R5; the +5V power supply is connected with the collector of the triode Q2 via the resistor R7; the collector of the triode Q2 is connected with a switch pin BKGO of a dot-matrix VFD screen; and the emitter BKG of the triode Q2 is connected with an I/O (Input/Output) pin of the CPU. According to the dot-matrix VFD screen protection circuit disclosed by the invention, stable periodical pulse signals are always used for controlling a clock pin CLKA of the dot-matrix VFD screen, and a switch pin BKG of the VFD screen is controlled by judging whether a clock wire is combined with the protection circuit and the CPU, so that the on/off of the VFD screen is controlled.
Description
Technical field
The present invention relates to dot matrix VFD display screen, the dot matrix VFD display screen that especially internal high-voltage drives, is mainly used in the demonstration of family's power amplifier.
Background technology
Home theater amplifier function development in recent years, function is more and more, exercisable function is also more and more, because VFD has fast response time, the advantage that contrast is high, still be widely used at present every field, in order to realize good man-machine interface, at present a lot of home theater amplifiers have all adopted dot matrix VFD to do to show, so that realize the prompting of various animation effects and Chinese character, because driving, dot matrix needs a lot of mouth lines, therefore this series products is substantially all the form that internal high-voltage drives chip, outside is only controlled by the data port of one group of serial, transmit data, inside completes and shows the work refreshing, therefore in the pause of the data clock in debug process and power down process, often there will be the high bright spot of short time, thereby burn black fluorescent powder, cause the damage of display screen, greatly reduce the serviceable life of display screen.
Summary of the invention
Technical matters to be solved by this invention is to provide a kind of dot matrix VFD display screen holding circuit, the serviceable life that can improve dot matrix VFD display screen.
For solving the problems of the technologies described above, technical scheme of the present invention is: a kind of dot matrix VFD display screen holding circuit, comprises resistance R 1, capacitor C 1, triode Q1, resistance R 4, capacitor C 2, resistance R 5, resistance R 7 and triode Q2; The periodicity clock signal clk A that CPU sends is the base stage every straight coupling capacitance control triode Q1 by resistance R 1 and capacitor C 1; + 5V power supply is connected with the emitter of triode Q1, and the collector of triode Q1 is connected with capacitor C 2 by resistance R 4; The collector of triode Q1 is connected with the base stage of triode Q2 by resistance R 4, resistance R 5; + 5V power supply is connected with the collector of triode Q2 by resistance R 7, and the collector of triode Q2 is connected with the switch pin BKGO of dot matrix VFD display screen, and the emitter BKG of triode Q2 is connected with the I/O pin of CPU;
CPU controls periodically conducting of triode Q1 by the periodicity clock signal clk A sending;
After the conducting of triode Q1 periodicity ,+5V power supply charges to capacitor C 2 by triode Q1 and resistance R 4;
In the time that holding circuit receives the CLKA signal that CPU sends, the I/O human hair combing waste of CPU goes out low level the emitter BKG current potential of triode Q2 is dragged down, and making the switch pin BKGO being connected with triode Q2 collector is low level, and now VFD shields normal demonstration work;
When machine is during in holding state, the I/0 pin output high level of CPU, draws high the emitter BKG current potential of triode Q2, and making the switch pin BKGO being connected with triode Q2 collector is high level, and display screen is closed;
In the time of normal machines shutdown or power down suddenly; the periodicity clock signal clk A that holding circuit receives is low level; now triode Q1, Q2 cut-off; now because+5V power supply has reason or the high level of large electric capacity accumulate; the switch pin BKGO being connected with triode Q2 collector is so just high level, has turned off demonstration at once, avoids because of power down suddenly; in the middle of causing display screen, there is local Chang Liang, thus protection VFD display screen.
As improvement, between described+5V power supply and the base stage of triode Q1, be provided with resistance R 3, between the base stage of triode Q1 and ground, be provided with resistance R 2; Between the base stage of triode Q2 and ground, be provided with resistance R 6.
As improvement, described holding circuit also comprises the switching power supply being electrically connected with external communication, described switching power supply comprises filtering circuit and mu balanced circuit, described mu balanced circuit comprises voltage stabilizing diode D1, the D2 of triode Q4 and two series connection, described mu balanced circuit is connected with the base stage of triode Q4, the collector of triode Q4 is connected with filtering circuit, and the emitter of triode Q4 is connected with the energization pins of dot matrix VFD display screen; Described switching power supply also comprises triode Q3, and the base stage of triode Q3 is connected with the standby signal control pin STBY of CPU, and collector is connected with the base stage of triode Q4, and emitter is connected with ground.CPU sends standby signal STBY and controls triode Q3 conducting by resistance R 11, and the conducting of triode Q3 causes triode Q4 cut-off, thereby cuts off the anode high voltage+45V of display screen, also turns off filament simultaneously, protects thoroughly display screen.
As improvement, between described external communication electricity and filtering circuit, be provided with diode D600, D601, the effect of diode is that alternating current is become to direct current.
As improvement, described CPU is 32 high-speed CPUs, and model is STM32F101.
The beneficial effect that the present invention compared with prior art brought is:
Utilize the clock pin CLKA of reference mark configuration VFD display screen is stable cyclic pulse signal always; control the switch pin BKGO of display screen by have or not join protection circuit and the CPU that judge this clock lines; thereby control the Push And Release of display screen, play the effect of protection display screen.
Brief description of the drawings
Fig. 1 is circuit frame figure of the present invention.
Fig. 2 is CPU pin schematic diagram.
Fig. 3 is circuit theory diagrams of the present invention.
Embodiment
Below in conjunction with Figure of description, the invention will be further described.
As shown in Figure 1, 2, the present embodiment is taking the dot matrix VFD display screen of the MN12864K of Japanese Noritake company as example, this display screen is 128 × 64 dot matrix screen, internal high-voltage drives, digital signal access, can directly connect high speed MCU, the present embodiment CPU is 32 high-speed CPUs, and model is STM32F101.
As shown in Figure 3, dot matrix VFD display screen holding circuit comprises resistance R 1 ~ R7, capacitor C 1, capacitor C 2, triode Q1, triode Q2.The periodicity clock signal clk A that CPU sends is the base stage every straight coupling capacitance control triode Q1 by resistance R 1 and capacitor C 1; + 5V power supply is connected with the emitter of triode Q1, and the collector of triode Q1 is connected with capacitor C 2 by resistance R 4; The collector of triode Q1 is connected with the base stage of triode Q2 by resistance R 4, resistance R 5; + 5V power supply is connected with the collector of triode Q2 by resistance R 7, and the collector of triode Q2 is connected with the switch pin BKGO of dot matrix VFD display screen, and the emitter BKG of triode Q2 is connected with the I/O pin of CPU; Between described resistance R 3 be arranged on+5V power supply and the base stage of triode Q1; Resistance R 2 is arranged between the base stage and ground of triode Q1; Resistance R 6 is arranged between the base stage and ground of triode Q2.
Described holding circuit also comprises the switching power supply being electrically connected with external communication, and described switching power supply comprises filtering circuit and mu balanced circuit.Described filtering circuit is made up of capacitor C in parallel 601, C602, and external communication electricity is powered to mu balanced circuit by diode D600, D601, filtering circuit.Described mu balanced circuit comprises voltage stabilizing diode D1, the D2 of triode Q4 and two series connection, described mu balanced circuit is connected with the base stage of triode Q4, the collector of triode Q4 is connected with filtering circuit, and the emitter of triode Q4 is connected with the energization pins of dot matrix VFD display screen.Described switching power supply also comprises triode Q3, and the base stage of triode Q3 is connected with the standby signal control pin STBY of CPU, and collector is connected with the base stage of triode Q4, and emitter is connected with ground.
Principle of work of the present invention is as follows:
CPU controls periodically conducting of triode Q1 by the periodicity clock signal clk A sending;
After the conducting of triode Q1 periodicity ,+5V power supply charges to capacitor C 2 by triode Q1 and resistance R 4;
In the time that holding circuit receives the CLKA signal that CPU sends, the I/O human hair combing waste of CPU goes out low level the emitter BKG current potential of triode Q2 is dragged down, and making the switch pin BKGO being connected with triode Q2 collector is low level, and now VFD shields normal demonstration work;
When machine is during in holding state, the I/0 pin output high level of CPU, draws high the emitter BKG current potential of triode Q2, and making the switch pin BKGO being connected with triode Q2 collector is high level, and display screen is closed; CPU sends standby signal STBY and controls triode Q3 conducting by resistance R 11 simultaneously, and the conducting of triode Q3 causes triode Q4 cut-off, thereby cuts off the anode high voltage+45V of display screen, also turns off filament simultaneously, protects thoroughly display screen.
In the time of normal machines shutdown or power down suddenly; the periodicity clock signal clk A that holding circuit receives is low level; now triode Q1, Q2 cut-off; now because+5V power supply has reason or the high level of large electric capacity accumulate; the switch pin BKGO being connected with triode Q2 collector is so just high level, has turned off demonstration at once, avoids because of power down suddenly; in the middle of causing display screen, there is local Chang Liang, thus protection VFD display screen.
In the machine simulating developer stage; can be often to interrupt sending number to display screen at debugging problem, so also be easy to cause the local Chang Liang of display screen to cause damaging, once periodically clock signal clk A stops sending number; just turn off display screen and show, thereby reach protection effect at once.
Claims (5)
1. a dot matrix VFD display screen holding circuit, comprises resistance R 1, capacitor C 1, triode Q1, resistance R 4, capacitor C 2, resistance R 5, resistance R 7 and triode Q2; It is characterized in that: the periodicity clock signal clk A that CPU sends is the base stage every straight coupling capacitance control triode Q1 by resistance R 1 and capacitor C 1; + 5V power supply is connected with the emitter of triode Q1, and the collector of triode Q1 is connected with capacitor C 2 by resistance R 4; The collector of triode Q1 is connected with the base stage of triode Q2 by resistance R 4, resistance R 5; + 5V power supply is connected with the collector of triode Q2 by resistance R 7, and the collector of triode Q2 is connected with the switch pin BKGO of dot matrix VFD display screen, and the emitter BKG of triode Q2 is connected with the I/O pin of CPU;
CPU controls the conducting of triode Q1 by the periodicity clock signal clk A sending;
After triode Q1 conducting ,+5V power supply charges to capacitor C 2 by triode Q1 and resistance R 4;
Capacitor C 2 is controlled the conducting of triode Q2 again by resistance R 5;
In the time that holding circuit receives the CLKA signal that CPU sends, the I/O human hair combing waste of CPU goes out low level the emitter BKG current potential of triode Q2 is dragged down, and making the switch pin BKGO being connected with triode Q2 collector is low level, and now VFD shields normal demonstration work;
When machine is during in holding state, the I/0 pin output high level of CPU, draws high the emitter BKG current potential of triode Q2, and making the switch pin BKGO being connected with triode Q2 collector is high level, and display screen is closed;
In the time of normal machines shutdown or power down suddenly; the periodicity clock signal clk A that holding circuit receives is low level; now triode Q1, Q2 cut-off; now because+5V power supply has reason or the high level of large electric capacity accumulate; the switch pin BKGO being connected with triode Q2 collector is so just high level, has turned off demonstration at once.
2. dot matrix VFD display screen holding circuit according to claim 1, is characterized in that: between described+5V power supply and the base stage of triode Q1, be provided with resistance R 3, be provided with resistance R 2 between the base stage of triode Q1 and ground; Between the base stage of triode Q2 and ground, be provided with resistance R 6.
3. dot matrix VFD display screen holding circuit according to claim 1, it is characterized in that: described holding circuit also comprises the switching power supply being electrically connected with external communication, described switching power supply comprises filtering circuit and mu balanced circuit, described mu balanced circuit comprises voltage stabilizing diode D1, the D2 of triode Q4 and two series connection, described mu balanced circuit is connected with the base stage of triode Q4, the collector of triode Q4 is connected with filtering circuit, and the emitter of triode Q4 is connected with the energization pins of dot matrix VFD display screen; Described switching power supply also comprises triode Q3, and the base stage of triode Q3 is connected with the standby signal control pin STBY of CPU, and collector is connected with the base stage of triode Q4, and emitter is connected with ground.
4. dot matrix VFD display screen holding circuit according to claim 3, is characterized in that: between described external communication electricity and filtering circuit, be provided with diode D600, D601.
5. dot matrix VFD display screen holding circuit according to claim 1, is characterized in that: described CPU is 32 high-speed CPUs, and model is STM32F101.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201210094402.3A CN102622955B (en) | 2012-04-01 | 2012-04-01 | Dot-matrix VFD (Vacuum Fluorescent Display) screen protection circuit |
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| CN201210094402.3A CN102622955B (en) | 2012-04-01 | 2012-04-01 | Dot-matrix VFD (Vacuum Fluorescent Display) screen protection circuit |
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| CN102622955B true CN102622955B (en) | 2014-06-25 |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5596471A (en) * | 1995-05-05 | 1997-01-21 | Advanced Micro Devices, Inc. | Adjustable undervoltage trip fault interrupt circuit |
| CN200983242Y (en) * | 2006-12-13 | 2007-11-28 | 上海三星真空电子器件有限公司 | A driving power circuit of vacuum fluorescence display |
| CN201359838Y (en) * | 2009-01-22 | 2009-12-09 | 辉创电子科技(苏州)有限公司 | Automatic brightness regulation device of VFD display screen |
| CN102263539A (en) * | 2010-05-28 | 2011-11-30 | 洛克威尔自动控制技术股份有限公司 | Variable frequency drive and methods for filter capacitor fault detection |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7558031B2 (en) * | 2003-05-02 | 2009-07-07 | Abb Inc. | Intelligent automatic bypass for a motor control device |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5596471A (en) * | 1995-05-05 | 1997-01-21 | Advanced Micro Devices, Inc. | Adjustable undervoltage trip fault interrupt circuit |
| CN200983242Y (en) * | 2006-12-13 | 2007-11-28 | 上海三星真空电子器件有限公司 | A driving power circuit of vacuum fluorescence display |
| CN201359838Y (en) * | 2009-01-22 | 2009-12-09 | 辉创电子科技(苏州)有限公司 | Automatic brightness regulation device of VFD display screen |
| CN102263539A (en) * | 2010-05-28 | 2011-11-30 | 洛克威尔自动控制技术股份有限公司 | Variable frequency drive and methods for filter capacitor fault detection |
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Owner name: WUZHOU HENGSHENG ELECTRONIC TECHNOLOGY CO., LTD. G Free format text: FORMER OWNER: WUZHOU HENGSHENG ELECTRONIC TECHNOLOGY CO., LTD. GUANGZHOU YANGCHENG PRECISION ELECTRONIC CO., LTD. Effective date: 20140905 |
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Effective date of registration: 20140905 Address after: 510800 Guangzhou street, Xinhua Street, Huadu District, Guangdong, China, No. 8, Jinghu Patentee after: Guoguang Electric Co., Ltd. Patentee after: Wuzhou Hengsheng Electronic Technology Co., Ltd. Patentee after: GUANGDONG MEIJIA AUDIO DEVELOPMENT CO., LTD. Address before: 510800 Guangzhou street, Xinhua Street, Huadu District, Guangdong, China, No. 8, Jinghu Patentee before: Guoguang Electric Co., Ltd. Patentee before: Wuzhou Hengsheng Electronic Technology Co., Ltd. Patentee before: Guangzhou Yangcheng Precision Electronics Co., Ltd. |