CN102621974B - Industrial automatic real-time control device and method based on communication bus - Google Patents
Industrial automatic real-time control device and method based on communication bus Download PDFInfo
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Abstract
The invention relates to an industrial automatic real-time control device based on a communication bus. The industrial automatic real-time control device comprises an FPGA (Field Programmable Gata Array) chip, a driving chip and a physical layer chip, wherein the FPGA chip is connected with the physical layer chip through the driving chip; the physical layer chip is connected with a real-time communication bus; and the FPGA chip comprises a PCI-E (Peripheral Component Interconnect-E) bus interface, an embedded soft core module, a driving controller module, an FIFO (First In First Out) buffer module and a PCI-E data pack resolving module. The invention further relates to a method for implementing industrial automatic real-time control based on a communication bus by using the device. In the device and the method disclosed by the invention, the FPGA chip is adopted, so that appropriate resources can be selected flexibly according to user requirements in comparison to a DSP (Digital Signal Processor) chip in the prior art; meanwhile, the device and the method have the advantages of high expandability, high processing speed, high integration degree, easiness for updating and the like; the industrial automatic real-time control device based on the communication bus has a simple structure and low cost; and the method is easy and convenient to apply, and has a wide application range.
Description
Technical field
The present invention relates to technical field of industrial automatic control, particularly the communication bus technical field, specifically refer to a kind of real-time control apparatus of industrial automation based on communication bus and control method.
Background technology
Existing servomotor is controlled and mainly is based on the driving control system that (Pulse) controlled in pulse, a kind of numerically controlled driver based on Industrial Ethernet occurs in recent years.With respect to former pulse, control, RTEX (Realtime Express, passage real-time) has the advantages such as low cost, high-performance, simplicity of design, reliability are high, easy expansion.As shown in Figure 1, be the schematic diagram of above-mentioned two kinds of communication mechanisms.
In addition, with traditional driver, compare, the driving control system of the A5N driver of employing PANASONIC as shown in Figure 2 has synchronism preferably, the solution of the A5N driver that PANASONIC provides is to use specific dsp chip+mnm1221 type to drive chip+PHY chip, wherein the mnm1221 chip comprises the communication protocol of driver, uses dsp chip to mainly contain following advantage:
The bus interface of A, these several specific dsp chips is identical with the interface of mnm1221, and directly being connected is addressable mnm1221.
B, dsp chip comprise the low-speed module commonly used such as fixing SPI, IIC, timer, UART, can directly use.
The digital processing ability of C, dsp chip is more powerful, can on the basis of communication, do some digital signal processing functions.
But there is following shortcoming equally in the solution of using PANASONIC to provide, is also advantage of the present invention:
A, dsp chip can only be specifically several, and resource is fixed, and washability is poor, and dsp chip is more expensive.And fpga chip has versatility, the difference only be resource the number, according to user's demand, can select neatly the fpga chip of appropriate resources.
B, extendability a little less than, only can design the simple module such as SPI, IIC, timer, UART, and can not design some complicated communication interfaces as USB, PCI, PCIe, CAN, Ethernet and PHY, PLB bus, AXI bus etc.
C, processing speed are lower.
D, integrated level are low, and circuit design is comparatively complicated.
E, DSP only can carry out software upgrading, can't reconfigure by HardwareUpgring.
The term table of comparisons:
● Pulse, pulse;
● RTEX, Realtime Express, passage real-time;
● DSP, Digital Signal Processor, digital signal processor;
● PHY, Physical Layer, Physical layer; Physical layer protocol;
● SPI, Serial Peripheral Interface, Serial Peripheral Interface (SPI);
● IIC, i.e. I2C, a kind of multidirectional control bus structure;
● Timer, timer;
● UART, Universal Asynchronous Receiver/Transmitter, Universal Asynchronous Receiver & dispensing device;
● FPGA, Field Programmable Gate Array, field programmable gate array;
● PCI-E (PCIe, PCI express), PCI of new generation (Peripheral Component Interconnect) high speed bus interface;
● PLB, Processor Local Bus, processor local bus;
● AXI, Advanced eXtensible Interface, advanced extensible interface bus;
● GPIO, General Purpose Input Output, universal input/output;
● FIFO, First Input First Output, First Input First Output;
● Microblaze, Embedded Soft Core title;
● ISC, interrupt source controller, interrupt source controller.
Summary of the invention
The objective of the invention is to have overcome above-mentioned shortcoming of the prior art, provide a kind of and can be neatly according to the user, need to select appropriate resources, extendability is strong, processing speed is fast, integrated level is high, is easy to upgrading, simple in structure, with low cost, the real-time control apparatus of the industrial automation based on communication bus and the method that have wide range of applications.
In order to realize above-mentioned purpose, the real-time control apparatus of the industrial automation based on communication bus of the present invention has following formation:
Should comprise based on the industrial automation real-time control apparatus of communication bus: fpga chip, driving chip and physical chip, described fpga chip connects described physical chip by described driving chip, described fpga chip comprises a PCI-E bus interface at least, and described physical chip connects the real-time Communication for Power bus.
Be somebody's turn to do in the industrial automation real-time control apparatus based on communication bus, described fpga chip also comprises one or more in USB interface, CAN bus interface, Ethernet interface, phy interface, PLB bus interface and AXI bus interface.
Be somebody's turn to do in the industrial automation real-time control apparatus based on communication bus, described fpga chip also comprises the embedded software core module, the driving governor module, fifo buffer module and PCI-E packet parsing module, described embedded software core module, the driving governor module, the fifo buffer module all connects the fpga chip internal bus, described PCI-E packet parsing module is connected in described fifo buffer module, this PCI-E packet parsing module also connects described PCI-E bus interface and outside manual impulsator, described driving governor module also connects described driving chip.
Be somebody's turn to do in the industrial automation real-time control apparatus based on communication bus, described embedded software core module comprises: GPIO unit, timer unit, URAT unit and user's configuration data unit, described GPIO unit, timer unit, URAT unit and user's configuration data unit all are connected in described fpga chip internal bus.
Be somebody's turn to do in the industrial automation real-time control apparatus based on communication bus, described fpga chip also comprises the interruption control module, and described interruption control module is connected between described driving governor module and described fpga chip internal bus.
Be somebody's turn to do in the industrial automation real-time control apparatus based on communication bus, described driving governor module comprises interconnective Bus Interface Unit and user logic unit, described Bus Interface Unit is connected in described fpga chip internal bus, and described user logic unit connects described driving chip.
Be somebody's turn to do in the industrial automation real-time control apparatus based on communication bus, described driving governor module also comprises the interrupt source controller unit, and described interrupt source controller unit is connected in described user logic unit.
Be somebody's turn to do in the industrial automation real-time control apparatus based on communication bus, described fifo buffer module comprises a plurality of multiple-input, multiple-output formation passages, the output terminal of described PCI-E packet parsing module connects described each multiple-input, multiple-output formation passage, and the output terminal of described each multiple-input, multiple-output formation passage all connects described embedded software core module by described fpga chip internal bus.
Be somebody's turn to do in the industrial automation real-time control apparatus based on communication bus, described PCI-E packet parsing module comprises: the PCI-E data interface unit, PCI-E has read and write message unit, PCI-E interrupts producing control module, AB phase cell encoder, the monostable trigger element of encoder zero-crossing, the address bus decoding unit, the clock division unit, the DA control module, the pulse interpolation unit, the input port expanding element, the output port expanding element, interrupt buffer control unit, hardware timer unit and pulse data bag resolution unit, described PCI-E data interface unit connect respectively described PCI-E and have read and write message unit, PCI-E interrupts producing control module and pulse data bag resolution unit, and described pulse data bag resolution unit connects respectively described AB phase cell encoder, the monostable trigger element of encoder zero-crossing, the address bus decoding unit, the clock division unit, the DA control module, the pulse interpolation unit, the input port expanding element, the output port expanding element, interrupt buffer control unit, the hardware timer unit, fifo buffer module and described fpga chip internal bus.
Be somebody's turn to do in the industrial automation real-time control apparatus based on communication bus, described fpga chip internal bus is PLB bus or AXI bus.
The present invention also provides a kind of and utilizes described device to realize the industrial automation real-time control method based on bus, and described method comprises the following steps:
(1) described embedded software core module judges that described fifo buffer module is whether not empty and be not in steering state, if, enter step (2), if not, enter step (3);
(2) described embedded software core module reads the data in described fifo buffer module, and enters step (3);
(3) described PCI-E packet parsing module is carried out the numerical control calculating operation;
(4) described driving governor module outage is served and is write and reading out data in described driving chip;
(5) described driving governor module determines whether to receive for the third time data, if, data are sent to PC by described PCI-E bus interface, if not, do not send.
This realizes that in the industrial automation real-time control method based on bus, it is communication protocol numerical control calculating operation or smoothing filter numerical control calculating operation that described PCI-E packet parsing module is carried out the numerical control calculating operation.
This is realized in the industrial automation real-time control method based on bus, described fifo buffer module comprises a plurality of multiple-input, multiple-output formation passages, the output terminal of described PCI-E packet parsing module connects described each multiple-input, multiple-output formation passage, the output terminal of described each multiple-input, multiple-output formation passage all connects described embedded software core module by described fpga chip internal bus, and described communication protocol numerical control calculating operation specifically comprises the following steps:
(31-1) described PCI-E packet parsing module judges whether to carry out reverse operating, if, enter step (31-2), if not, enter step (31-3);
(31-2) described PCI-E packet parsing module is carried out and is oppositely mended 0 operation, then enters step (31-7);
(31-3) described PCI-E packet parsing module judges whether that described each multiple-input, multiple-output formation passage is not all for empty, if, enter step (31-4), if not, enter step (31-7);
(31-4) described PCI-E packet parsing module reads 9 binary pulse data from described fifo buffer module;
(31-5) described PCI-E packet parsing module has been converted to symbol long data by described 9 binary pulse data;
(31-6) described PCI-E packet parsing module judges whether to carry out reverse operating, if return to step (31-2); If not, enter step (31-7);
(31-7) described PCI-E packet parsing module is from described PCI-E bus interface reading out data.
This realizes that in the industrial automation real-time control method based on bus, described smoothing filter numerical control calculating operation comprises the following steps:
(32-1) described PCI-E packet parsing module amplifies 100 times by the data A that reads and is 100A;
(32-2) described PCI-E packet parsing module judges whether it is to carry out smoothing filter to circulate for the first time, if, enter step (32-3), if not, enter step (32-4);
(32-3) described PCI-E packet parsing module loopy moving buffer memory, and by data stuffing to described buffer memory;
(32-4) described PCI-E packet parsing module output data 100A/12 or 100A/12+1, and enter step (32-5);
(32-5) described PCI-E packet parsing module determines whether the tenth secondary cycle, if, finish smoothing filter numerical control calculating operation, if not, return to step (32-2).
Adopted the real-time control apparatus of the industrial automation based on communication bus of this invention, because it comprises fpga chip, drives chip and physical chip, described fpga chip connects described physical chip by described driving chip, described fpga chip comprises a PCI-E bus interface at least, and described physical chip connects the real-time Communication for Power bus.And described fpga chip also comprises embedded software core module, driving governor module, fifo buffer module and PCI-E packet parsing module.Make and utilize device of the present invention to realize in the method for controlling in real time based on the industrial automation of communication bus, can first utilize the embedded software core module to judge that described fifo buffer module is whether not empty and be not in steering state, determine whether to read the data in described fifo buffer module by the embedded software core module, after by PCI-E packet parsing module, carrying out the numerical control calculating operation again, by driving governor module outage, serve and write and reading out data in described driving chip, realization is controlled in real time based on the industrial automation of communication bus.Because device and method of the present invention has adopted fpga chip, therefore, it is compared to dsp chip of the prior art, can according to the user, need to select appropriate resources neatly, have simultaneously extendability strong, processing speed is fast, and integrated level is high, be easy to the advantages such as upgrading, and the real-time control apparatus of the industrial automation based on communication bus of the present invention and method, its apparatus structure is simple, with low cost, its method application is easy, and range of application is also comparatively extensive.
The accompanying drawing explanation
Fig. 1 is the structural representation of the driving control system for servomotor control of the prior art.
The structural representation of the solution of the employing A5N driver that Fig. 2 provides for PANASONIC in prior art.
Fig. 3 is the structural representation that the present invention is based on the industrial automation real-time control apparatus of communication bus.
Fig. 4 is the structural representation of fpga chip that the present invention is based on the industrial automation real-time control apparatus of communication bus.
Fig. 5 is the flow chart of steps that the present invention is based on the industrial automation real-time control method of communication bus.
Fig. 6 is mnm1221_controller (driver module control) the IP bus bridge structural representation the present invention is based in the fpga chip of industrial automation real-time control apparatus of communication bus.
Fig. 7 is the PCIe stone part framework schematic diagram the present invention is based in the fpga chip of industrial automation real-time control apparatus of communication bus.
Fig. 8 is the schematic diagram that the present invention is based on the PCI Express data interface module in the fpga chip of industrial automation real-time control apparatus of communication bus.
Fig. 9 the present invention is based on the module for reading and writing operational flowchart of the PCI Express data interface module in the fpga chip of industrial automation real-time control apparatus of communication bus.
Figure 10 the present invention is based on the schematic diagram that PCI Express in the fpga chip of industrial automation real-time control apparatus of communication bus has read and write the message module.
Figure 11 the present invention is based on PCI Express in the fpga chip of industrial automation real-time control apparatus of communication bus to have read and write the message module and according to the PCIe agreement, send the operational flowchart of corresponding data message.
Figure 12 the present invention is based on the schematic diagram that PCI Express in the fpga chip of industrial automation real-time control apparatus of communication bus interrupts producing control module.
Figure 13 the present invention is based on the interrupt acknowledge cycle figure that PCI Express in the fpga chip of industrial automation real-time control apparatus of communication bus interrupts producing control module.
Figure 14 is the schematic diagram that the present invention is based on the Nctudio packet parsing module in the fpga chip of industrial automation real-time control apparatus of communication bus.
Figure 15 is the program flow diagram of fpga chip that the present invention is based on the industrial automation real-time control apparatus of communication bus.
Figure 16 is the data flow schematic diagram while adopting the industrial automation real-time control apparatus that the present invention is based on communication bus to carry out periodical communication.
The overall flow schematic diagram of Figure 17 for adopting the industrial automation real-time control apparatus the present invention is based on communication bus to communicate.
Figure 18 is smoothing filter model schematic diagram of the prior art.
Figure 19 is for adopting the data transmitting period schematic diagram of the smoothing filter in Figure 18.
Figure 20 is the smoothing filter model schematic diagram the present invention is based in the industrial automation real-time control method of communication bus.
Figure 21 is for adopting the data transmitting period schematic diagram of the smoothing filter in Figure 20.
Figure 22 is the real-time control apparatus of the industrial automation based on communication bus of the present invention structural representation in actual applications.
Embodiment
In order more clearly to understand technology contents of the present invention, describe in detail especially exemplified by following examples.
Refer to shown in Figure 3ly, be the structural representation of the industrial automation real-time control apparatus that the present invention is based on communication bus.
In one embodiment, should based on the industrial automation real-time control apparatus of communication bus, comprise fpga chip, drive chip and physical chip.Described fpga chip connects described physical chip by described driving chip, and described fpga chip comprises a PCI-E bus interface at least, and described physical chip connects the real-time Communication for Power bus.And as shown in Figure 4, described fpga chip also comprises embedded software core module, driving governor module, fifo buffer module and PCI-E packet parsing module, and one or more in USB interface, CAN bus interface, Ethernet interface, phy interface, PLB bus interface and AXI bus interface.Described embedded software core module, driving governor module, fifo buffer module all connect the fpga chip internal bus, described PCI-E packet parsing module is connected in described fifo buffer module, this PCI-E packet parsing module also connects described PCI-E bus interface and outside manual impulsator, and described driving governor module also connects described driving chip.Described fpga chip internal bus is PLB bus or AXI bus.
Utilize the described device of this embodiment to realize the industrial automation real-time control method based on bus, as shown in Figure 5, comprise the following steps:
(1) described embedded software core module judges that described fifo buffer module is whether not empty and be not in steering state, if, enter step (2), if not, enter step (3);
(2) described embedded software core module reads the data in described fifo buffer module, and enters step (3);
(3) described PCI-E packet parsing module is carried out the numerical control calculating operation;
(4) described driving governor module outage is served and is write and reading out data in described driving chip;
(5) described driving governor module determines whether to receive for the third time data, if, data are sent to PC by described PCI-E bus interface, if not, do not send.
In a kind of more preferably embodiment, described embedded software core module comprises: GPIO unit, timer unit, URAT unit and user's configuration data unit, described GPIO unit, timer unit, URAT unit and user's configuration data unit all are connected in described fpga chip internal bus.
More preferably in embodiment, described fpga chip also comprises the interruption control module at another kind, and described interruption control module is connected between described driving governor module and described fpga chip internal bus.
At another more preferably in embodiment, described driving governor module comprises interconnective Bus Interface Unit and user logic unit, described Bus Interface Unit is connected in described fpga chip internal bus, and described user logic unit connects described driving chip.Wherein, described driving governor module also comprises the interrupt source controller unit, and described interrupt source controller unit is connected in described user logic unit.
At another more preferably in embodiment, described fifo buffer module comprises a plurality of multiple-input, multiple-output formation passages, the output terminal of described PCI-E packet parsing module connects described each multiple-input, multiple-output formation passage, and the output terminal of described each multiple-input, multiple-output formation passage all connects described embedded software core module by described fpga chip internal bus.
More preferably in embodiment, described PCI-E packet parsing module comprises: the PCI-E data interface unit at another kind again, PCI-E has read and write message unit, PCI-E interrupts producing control module, AB phase cell encoder, the monostable trigger element of encoder zero-crossing, the address bus decoding unit, the clock division unit, the DA control module, the pulse interpolation unit, the input port expanding element, the output port expanding element, interrupt buffer control unit, hardware timer unit and pulse data bag resolution unit, described PCI-E data interface unit connect respectively described PCI-E and have read and write message unit, PCI-E interrupts producing control module and pulse data bag resolution unit, and described pulse data bag resolution unit connects respectively described AB phase cell encoder, the monostable trigger element of encoder zero-crossing, the address bus decoding unit, the clock division unit, the DA control module, the pulse interpolation unit, the input port expanding element, the output port expanding element, interrupt buffer control unit, the hardware timer unit, fifo buffer module and described fpga chip internal bus.
In a kind of preferred embodiment, it is communication protocol numerical control calculating operation or smoothing filter numerical control calculating operation that described step (3) PCI-E packet parsing module is carried out the numerical control calculating operation.Wherein, described communication protocol numerical control calculating operation specifically comprises the following steps:
(31-1) described PCI-E packet parsing module judges whether to carry out reverse operating, if, enter step (31-2), if not, enter step (31-3);
(31-2) described PCI-E packet parsing module is carried out and is oppositely mended 0 operation, then enters step (31-7);
(31-3) described PCI-E packet parsing module judges whether that described each multiple-input, multiple-output formation passage is not all for empty, if, enter step (31-4), if not, enter step (31-7);
(31-4) described PCI-E packet parsing module reads 9 binary pulse data from described fifo buffer module;
(31-5) described PCI-E packet parsing module has been converted to symbol long data by described 9 binary pulse data;
(31-6) described PCI-E packet parsing module judges whether to carry out reverse operating, if return to step (31-2); If not, enter step (31-7);
(31-7) described PCI-E packet parsing module is from described PCI-E bus interface reading out data.
And described smoothing filter numerical control calculating operation comprises the following steps:
(32-1) described PCI-E packet parsing module amplifies 100 times by the data A that reads and is 100A;
(32-2) described PCI-E packet parsing module judges whether it is to carry out smoothing filter to circulate for the first time, if, enter step (32-3), if not, enter step (32-4);
(32-3) described PCI-E packet parsing module loopy moving buffer memory, and by data stuffing to described buffer memory;
(32-4) described PCI-E packet parsing module output data 100A/12 or 100A/12+1, and enter step (32-5);
(32-5) described PCI-E packet parsing module determines whether the tenth secondary cycle, if, finish smoothing filter numerical control calculating operation, if not, return to step (32-2).
In actual applications, the circuit design of the real-time control apparatus of the industrial automation based on communication bus of the present invention mainly comprises: control chip is fpga chip, compared to the design proposal that PANASONIC in prior art provides, circuit of the present invention has improved integrated level, has simplified circuit.So in circuit design, take 4 layers of isolation scheme, can meet the EMC performance fully.
When PCB designs, followed following standard:
A, differential signal, impedance Control and parallel isometric wiring;
B, Tx signal and Rx signal cloth, different two-layer, prevent from producing at grade loop;
C, bus plane and stratum are cut apart, carried out interference and insulation by network transformer;
The length of D, bus is tried one's best parallel and isometric.
In addition, for convenient plug control card, on circuit board specialized designs two grooves.
FPAG design of the present invention mainly comprises two parts: hardware design (using VHDL), software (using the C language).
Hardware design mainly comprises following three parts:
The first, as shown in figure 22, customize the soft core of Microblaze, soft core adds the following IP kernel heart: GPIO, timer, UART, SPI.
Wherein, the GPIO module can be exported and control mnm1221 driving chip and PHY chip reset, and input can be read communications status (link signal).
Timer can accurate timing, and precision is 12ns (clock is 83.333333MHz).
URAT is mainly in order to print Debugging message.Also used in addition the mdm module also can debugging software, with better function.
SPI can read user's configuration data.
The second, customize two User Defined IP:mnm1221controller and FIFO_CON.
Because the PLB bus that soft core is used is different with the bus that mnm1221 is used, so can't directly be connected.This IP of mnm1221_controller (driver module control) is a bus bridge, its structure as shown in Figure 6, by mnm1221_controller, the soft register of endorsing with direct read/write mnm1221.Mnm1221_controller also comprises 1 ISC in addition, can the self-defined interruption of leading subscriber.
FIFO_CON is an impact damper, and packet is issued soft core by impact damper after resolving.Impact damper is comprised of a plurality of passages, and each passage is a fifo queue, and corresponding axle.The status signal of all FIFO is put into to a register, can be read to judge by Microblaze the state of current FIFO.
The the 3rd: the use of PCIe stone and the parsing of packet.
PCIe stone part framework as shown in Figure 7.
Wherein AB phase scrambler, the monostable triggering of encoder zero-crossing, address bus decoding, clock division, DA control, pulse interpolation, input port expansion, output port expansion, be all to use for a long time in sundry item, working stability, the module of technology maturation.
PM932A1 control card function is with reference to the existing PCIMC63A control card realization of company, and employing Xilinx Spartan-6 serial model No. is that the chip of XC6SLX45T is realized.
PCIExpress data interface module PIO_32_RX_ENGINE.vhd as shown in Figure 8, while resetting, state machine is in the PIO_32_RX_RST_STATE state, after resetting and finishing, state machine carries out state transition according to the command header form of PCIe packet, supports 32 bit data read-write operations and 64 bit data read-write operations.Its operational flowchart as shown in Figure 9.
PCIExpress has read and write message module PIO_32_TX_ENGINE.vhd as shown in figure 10, while resetting, state machine is in the PIO_32_TX_RST_STATE state, end resets, state machine is read operation or IO write operation according to current operation, according to the PCIe agreement, send corresponding data message, its operational flowchart is as shown in 11.
PCIExpress interrupts producing control module PCIE_INTER.vhd as shown in figure 12.The end that resets, when P35=' 0 ', the interrupt control state machine brings into operation, and supports two kinds of interrupt modes: MSI interrupt mode and Legacy interrupt mode.The MSI interrupt mode is that edging trigger is effective, therefore produces and interrupts without cancelling; And the Legacy interrupt mode is level triggering mode, therefore need to cancel interruption by control module in interrupting, when PC sends first group of data to control card, look-at-me is cancelled.Be spaced apart 1.5ms break period.Interrupt acknowledge cycle figure as shown in figure 13.
As shown in figure 14, notebook data bag parsing module is to design according to the data communication protocol of PCIMC63A to Nctudio packet parsing module PCIMC63A_CTROL.vhd, so that can the compatible function of the PCIMC63A control card of company at present.In order to ensure data, can write the data buffer of FIFO.
Hardware timer module CH365_COUNTER.vhd: be a 3.84us timer, timing by obtaining hardware timer in driver is for the corrective system time, there is this function the CH365 inside of original PCIMC6A control card, for the driving of compatible with PCI MC6A control card, PM932A1 has realized this function with the form of FPGA code.
Buffering control module INTERRUPT_CONTROL.vhd: control the function compatibility with the buffering of original PCIMC6A control card.When without buffering, FIFO can only accept one group of data; When FIFO had buffering, the degree of depth of FIFO was 32.Namely when without when buffering, be masked as with the sky of FIFO the foundation that judges whether to produce interruption; When buffering is arranged, with expiring of FIFO, be masked as the foundation that judges whether to produce interruption.
In software section, the program flow diagram of control device of the present invention, as shown in figure 15, after sequence of operations, connection setup, software mainly operate in the RUNNING state.The user carries out periodical communication at the RUNNING state.
During periodical communication, upper computer software sends data to and receives in data buffering (FIFO), and then control card removes to read FIFO, then, after a series of computings, issues driver, simultaneously the data that receive from driver is sent to the transmission data buffering.Data during periodical communication flow as shown in figure 16.Wherein NC calculating (numerical control calculating) mainly comprises communication protocol and smoothing filter.
Communication needs to consider following problem:
A, oppositely the time, after the pulse data that needs to wait for upper one-period all is sent completely, could send reverse command pulse.Otherwise can cause pulse data to be lost, not reach reverse maximum position.Because what program was used is the level Four smoothing filter, so, now must continuous 3 cycle interpolation pulses 0.
The format conversion of B, pulse data.The data of taking out from FIFO are 9 binary pulse data axes.buf (direction position+8 digit pulse data), the direction of the direction in previous cycle and current period need to be recorded in respectively in last_symbol and now_symbol, and pulse data has been converted to symbol long data (signed long int), finally obtain get_data.
C, consider special circumstances: when returning former point operation, system can be configured to non-cushioned situation, and FIFO there will be sky, now needs to mend 0.Control card and PC power on asynchronously in addition, also can cause FIFO to be read sky, now also should mend 0.
The core concept of communication is to set up data channel, considers to obtain the distinct methods of data under different situations.The integrated communication flow process as shown in figure 17.
Common smoothing filter, as shown in figure 18, according to processing, reduce acceleration for number of pulses, and velocity variations slows down, to reduce motor oscillating.As shown in Figure 19, the level Four smoothing filter is divided into four cycles transmissions by data, and in fact smoothing filter buffering progression is higher, and smooth effect is better, but also there will be a drawback simultaneously, and the data response time is elongated, the real-time variation.Through facts have proved, the level Four smoothing filter effect that the present invention uses is most suitable.
The cycle of considering the order of host computer transmitted is 1.5ms, and the exectorial communication cycle of A5N driver is 0.5ms, becomes three cycles to send the Data Division of one-period so also need.Top smoothing filter basic model can be used after need to changing.Smoothing filter model after change of the present invention is illustrated in fig. 20 shown below.As shown in figure 21, the smoothing filter after improvement can the different transceiving data for the treatment of cycle.Once, data 0.5ms exports once the input of one-period 1.5ms data.If there is a data A to enter smoothing filter, at first amplify 100 times, loop-around data of every execution output 100A/12 or 100A/12+1 (1 be the accumulation of decimal), such 12 circulations data 100A afterwards are output fully, and at next cycle by new data cover.Design is the accurate control for the driver that takes full advantage of A5N like this, reaches the purpose of sending out the decimal pulse.Pulse equivalency in software is S, and the pulse equivalency of A5N driver is P, P=S/100, and namely S is 100 times of P.This multiple is used for tentative, because will be divided exactly by four, this multiple is necessary for 4 multiple.Like this pulse equivalency of driver and software being arranged to difference, is in order to send out decimal pulse (rate smoothing when speed is slow).
Adopted the real-time control apparatus of the industrial automation based on communication bus of this invention, because it comprises fpga chip, drives chip and physical chip, described fpga chip connects described physical chip by described driving chip, described fpga chip comprises a PCI-E bus interface at least, and described physical chip connects the real-time Communication for Power bus.And described fpga chip also comprises embedded software core module, driving governor module, fifo buffer module and PCI-E packet parsing module.Make and utilize device of the present invention to realize in the method for controlling in real time based on the industrial automation of communication bus, can first utilize the embedded software core module to judge that described fifo buffer module is whether not empty and be not in steering state, determine whether to read the data in described fifo buffer module by the embedded software core module, after by PCI-E packet parsing module, carrying out the numerical control calculating operation again, by driving governor module outage, serve and write and reading out data in described driving chip, realization is controlled in real time based on the industrial automation of communication bus.Because device and method of the present invention has adopted fpga chip, therefore, it is compared to dsp chip of the prior art, can according to the user, need to select appropriate resources neatly, have simultaneously extendability strong, processing speed is fast, and integrated level is high, be easy to the advantages such as upgrading, and the real-time control apparatus of the industrial automation based on communication bus of the present invention and method, its apparatus structure is simple, with low cost, its method application is easy, and range of application is also comparatively extensive.
In this instructions, the present invention is described with reference to its specific embodiment.But, still can make various modifications and conversion obviously and not deviate from the spirit and scope of the present invention.Therefore, instructions and accompanying drawing are regarded in an illustrative, rather than a restrictive.
Claims (13)
1. real-time control apparatus of the industrial automation based on communication bus, it is characterized in that, the described real-time control apparatus of industrial automation based on communication bus comprises: fpga chip, drive chip and physical chip, described fpga chip connects described physical chip by described driving chip, described fpga chip comprises a PCI-E bus interface at least, described physical chip connects the real-time Communication for Power bus, described fpga chip also comprises the embedded software core module, the driving governor module, fifo buffer module and PCI-E packet parsing module, described embedded software core module, the driving governor module, the fifo buffer module all connects the fpga chip internal bus, described PCI-E packet parsing module is connected in described fifo buffer module, this PCI-E packet parsing module also connects described PCI-E bus interface and outside manual impulsator, described driving governor module also connects described driving chip.
2. the real-time control apparatus of the industrial automation based on communication bus according to claim 1, it is characterized in that, described fpga chip also comprises one or more in USB interface, CAN bus interface, Ethernet interface, phy interface, PLB bus interface and AXI bus interface.
3. the real-time control apparatus of the industrial automation based on communication bus according to claim 1, it is characterized in that, described embedded software core module comprises: GPIO unit, timer unit, URAT unit and user's configuration data unit, described GPIO unit, timer unit, URAT unit and user's configuration data unit all are connected in described fpga chip internal bus.
4. the real-time control apparatus of the industrial automation based on communication bus according to claim 1, it is characterized in that, described fpga chip also comprises the interruption control module, and described interruption control module is connected between described driving governor module and described fpga chip internal bus.
5. the real-time control apparatus of the industrial automation based on communication bus according to claim 1, it is characterized in that, described driving governor module comprises interconnective Bus Interface Unit and user logic unit, described Bus Interface Unit is connected in described fpga chip internal bus, and described user logic unit connects described driving chip.
6. the real-time control apparatus of the industrial automation based on communication bus according to claim 5, it is characterized in that, described driving governor module also comprises the interrupt source controller unit, and described interrupt source controller unit is connected in described user logic unit.
7. the real-time control apparatus of the industrial automation based on communication bus according to claim 1, it is characterized in that, described fifo buffer module comprises a plurality of multiple-input, multiple-output formation passages, the output terminal of described PCI-E packet parsing module connects described each multiple-input, multiple-output formation passage, and the output terminal of described each multiple-input, multiple-output formation passage all connects described embedded software core module by described fpga chip internal bus.
8. the real-time control apparatus of the industrial automation based on communication bus according to claim 1, is characterized in that, described PCI-E packet parsing module comprises: the PCI-E data interface unit, PCI-E has read and write message unit, PCI-E interrupts producing control module, AB phase cell encoder, the monostable trigger element of encoder zero-crossing, the address bus decoding unit, the clock division unit, the DA control module, the pulse interpolation unit, the input port expanding element, the output port expanding element, interrupt buffer control unit, hardware timer unit and pulse data bag resolution unit, described PCI-E data interface unit connect respectively described PCI-E and have read and write message unit, PCI-E interrupts producing control module and pulse data bag resolution unit, and described pulse data bag resolution unit connects respectively described AB phase cell encoder, the monostable trigger element of encoder zero-crossing, the address bus decoding unit, the clock division unit, the DA control module, the pulse interpolation unit, the input port expanding element, the output port expanding element, interrupt buffer control unit, the hardware timer unit, fifo buffer module and described fpga chip internal bus.
9. according to the described real-time control apparatus of industrial automation based on communication bus of any one in claim 1 to 8, it is characterized in that, described fpga chip internal bus is PLB bus or AXI bus.
10. one kind is utilized device claimed in claim 1 to realize the industrial automation real-time control method based on bus, it is characterized in that, described fpga chip also comprises the embedded software core module, the driving governor module, fifo buffer module and PCI-E packet parsing module, described embedded software core module, the driving governor module, the fifo buffer module all connects the fpga chip internal bus, described PCI-E packet parsing module is connected in described fifo buffer module, this PCI-E packet parsing module also connects described PCI-E bus interface and outside manual impulsator, described driving governor module also connects described driving chip, described method comprises the following steps:
(1) described embedded software core module judges that described fifo buffer module is whether not empty and be not in steering state, if, enter step (2), if not, enter step (3);
(2) described embedded software core module reads the data in described fifo buffer module, and enters step (3);
(3) described PCI-E packet parsing module is carried out the numerical control calculating operation;
(4) described driving governor module outage is served and is write and reading out data in described driving chip;
(5) described driving governor module determines whether to receive for the third time data, if, data are sent to PC by described PCI-E bus interface, if not, do not send.
11. realization according to claim 10 is based on the industrial automation real-time control method of bus, it is characterized in that, it is communication protocol numerical control calculating operation or smoothing filter numerical control calculating operation that described PCI-E packet parsing module is carried out the numerical control calculating operation.
12. realization according to claim 11 is based on the industrial automation real-time control method of bus, it is characterized in that, described fifo buffer module comprises a plurality of multiple-input, multiple-output formation passages, the output terminal of described PCI-E packet parsing module connects described each multiple-input, multiple-output formation passage, the output terminal of described each multiple-input, multiple-output formation passage all connects described embedded software core module by described fpga chip internal bus, and described communication protocol numerical control calculating operation specifically comprises the following steps:
(31-1) described PCI-E packet parsing module judges whether to carry out reverse operating, if, enter step (31-2), if not, enter step (31-3);
(31-2) described PCI-E packet parsing module is carried out and is oppositely mended 0 operation, then enters step (31-7);
(31-3) described PCI-E packet parsing module judges whether that described each multiple-input, multiple-output formation passage is not all for empty, if, enter step (31-4), if not, enter step (31-7);
(31-4) described PCI-E packet parsing module reads 9 binary pulse data from described fifo buffer module;
(31-5) described PCI-E packet parsing module has been converted to symbol long data by described 9 binary pulse data;
(31-6) described PCI-E packet parsing module judges whether to carry out reverse operating, if return to step (31-2); If not, enter step (31-7);
(31-7) described PCI-E packet parsing module is from described PCI-E bus interface reading out data.
13. realization according to claim 11, based on the industrial automation real-time control method of bus, is characterized in that, described smoothing filter numerical control calculating operation comprises the following steps:
(32-1) described PCI-E packet parsing module amplifies 100 times by the data A that reads and is 100A;
(32-2) described PCI-E packet parsing module judges whether it is to carry out smoothing filter to circulate for the first time, if, enter step (32-3), if not, enter step (32-4);
(32-3) described PCI-E packet parsing module loopy moving buffer memory, and by data stuffing to described buffer memory;
(32-4) described PCI-E packet parsing module output data 100A/12 or 100A/12+1, and enter step (32-5);
(32-5) described PCI-E packet parsing module determines whether the tenth secondary cycle, if, finish smoothing filter numerical control calculating operation, if not, return to step (32-2).
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| CN103605625B (en) * | 2013-11-29 | 2016-04-06 | 山东大学 | Based on the control method of the Nor Flash chip of AXI bus |
| JP5877826B2 (en) * | 2013-12-16 | 2016-03-08 | ファナック株式会社 | Numerical control device with servo output delay means |
| CN104714910B (en) * | 2013-12-17 | 2018-11-30 | 研祥智能科技股份有限公司 | The method and system of adaptive configuration PCIE bus interface |
| EP2927763B1 (en) * | 2014-04-04 | 2019-06-19 | Abb Ag | System and method for an optimized operation of real-time embedded solutions in industrial automation |
| US10127183B2 (en) * | 2016-06-30 | 2018-11-13 | Fisher Controls International Llc | Systems and methods for provisioning devices operating in industrial automation environments |
| CN106201982A (en) * | 2016-07-01 | 2016-12-07 | 深圳市紫光同创电子有限公司 | A kind of PCI Express IP kernel |
| CN108075882A (en) * | 2016-11-14 | 2018-05-25 | 航天信息股份有限公司 | Cipher card and its encipher-decipher method |
| WO2019113726A1 (en) * | 2017-12-11 | 2019-06-20 | 深圳配天智能技术研究院有限公司 | Motion controller and motion control method |
| CN108572551A (en) * | 2018-04-23 | 2018-09-25 | 广东水利电力职业技术学院（广东省水利电力技工学校） | A kind of Industrial Embedded Control System based on EtherCAT buses |
| CN109379262B (en) * | 2018-09-30 | 2021-03-23 | 天津市英贝特航天科技有限公司 | Dual-redundancy CAN bus communication card and method for PCIe interface |
| CN110457042A (en) * | 2019-07-18 | 2019-11-15 | 广州健飞通信有限公司 | A kind of module integrated system with third party's analytic technique |
| CN112035389B (en) * | 2020-08-28 | 2022-08-23 | 西安微电子技术研究所 | PLB-AXI bus conversion bridge and working method thereof |
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