CN102621478B - Dynamic test device and system of radio-frequency front-end chip - Google Patents
Dynamic test device and system of radio-frequency front-end chip Download PDFInfo
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- CN102621478B CN102621478B CN201210089304.0A CN201210089304A CN102621478B CN 102621478 B CN102621478 B CN 102621478B CN 201210089304 A CN201210089304 A CN 201210089304A CN 102621478 B CN102621478 B CN 102621478B
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Abstract
The embodiment of the invention discloses a dynamic test device and system of a radio-frequency front-end chip. The system comprises a host computer and a dynamic test device, wherein the host computer is used for editing and storing control sequences of all required test items for the dynamic test; during the dynamic test process, a control sequence corresponding to the current test item is transmitted to the dynamic test device; the dynamic test device is used for receiving and storing the control sequence transmitted by the host computer and corresponding to the current test item; a corresponding control order is sequentially scheduled according to an execution time of each control order in the control sequence corresponding to the current test item to be transmitted to a tested radio-frequency front-end chip. By adopting the embodiment, the radio-frequency front-end chip can be separated from a baseband chip, and the dynamic performance of the radio-frequency front-end chip can be independently tested; and the device and the system are high in flexibility, and the efficiency and effect on testing the dynamic performances of the radio-frequency front-end chip can be greatly improved.
Description
Technical field
The present invention relates to mobile communication technology field, particularly relate to a kind of dynamic checkout unit and system of radio frequency front end chip.
Background technology
Radio frequency front end chip and baseband chip are all the core components of mobile terminal.Wherein, baseband chip is for the synthesis of the baseband signal that is about to transmitting, or the baseband signal receiving is decoded; Baseband signal refer to that information source sends not through the raw electrical signal of ovennodulation.Radio frequency front end chip is responsible for radio-frequency receiving-transmitting; Concrete, during transmitting, pass the baseband signal of coming from baseband chip, by up-conversion, frequency modulation (PFM), on frequency higher, that be applicable to antenna transmission, is transmitted by antenna wireless; During reception, the radiofrequency signal receiving from antenna, by down coversion, be converted to baseband signal, pass to baseband chip and process.
Conventionally, the ideal baseband signal that baseband chip sends, need to become radiofrequency signal through the various processing of radio frequency front end chip, then send.Conversion and processing procedure in the middle of this, be not completely desirable, and the radiofrequency signal of therefore finally launching, can exist certain deviation (as frequency error, phase error etc.).Same, in receiving course, radio frequency front end chip receives aerial radiofrequency signal, and by its down coversion, the processing such as in addition filtering, amplification, change baseband signal into, pass to baseband chip and process.In the process of reception & disposal, equally also exist deviation.The above-mentioned various deviations that produce in process that transmit and receive, are that the characteristic by radio frequency front end chip itself causes, and cannot eliminate completely, and its degree size, can be used for weighing the performance of radio frequency front end chip.
Therefore, need to test the performance of radio frequency front end chip, thereby radio frequency front end chip be made to the assessment of quantification.Conventionally, for the performance test of radio frequency front end chip, comprise static properties test and dynamic performance testing two aspects.The test of static properties can be arranged on specific duty by radio frequency front end chip by manual, then its performance is tested.And the test of dynamic property need to be simulated the various sights in practical application, within the extremely short time, chip is carried out to the accurate a series of control of timing, this cannot realize by manual type.
In prior art, the dynamic property of radio frequency front end chip is tested, time delay relation that need to be between the precedence relationship of the various control sequences of radio frequency front end chip and steering order is as sequential template, and the mode by program Solidification is burnt in baseband chip.But in the time of need to modifying to control sequence or instruction time delay, need to remodify code, after recompiling, be burnt in baseband chip again.
And, in prior art, can only rely on the dynamic performance testing that baseband chip carries out radio frequency front end chip, make testing progress be limited by the progress of baseband chip, be unfavorable for the research and development of radio frequency front end chip and release market.
As can be seen here, existing radio frequency front end chip dynamic performance testing technology, its test process is more consuming time, complexity is high and versatility is not strong, makes tester need to expend a lot of time test platform is modified, efficiency and the effect of impact test.
Summary of the invention
In view of this, the object of the present invention is to provide a kind of dynamic checkout unit and system of radio frequency front end chip, can allow radio frequency front end chip depart from baseband chip, the dynamic property of independent test radio frequency front end chip; This Apparatus and system has higher dirigibility, has greatly improved efficiency and the effect of radio frequency front end chip dynamic performance testing.
The invention provides a kind of dynamic test system of radio frequency front end chip, described system comprises: host computer and dynamic checkout unit;
Described host computer connects tested radio frequency front end chip by dynamic checkout unit;
Described host computer, for editing and store the control sequence of the required all test items of dynamic test; In dynamic test process, send control sequence that current test item is corresponding to described dynamic checkout unit;
Described dynamic checkout unit, control sequence corresponding to current test item sending for receiving and preserve described host computer; And in dynamic test process, the execution time according to each steering order in control sequence corresponding to current test item, recall successively corresponding steering order, be sent to tested radio frequency front end chip.
Preferably, described dynamic checkout unit comprises: clock module, register module, task scheduling modules, data memory module, host computer interface module, RF data interface module and RF control interface module;
Described clock module, for generation of the clock of the required various frequencies of described dynamic checkout unit;
Described register module, control sequence corresponding to current test item sending for receive and preserve described host computer by described host computer interface module; And in dynamic test process, according to the dispatch command that is received from described task scheduling modules, recall corresponding steering order, by described RF control interface module, be sent to tested radio frequency front end chip;
Described task scheduling modules, in dynamic test process, controls the switching of described proving installation mode of operation; According to the execution time of each steering order in control sequence corresponding to current test item, to described register module, send dispatch command; Control startup and the operation to tested each input/output port of radio frequency front end chip of described RF data interface module and RF control interface module;
Described data memory module, the data of launching when storing described tested radio frequency front end chip transmission test and the logical credit data of receiving while receiving test;
Described host computer interface module, for realizing communicating by letter between described host computer and described proving installation;
Described RF data interface module, for leading to credit data to described tested radio frequency front end chip transmitting-receiving;
Described RF control interface module, for realizing the operation of described proving installation to the read-write register of described tested radio frequency front end chip and correlated inputs output port.
Preferably, described clock module adopts from the 26M of radio frequency front end chip input as synchronous clock source, by digital dock administration module DCM, produces the required synchronous clock of transceiving data under the major clock of described dynamic checkout unit work and different communication standard.
Preferably, the mode of operation of described proving installation comprises: single operational mode and circular flow pattern;
Described circular flow pattern is, all steering orders that the current test item of take is corresponding are a cycle, from article one steering order, start to carry out until the last item steering order, timer zero clearing, return to original state, from article one steering order, start to carry out again, so all steering orders are carried out in circulation;
Described single operational mode is, all steering orders that current test item is corresponding are carried out once, returns to idle condition.
Preferably, described data memory module comprises: data transmission unit and data receiver unit;
Described data transmission unit, for when the transmission test, data storage for download communication from described host computer in advance; When dynamic test runs to emission state, recall successively corresponding data, by described RF data interface module, be sent to described tested radio frequency front end chip;
Described data receiver unit, for when receiving test, receives and stores the logical credit data of described tested radio frequency front end chip; After Acceptance Tests waiting completes, the data that receive by passing described host computer back in described host computer interface module.
Preferably, described host computer interface module comprises two kinds of mode of operations: data communication mode and command communication pattern;
Under data communication mode, described host computer interface module operates described data memory module for described host computer;
Under command communication module, described host computer interface module operates described register module for described host computer.
The present invention also provides a kind of dynamic checkout unit of radio frequency front end chip, and described device is used for coordinating host computer to carry out dynamic test to tested radio frequency front end chip;
Described device comprises: clock module, register module, task scheduling modules, data memory module, host computer interface module, RF data interface module and RF control interface module;
Described clock module, for generation of the clock of the required various frequencies of described dynamic checkout unit;
Described register module, control sequence corresponding to current test item sending for receive and preserve described host computer by described host computer interface module; And in dynamic test process, according to the dispatch command that is received from described task scheduling modules, recall corresponding steering order, by described RF control interface module, be sent to tested radio frequency front end chip;
Described task scheduling modules, in dynamic test process, controls the switching of described proving installation mode of operation; According to the execution time of each steering order in control sequence corresponding to current test item, to described register module, send dispatch command; Control startup and the operation to tested each input/output port of radio frequency front end chip of described RF data interface module and RF control interface module;
Described data memory module, the logical credit data of launching when storing described tested radio frequency front end chip transmission test and the logical credit data of receiving while receiving test;
Described host computer interface module, for realizing communicating by letter between described host computer and described proving installation;
Described RF data interface module, for leading to credit data to described tested radio frequency front end chip transmitting-receiving;
Described RF control interface module, for realizing the operation of described proving installation to the read-write register of described tested radio frequency front end chip and correlated inputs output port.
Preferably, described clock module adopts from the 26M of radio frequency front end chip input as synchronous clock source, by digital dock administration module DCM, produces the required synchronous clock of transceiving data under the major clock of described dynamic checkout unit work and different communication standard.
Preferably, the mode of operation of described proving installation comprises: single operational mode and circular flow pattern;
Described circular flow pattern is, all steering orders that the current test item of take is corresponding are a cycle, from article one steering order, start to carry out until the last item steering order, timer zero clearing, return to original state, from article one steering order, start to carry out again, so all steering orders are carried out in circulation;
Described single operational mode is, all steering orders that current test item is corresponding are carried out once, returns to idle condition.
Preferably, described data memory module comprises: data transmission unit and data receiver unit;
Described data transmission unit, for when the transmission test, data storage for download communication from described host computer in advance; When dynamic test runs to emission state, recall successively corresponding data, by described RF data interface module, be sent to described tested radio frequency front end chip;
Described data receiver unit, for when receiving test, receives and stores the logical credit data of described tested radio frequency front end chip; After Acceptance Tests waiting completes, the data that receive by passing described host computer back in described host computer interface module.
Preferably, described host computer interface module comprises two kinds of mode of operations: data communication mode and command communication pattern;
Under data communication mode, described host computer interface module operates described data memory module for described host computer;
Under command communication module, described host computer interface module operates described register module for described host computer
According to specific embodiment provided by the invention, the invention discloses following technique effect:
In the embodiment of the present invention, needs debugging and the frequent part (being the control sequence of described tested radio frequency front end chip being carried out to the required all test items of dynamic test) of revising that needs are stored in host computer, in each dynamic test process, send control sequence that current test item is corresponding to described dynamic checkout unit; Described dynamic checkout unit receives the control sequence that current test item is corresponding, according to the execution time of each steering order in control sequence corresponding to current test item, recall successively corresponding steering order, be sent to tested radio frequency front end chip, realize the dynamic test to described tested radio frequency front end chip.
Thus, can allow radio frequency front end chip depart from baseband chip, the dynamic property of independent test radio frequency front end chip; And in the embodiment of the present invention, need debugging and often need the part of revising to be stored in host computer, even if need to modify to the execution time of control sequence or each steering order, also only need in the control software of host computer, modify, do not need dynamic checkout unit to carry out hardware modifications, make thus this Apparatus and system there is higher dirigibility, greatly improved efficiency and the effect of radio frequency front end chip dynamic performance testing.
Accompanying drawing explanation
Fig. 1 is the dynamic test system of the radio frequency front end chip described in the embodiment of the present invention one;
Fig. 2 is the dynamic test system of the radio frequency front end chip described in the embodiment of the present invention two.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, below in conjunction with the drawings and specific embodiments, the present invention is further detailed explanation.
In view of this, the object of the present invention is to provide a kind of dynamic checkout unit and system of radio frequency front end chip, can allow radio frequency front end chip depart from baseband chip, the dynamic property of independent test radio frequency front end chip; This Apparatus and system has higher dirigibility, has greatly improved efficiency and the effect of radio frequency front end chip dynamic performance testing.
The main inventive concept of the embodiment of the present invention is: needs debugging is separated with program curing with the part that often needs to revise.The hardware frame of the dynamic checkout unit of radio frequency front end chip is realized by program curing, as circuit structure of the hardware structure of task scheduling, various external interface, read-write register etc.Needs debugging and the frequent part (as the control sequence of all test items in dynamic test process) of revising that needs are kept in host computer, by upper computer software, writing the register of dynamic checkout unit realizes, can meet and not change under the prerequisite of proving installation hardware frame, the modification at any time to this part.In proving installation, be reserved with enough register space control sequence used and relevant time module when storing dynamic test.
With reference to Fig. 1, it is the dynamic test system structural drawing of the radio frequency front end chip described in the embodiment of the present invention one.As shown in Figure 1, described system comprises: host computer 10 and dynamic checkout unit 20.
Described host computer 10 connects tested radio frequency front end chip 30 by described dynamic checkout unit 20.
Described host computer 10, for store control sequence that described tested radio frequency front end chip 30 is carried out to the required all test items of dynamic test with; In dynamic test process, send control sequence that current test item is corresponding to described dynamic checkout unit 20.
Described dynamic checkout unit 20, control sequence corresponding to current test item sending for receiving and preserve described host computer 10; And in dynamic test process, the execution time according to each steering order in control sequence corresponding to current test item, recall successively corresponding steering order, be sent to tested radio frequency front end chip 30.
In the embodiment of the present invention, needs debugging and the frequent part (being the control sequence of described tested radio frequency front end chip 30 being carried out to the required all test items of dynamic test) of revising that needs are stored in host computer 10, in each dynamic test process, send control sequence that current test item is corresponding and relevant time module to described dynamic checkout unit 20; The control sequence that the current test item of described dynamic checkout unit 20 reception is corresponding and relevant time module, according to the execution time of each steering order in control sequence corresponding to current test item, recall successively corresponding steering order, be sent to tested radio frequency front end chip 30, realize the dynamic test to described tested radio frequency front end chip 30.
Thus, can allow radio frequency front end chip 30 depart from baseband chip, the dynamic property of independent test radio frequency front end chip; And in the embodiment of the present invention, needs debugging and the mode of the part that often needs to revise with register are realized, debugging and operating in host computer 10 of modification complete, even if need to modify to the execution time of control sequence or each steering order, also only need in the control software of host computer 10, modify, do not need dynamic checkout unit 20 to carry out hardware modifications, make thus this Apparatus and system there is higher dirigibility, greatly improved efficiency and the effect of radio frequency front end chip dynamic performance testing.
With reference to Fig. 2, it is the dynamic test system structural drawing of the radio frequency front end chip described in the embodiment of the present invention two.As shown in Figure 2, described system comprises: host computer 10 and dynamic checkout unit 20.
Described host computer 10 connects tested radio frequency front end chip 30 by described dynamic checkout unit 20.
Described host computer 10, for storing the control sequence of described tested radio frequency front end chip 30 being carried out to the required all test items of dynamic test; In dynamic test process, send control sequence that current test item is corresponding and relevant time module to described dynamic checkout unit 20.
Concrete, the part that needs debugging and frequent needs to revise in described host computer editor dynamic test, specifically comprises: the control sequence of described tested radio frequency front end chip 30 being carried out to the required all test items of dynamic test; After editting, host computer 10 is sent to described dynamic checkout unit 20 by configuration information corresponding to current test item (comprising control sequence that current test item is required and relevant time module), for recalling in dynamic test process.
Dynamic test for tested radio frequency chip 30, general each test item can comprise a lot of bar steering orders, every steering order all comprises the content of its palpus execution and the execution time of appointment, according to the execution time of each steering order, all steering orders that this test item is corresponding just form a control sequence.
Preferably, described host computer 10, the control sequence that can provide graphical interfaces to edit and store the required all test items of dynamic test for operating personnel.
It should be noted that, control sequence used when described tested radio frequency front end chip 30 is carried out to dynamic test, does not decide at the very start.Concrete, can be according to the design objective of tested radio frequency chip 30, first estimate a Utopian flow process, then tester is according to the actual conditions of test, the priority execution sequence of adjusting each steering order with and invoked time point, or add or leave out steering order, to reach the control sequence that meets test needs.Above-mentioned all adjustment processes are exactly to revise the value of register in the control software of host computer 10, and write the process that described dynamic checkout unit 20 is watched the output of tested radio frequency front end chip 30, and the effect that configuration reaches is revised in thus can be instant see.Once determine after control sequence and relevant time module, just all configurations for current test item can be saved, for test item of the same type, just can directly call configuration afterwards.
In the embodiment of the present invention, needs are debugged and often needed the operator placement of revising in host computer 10, the beneficial effect of doing is like this, can Analog Baseband chip for the control flow of radio frequency front end chip, realization can be revised the dynamic control of debugging flexibly, to reach the object improving the efficiency of radio frequency front end chip dynamic test and effect.
As shown in Figure 2, described dynamic checkout unit 20 comprises: clock module 201, register module 202, task scheduling modules 203, data memory module 204, host computer interface module 205, RF (Radio Frequency, radio frequency) data interface module 206 and RF control interface module 207.
Described clock module 201, for generation of the clock of the required various frequencies of described dynamic checkout unit 20.
Concrete, described clock module 201 adopts from the 26M of radio frequency chip input as synchronous clock source, by DCM (Digital Clock Managers, digital dock administration module), produce the required synchronous clock of transceiving data under the major clock of whole dynamic checkout unit 20 work and different communication standard.
Under GSM standard and TD-SCDMA standard and even TD-LTE standard, for the rate requirement of signal, be different.Therefore described in the embodiment of the present invention, dynamic checkout unit 20 also needs the difference according to standard, is operated under corresponding clock frequency, and therefore described clock module 201 can produce at least two kinds of clock frequencies.In actual applications, according to the current residing mode of operation of described dynamic checkout unit 20, select corresponding clock frequency.
Described register module 202, for being received and preserved the configuration information that current test item that described host computer 10 sends is corresponding (being control sequence that current test item is corresponding and relevant time module) by described host computer interface module 205; And in dynamic test process, according to the dispatch command that is received from described task scheduling modules 203, recall corresponding steering order, by described RF control interface module 207, be sent to tested radio frequency front end chip 30.
It should be noted that, in the embodiment of the present invention, described register module 202 can be read and write by host computer 10 softwares, does not relate to hardware modifications, therefore can realize fast reading and writing.
Described task scheduling modules 203, in dynamic test process, controls the switching of the mode of operation of described proving installation; According to the execution time of each steering order in control sequence corresponding to current test item, to described register module 202, send dispatch command, the timing that completes each steering order of dynamic test is called; Control startup and the operation to tested radio frequency front end chip 30 each input and output (IO) ports of described RF data interface module 206 and RF control interface module 207.
Wherein, described according to the execution time of each steering order in control sequence corresponding to current test item, to described register module 202, send dispatch commands, the timing that completes each steering order of dynamic test is called and is specially:
When carrying out dynamic test, the timer of described task scheduling modules 203 starts timing, send the first dispatch command to described register module 202, described register module 202 receives after described the first dispatch command, read article one steering order in the corresponding control sequence of current test item, wait for the arrival of described article one steering order execution time.
When the execution time of described article one steering order is arrived in timing, described task scheduling modules 203 sends the second dispatch command to described register module 202, described register module 202 receives after described the second dispatch command, described article one steering order is sent to tested radio frequency front end chip 30 operations, and read the second steering order in the corresponding control sequence of current test item, wait for the arrival of described second steering order execution time.
When the execution time of described second steering order is arrived in timing, described task scheduling modules 203 sends the 3rd dispatch command to described register module 202, described register module 202 receives after described the 3rd dispatch command, described the 3rd steering order is sent to tested radio frequency front end chip 30 operations, and read the 3rd steering order in the corresponding control sequence of current test item, wait for the arrival of described the 3rd steering order execution time.
The like, complete the timer-triggered scheduler to each steering order in the corresponding control sequence of current test item.
In the embodiment of the present invention, described register module 202 is according to the dispatch command that is received from described task scheduling modules 203, read in advance each steering order that current test item is corresponding and wait for the arrival of its execution time, can effectively avoid reading steering order and carry out the time delay during this steering order to reality from register module 202, make when the execution time of each steering order reaches, can move immediately this steering order, reach the object that every steering order can accurate timing.
Need to further illustrate: the mode of operation of described proving installation comprises: single operational mode and circular flow pattern.
Described circular flow pattern refers to, all steering orders that the current test item of take is corresponding are a cycle, from article one steering order, start to carry out until the last item steering order, then timer zero clearing, get back to original state, from article one steering order, start to carry out again, so all steering orders are carried out in circulation.This mode of operation is applicable to according to communication protocol, carry out in analog wireless communication the process of data transmit-receive.For example, the transmitting-receiving of being undertaken by time slot under TD-SCDMA standard, or the form happening suddenly under GSM standard.
Described single operational mode refers to: only all steering orders corresponding to current test item are carried out once, then returned to idle condition.Now described tested radio frequency front end chip rests on the state while executing the last item steering order, can verify thus the impact of the operation of certain a series of steering order on tested radio frequency front end chip.
Described data memory module 204, the logical credit data of launching when storing described tested radio frequency front end chip 30 transmission test and the logical credit data of receiving while receiving test.
Concrete, described data memory module comprises: data transmission unit and data receiver unit.
Described data transmission unit, for when the transmission test, data storage for download communication from described host computer in advance; When dynamic test runs to emission state, recall successively corresponding data, by described RF data interface module, be sent to described tested radio frequency front end chip.
Described data receiver unit, for when receiving test, receives and stores the logical credit data of described tested radio frequency front end chip; After Acceptance Tests waiting completes, the data that receive by passing described host computer back in described host computer interface module.
When transmission test, described proving installation 20 is downloading data from described host computer 10 in advance, and be stored in described data memory module 204, when dynamic test runs to emission state, from described data memory module 204, recall successively corresponding data, by described RF data interface module 206, be sent to described tested radio frequency front end chip 30.
When receiving test, described proving installation 20 is stored in the data that are received from described tested radio frequency front end chip 30 in described data memory module 204, after Acceptance Tests waiting completes, the data that receive by passing described host computer back in described host computer interface module 205, for follow-up data analysis work.
Described host computer interface module 205, for realizing communicating by letter between described host computer 10 and described proving installation 20.
It should be noted that, described host computer interface module 205 comprises data communication and two kinds of operational modules of command communication.Wherein, under data communication mode, described host computer 10 directly operates the data memory module 204 of described proving installation 20.Under command communication module, the register module 202 of 10 pairs of described proving installations 20 of described host computer operates.Can realize bus-sharing function thus, save hardware resource.
Described RF data interface module 206, for leading to credit data to described tested radio frequency front end chip 30 transmitting-receivings.
Concrete, described RF data interface module 206 can carry out switch data transmission mode according to current communication standard.According to current general standard on the market, under TD standard, adopt 10bit parallel interface, under GSM standard, adopt DIGRF interface.
In order to simplify tester, edit the flow process of data source for test, in described data memory module 203, the transmitting data of storage, is original base band data.When transmission test, described RF data interface module 206, according to the difference of communication standard, is processed the data of reading from described data memory module 203 respectively.Concrete, under TD-SCDMA standard, described RF data interface module 206 is first sent the data of reading into Pulse shaped filter, sends to tested radio frequency front end chip after filter process again; Under GSM standard, described RF data interface module 206 first adds interface protocol information according to DIGRF agreement by the base band data of reading, then sends to tested radio frequency front end chip.
Described RF control interface module 207, controls for realizing the read-write register of 20 pairs of described tested radio frequency front end chips 30 of proving installation and the operation of corresponding I port.
Generally, the read-write register of described tested radio frequency front end chip 30 adopts MOTOROLASPI interface and DIGRF interface, and described RF control interface module 207 can need to be switched according to practical application.In the time need to testing the radio frequency front end chip of other types interface, only need the interface type of the corresponding described RF control interface of change module 207, do not need whole proving installation to carry out too much modification.
In the embodiment of the present invention, employing is solidificated in hardware frame in described dynamic checkout unit 20, the control sequence part that needs in dynamic test debug process often to revise, mode with register module 202 realizes, in dynamic checkout unit 20, build a memory capacity enough large, the register module 202 that structure is fixing, after building, the hardware of whole dynamic checkout unit 20 will not need to change again.During dynamic test, only need edit control sequence by host computer 10, and in each dynamic test process, send control sequence that current test item is corresponding to described dynamic checkout unit 20; Described dynamic checkout unit 20 receives control sequence corresponding to current test item, according to the execution time of each steering order in control sequence corresponding to current test item, recall successively corresponding steering order, be sent to tested radio frequency front end chip 30, realize the dynamic test to described tested radio frequency front end chip 30.When test completes, the current control sequence editting can be stored in host computer 10, avoid causing after dynamic checkout unit 20 power down the loss of content of registers.
Below the course of work of the dynamic test system described in the embodiment of the present invention is described in detail.
After described dynamic checkout unit 20 powers on, in idle condition (IDLE), now host computer 10 carries out following operation:
(1) edit the required control sequence of current dynamic test, and set the execution time of each steering order.
(2) after verifying that by the mode of single step run each step (being each steering order) of described control sequence is carried out, the residing state of described tested radio frequency front end chip 30.
(3) in download transmission test, need the data that are sent to tested radio frequency front end chip to described dynamic checkout unit 20; Or upload and receive the data that receive in test from described tested radio frequency front end chip 30.
(4) configure the correlation parameter of described dynamic checkout unit 20, as the frequency of operation of interface, switching RF control interface module etc.
(5) preserve the required control sequence of current test and relevant time module, or the configuration keeping in test before loading.
Under above-mentioned idle condition, after the required configuration of dynamic test process is set, the control software by host computer 10 makes described dynamic checkout unit 20 enter operational mode (RUN).First, the control software of host computer 10 writes configuration information corresponding to current test item setting in the register module 202 of described dynamic checkout unit 20, then the task scheduling modules 203 of described dynamic checkout unit 20 is started working, when running to execution time corresponding to certain steering order during point, carry out this steering order, be the operation that 20 pairs of tested radio frequency front end chips 30 of dynamic checkout unit are correlated with, such as writing the register of radio frequency front end chip 30 or changing level of corresponding IO port etc.
The mode of operation of described dynamic checkout unit 20 comprises two kinds: single operational mode and circular flow pattern.These two kinds of mode of operations can be tackled different testing requirements.
When selecting circular flow pattern, all steering orders that the current test item of take is corresponding are a cycle, from article one steering order, start to carry out until the last item steering order, then timer zero clearing, get back to original state, from article one steering order, start to carry out again, so all steering orders are carried out in circulation.This mode of operation is applicable to according to communication protocol, carry out in analog wireless communication the process of data transmit-receive.For example, the transmitting-receiving of being undertaken by time slot under TD-SCDMA standard, or the form happening suddenly under GSM standard.
When selecting single operational mode, only all steering orders corresponding to current test item are carried out once, then return to idle condition.Now described tested radio frequency front end chip 30 rests on the state while executing the last item steering order, the impact of the operation that can verify thus certain a series of steering order on tested radio frequency front end chip 30.
It should be noted that, in dynamic test process, once described dynamic checkout unit 20 enters operational mode, between the control software of described host computer 10 and dynamic checkout unit 20, by not needing, carry out again any artificial control, there will be no the mutual of any data between the two, all operations to tested radio frequency front end chip 30 are controlled and all will automatically be completed by described dynamic checkout unit 20.Can reduce greatly tester's operation element amount thus, make it be absorbed in analysis and the record of test phenomenon, not need proving installation more to operate.
Above to the dynamic checkout unit of a kind of radio frequency front end chip provided by the present invention and system, be described in detail, applied specific case herein principle of the present invention and embodiment are set forth, the explanation of above embodiment is just for helping to understand method of the present invention and core concept thereof; Meanwhile, for one of ordinary skill in the art, according to thought of the present invention, all will change in specific embodiments and applications.In sum, this description should not be construed as limitation of the present invention.
Claims (10)
1. a dynamic test system for radio frequency front end chip, is characterized in that, described system comprises: host computer and dynamic checkout unit;
Described host computer connects tested radio frequency front end chip by dynamic checkout unit;
Described host computer, for editing and store the control sequence of the required all test items of dynamic test; In dynamic test process, send control sequence that current test item is corresponding to described dynamic checkout unit;
Described dynamic checkout unit, control sequence corresponding to current test item sending for receiving and preserve described host computer; And in dynamic test process, the execution time according to each steering order in control sequence corresponding to current test item, recall successively corresponding steering order, be sent to tested radio frequency front end chip;
Described dynamic checkout unit comprises: clock module, register module, task scheduling modules, data memory module, host computer interface module, RF data interface module and RF control interface module;
Described clock module, for generation of the clock of the required various frequencies of described dynamic checkout unit;
Described register module, control sequence corresponding to current test item sending for receive and preserve described host computer by described host computer interface module; And in dynamic test process, according to the dispatch command that is received from described task scheduling modules, recall corresponding steering order, by described RF control interface module, be sent to tested radio frequency front end chip;
Described task scheduling modules, in dynamic test process, controls the switching of described proving installation mode of operation; According to the execution time of each steering order in control sequence corresponding to current test item, to described register module, send dispatch command; Control startup and the operation to tested each input/output port of radio frequency front end chip of described RF data interface module and RF control interface module;
Described data memory module, the data of launching when storing described tested radio frequency front end chip transmission test and the logical credit data of receiving while receiving test;
Described host computer interface module, for realizing communicating by letter between described host computer and described proving installation;
Described RF data interface module, for leading to credit data to described tested radio frequency front end chip transmitting-receiving;
Described RF control interface module, for realizing the operation of described proving installation to the read-write register of described tested radio frequency front end chip and correlated inputs output port.
2. the dynamic test system of radio frequency front end chip according to claim 1, it is characterized in that, described clock module adopts from the 26M of radio frequency front end chip input as synchronous clock source, by digital dock administration module DCM, produces the required synchronous clock of transceiving data under the major clock of described dynamic checkout unit work and different communication standard.
3. the dynamic test system of radio frequency front end chip according to claim 1, is characterized in that, the mode of operation of described proving installation comprises: single operational mode and circular flow pattern;
Described circular flow pattern is, all steering orders that the current test item of take is corresponding are a cycle, from article one steering order, start to carry out until the last item steering order, timer zero clearing, return to original state, from article one steering order, start to carry out again, so all steering orders are carried out in circulation;
Described single operational mode is, all steering orders that current test item is corresponding are carried out once, returns to idle condition.
4. the dynamic test system of radio frequency front end chip according to claim 1, is characterized in that, described data memory module comprises: data transmission unit and data receiver unit;
Described data transmission unit, for when the transmission test, data storage for download communication from described host computer in advance; When dynamic test runs to emission state, recall successively corresponding data, by described RF data interface module, be sent to described tested radio frequency front end chip;
Described data receiver unit, for when receiving test, receives and stores the logical credit data of described tested radio frequency front end chip; After Acceptance Tests waiting completes, the data that receive by passing described host computer back in described host computer interface module.
5. the dynamic test system of radio frequency front end chip according to claim 1, is characterized in that, described host computer interface module comprises two kinds of mode of operations: data communication mode and command communication pattern;
Under data communication mode, described host computer interface module operates described data memory module for described host computer;
Under command communication module, described host computer interface module operates described register module for described host computer.
6. a dynamic checkout unit for radio frequency front end chip, is characterized in that, described device is used for coordinating host computer to carry out dynamic test to tested radio frequency front end chip;
Described device comprises: clock module, register module, task scheduling modules, data memory module, host computer interface module, RF data interface module and RF control interface module;
Described clock module, for generation of the clock of the required various frequencies of described dynamic checkout unit;
Described register module, control sequence corresponding to current test item sending for receive and preserve described host computer by described host computer interface module; And in dynamic test process, according to the dispatch command that is received from described task scheduling modules, recall corresponding steering order, by described RF control interface module, be sent to tested radio frequency front end chip;
Described task scheduling modules, in dynamic test process, controls the switching of described proving installation mode of operation; According to the execution time of each steering order in control sequence corresponding to current test item, to described register module, send dispatch command; Control startup and the operation to tested each input/output port of radio frequency front end chip of described RF data interface module and RF control interface module;
Described data memory module, the logical credit data of launching when storing described tested radio frequency front end chip transmission test and the logical credit data of receiving while receiving test;
Described host computer interface module, for realizing communicating by letter between described host computer and described proving installation;
Described RF data interface module, for leading to credit data to described tested radio frequency front end chip transmitting-receiving;
Described RF control interface module, for realizing the operation of described proving installation to the read-write register of described tested radio frequency front end chip and correlated inputs output port.
7. the dynamic checkout unit of radio frequency front end chip according to claim 6, it is characterized in that, described clock module adopts from the 26M of radio frequency front end chip input as synchronous clock source, by digital dock administration module DCM, produces the required synchronous clock of transceiving data under the major clock of described dynamic checkout unit work and different communication standard.
8. the dynamic checkout unit of radio frequency front end chip according to claim 6, is characterized in that, the mode of operation of described proving installation comprises: single operational mode and circular flow pattern;
Described circular flow pattern is, all steering orders that the current test item of take is corresponding are a cycle, from article one steering order, start to carry out until the last item steering order, timer zero clearing, return to original state, from article one steering order, start to carry out again, so all steering orders are carried out in circulation;
Described single operational mode is, all steering orders that current test item is corresponding are carried out once, returns to idle condition.
9. the dynamic checkout unit of radio frequency front end chip according to claim 6, is characterized in that, described data memory module comprises: data transmission unit and data receiver unit;
Described data transmission unit, for when the transmission test, data storage for download communication from described host computer in advance; When dynamic test runs to emission state, recall successively corresponding data, by described RF data interface module, be sent to described tested radio frequency front end chip;
Described data receiver unit, for when receiving test, receives and stores the logical credit data of described tested radio frequency front end chip; After Acceptance Tests waiting completes, the data that receive by passing described host computer back in described host computer interface module.
10. the dynamic checkout unit of radio frequency front end chip according to claim 6, is characterized in that, described host computer interface module comprises two kinds of mode of operations: data communication mode and command communication pattern;
Under data communication mode, described host computer interface module operates described data memory module for described host computer;
Under command communication module, described host computer interface module operates described register module for described host computer.
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| CN102946257B (en) * | 2012-11-05 | 2016-01-20 | 中兴通讯股份有限公司 | A kind of multimode rake receiver and method of reseptance thereof |
| CN105357379A (en) * | 2015-10-27 | 2016-02-24 | 上海斐讯数据通信技术有限公司 | Method and system for making intelligent terminal still be effective after being restarted under specific mode |
| CN107589366B (en) * | 2017-10-16 | 2023-09-29 | 江苏钜芯集成电路技术股份有限公司 | Batch testing device and method for wireless transceiver chips |
| CN108427127A (en) * | 2018-01-31 | 2018-08-21 | 交通运输部水运科学研究所 | The test method and device of baseband chip performance |
| CN109582348A (en) * | 2018-11-22 | 2019-04-05 | Tcl移动通信科技（宁波）有限公司 | Processing method, mobile terminal and storage medium is arranged in mobile terminal radio frequency |
| CN111781488B (en) * | 2020-06-24 | 2023-04-07 | 芯佰微电子（北京）有限公司 | Chip and chip test system |
| CN113708905A (en) * | 2021-08-18 | 2021-11-26 | Oppo广东移动通信有限公司 | Control method and device of radio frequency front end, terminal and chip |
| CN115623077B (en) * | 2022-10-18 | 2023-08-18 | 开元华创科技(集团)有限公司 | Autonomous controllable test system |
| CN116203856B (en) * | 2023-05-04 | 2023-10-31 | 成都天成电科科技有限公司 | Universal test method and device based on parameter configuration and storage medium |
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| JP4339534B2 (en) * | 2001-09-05 | 2009-10-07 | 富士通マイクロエレクトロニクス株式会社 | A semiconductor device with a memory chip and logic chip that enables testing of the memory chip |
| TWI267086B (en) * | 2005-12-30 | 2006-11-21 | Ind Tech Res Inst | Built-in memory current test circuit |
| JP2010250905A (en) * | 2009-04-16 | 2010-11-04 | Toshiba Corp | Semiconductor integrated circuit and method for testing the same |
| CN102288895B (en) * | 2011-05-05 | 2013-05-01 | 清华大学 | On-chip auxiliary testing system of delta-sigma analog-digital converter and auxiliary testing method of same |
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