CN102610572B - Preparation method of dual-layer semiconductor apparatus with semi-cavity structure - Google Patents
Preparation method of dual-layer semiconductor apparatus with semi-cavity structure Download PDFInfo
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- CN102610572B CN102610572B CN201210090254.8A CN201210090254A CN102610572B CN 102610572 B CN102610572 B CN 102610572B CN 201210090254 A CN201210090254 A CN 201210090254A CN 102610572 B CN102610572 B CN 102610572B
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Abstract
The invention discloses a preparation method for achieving layer transfer of an upper-layer semiconductor layer on a lower-layer semiconductor apparatus layer by adopting a low-temperature bonding and low-temperature stripping method, then preparing an upper-layer semiconductor apparatus in the upper-layer semiconductor layer, and finally finishing upper layer contact hole and lower layer contact hole processes once to achieve the isolation of the upper-layer semiconductor apparatus and the lower-layer semiconductor apparatus. The process is simple; the integrated level of the semiconductor apparatus is effectively improved. A semi-cavity isolation structure for a cavity layer and an insulated medium supporting layer structure is prepared in the upper-layer semiconductor apparatus and the lower-layer semiconductor apparatus, and the capacitive coupling effect between an upper apparatus layer and a lower apparatus layer is effectively reduced.
Description
Technical field
The present invention relates to a kind of preparation method of semiconductor device, relate in particular to a kind of preparation method of the upper and lower two-layer semiconductor device with half empty isolation structure.
Background technology
SOI(Silicon On Insulator) because of its unique structure and a series of premium properties, can realize the insulation isolation of components and parts in integrated circuit manufacture, eliminate the parasitic latch-up in Bulk CMOS; Meanwhile, CMOS/SOI circuit also has the series of advantages such as parasitic capacitance is little, integrated level is high, speed is fast, low in energy consumption, working temperature is high (300 ℃), anti-irradiation.Therefore, SOI material will be one of main material of more hachure (0.1 μ m) integrated circuit, estimate will mainly use above-mentioned material when integrated level reaches when 1Gb is used Φ 300mm silicon chip.In recent years, SOI Materials is rapid, more and more causes people's great attention, and is considered to most important silicon integrated circuit technology of 21st century.
At present, layer transfer technology is the mainstream technology of preparation SOI material, and in layer transfer technology, a thin surface silicon layer, after a silicon substrate is peeled off, is transferred on a silicon substrate after oxidation, forms a slice SOI material.Owing to being substrate preparation, in preparation technology, there is no the restriction of temperature, therefore, bonding and stripping process in preparation SOI silicon substrate mostly adopt high-temperature technology, and to increase bond strength, to make to peel off easier simultaneously.At present, business-like layer transfer technology mainly comprises smart peeling technology (Smart-Cut), epitaxial loayer transfer techniques (ELTRAN) and notes oxygen bonding techniques (Simbond).
But the support chip in layer shifts is while being prepared with the device sheet of semiconductor device, existence due to semiconductor device in support chip and semiconductor metal alloy (as nickel silicon alloy, cobalt silicon alloy, tungsten silicon alloy, alusil alloy etc.), just can not adopt high temperature bonding and the high temperature lift-off technology of conventional SOI silicon substrate, and must adopt cryogenic technique (400 ℃ of General Requirements are following).
Chinese patent CN1610114A discloses a kind of three-dimensional complementary metal oxide semiconductor device (CMOS) structure and preparation method thereof, it adopts low-temperature bonding and low temperature lift-off technology, can realize the multiple-level stack of CMOS, improve device integration density, but there is following defect: need between layers to add layer of metal layer, its upper and lower two layer devices are connected with it by through hole; This has increased the complexity of technique.
Chinese patent CN100440513C discloses a kind of three-dimensional complementary metal oxide semiconductor (CMOS) device architecture and preparation method thereof, it adopts low-temperature bonding and low temperature lift-off technology, can realize the multiple-level stack of CMOS, improve device integration density, although it does not need to increase layer of metal layer as the articulamentum of upper and lower device layer between two-layer device layer, but it still needs to prepare connecting through hole between each layer device layer, as the connecting line of upper and lower two-layer device layer, this has increased the complexity of technique equally.
What above-mentioned two patented technologies realized is all multiple-level stacks of CMOS, and multiple-level stack must increase the parasitic capacitance between semiconductor device, thereby Circuit responce speed is restricted.
Summary of the invention
For the problems referred to above, the invention provides a kind of preparation method of the upper and lower two-layer semiconductor device with half empty structure.
A first aspect of the present invention is to provide a kind of preparation method of the two-layer semiconductor device with half empty structure, and step comprises:
Preferably, when upper strata silicon bonding segment thickness hour, in the part of upper strata silicon and lower layer support sheet bonding, carry out growing epitaxial silicon;
Step 4 is prepared upper strata semiconductor device in the silicon of upper strata; On the upper strata semiconductor device obtaining, form upper strata ILD layer, then prepare upper strata contact hole and lower floor's contact hole.Upper strata contact hole and lower floor's contact hole can be disposable or successively form;
Step 5, then prepares amorphous carbon ashing through hole at upper layer device, and described amorphous carbon ashing through hole runs through layer device to the ILD layer of lower layer support sheet;
Step 6, carries out ashing processing by described amorphous carbon ashing through hole to the ILD layer in lower layer support sheet, forms cavity layer in the ILD position of lower layer support sheet;
Step 7, upwards deposits dielectric in the amorphous carbon ashing through hole in layer device, by the shutoff of amorphous carbon ashing through hole.
In a kind of preferred implementation of the present invention, described amorphous carbon ashing through hole is prepared above the sti structure of upper layer device, and amorphous carbon ashing through hole runs through the ILD layer of layer device and STI layer until the ILD layer of lower layer support sheet.
In another kind of preferred implementation of the present invention, described in step 7, dielectric is preferably SiO
2.
In another kind of preferred implementation of the present invention, in lower layer support sheet, one deck insulating medium layer is prepared in device sti structure top, as the supporting construction of cavity layer.
In another kind of preferred implementation of the present invention, upper layer device MOS district and lower layer device MOS district also do not line up, thereby are lower floor's device contacts hole slot milling.
In the above-mentioned preparation method of the present invention, described lower layer support sheet can be body silicon silicon chip, can be also soi wafer, or other semiconductor chips is as germanium wafer, germanium silicon chip, strain silicon chip etc.
Wherein, in order to guarantee a layer transfer mass, must guarantee the ILD of lower floor enough little surface roughness CMP after, preferably, can adopt FACMP(Fixed Abrasive CMP) processing, make surface roughness be less than 10nm.
Second aspect of the present invention is to provide two-layer semiconductor device prepared by a kind of said method, comprises lower layer device and upper layer device, and upper layer device and lower layer device are connected to a fixed by low-temperature bonding technology.
Wherein, in above-mentioned steps 4, epitaxial growth temperature is controlled at≤and 650 ℃.
In order to guarantee before lower floor's half cavity preparation that AC layer can ashing, in step 1, lower layer support sheet after AC layer deposition to thin layer SiO
2between having deposited, can not occur that dry method is removed photoresist and cineration technics, can only adopt wet processing.That in addition, the EBR(Edge Bead Removal of deposition AC layer) must come than the EBR of deposition SiO2 layer is large, to guarantee that AC on wafer limit is by SiO
2wrap.
The present invention is by the method that adopts low-temperature bonding, low temperature to peel off, the layer of realizing the upper strata semiconductor layer in lower floor's semiconductor device layer shifts, then in the semiconductor layer of upper strata, prepare upper strata semiconductor device, last property completes upper strata contact hole and lower floor's contact hole technique, realize upper and lower two-layer semiconductor device isolation preparation method, technique is simple, has effectively improved the integrated level of semiconductor device.
The present invention is owing to only having upper and lower two-layer semiconductor device layer, so upper strata contact hole and lower floor's contact hole can once complete, than existing multi-lager semiconductor technology, simply many in technique.The half empty isolation structure that is prepared with cavity layer+dielectric supporting layer structure in levels semiconductor device layer, effectively reduces the capacitance coupling effect between upper and lower device layer simultaneously.
Accompanying drawing explanation
Fig. 1 is in an embodiment of the present invention, lower layer support sheet and upper strata silicon structure schematic diagram;
Fig. 2 is attaching process schematic diagram in embodiment described in Fig. 1;
Fig. 3 is structural representation after low-temperature bonding in embodiment described in Fig. 1;
Fig. 4 be described in Fig. 1 in embodiment low temperature peel off rear structural representation;
Fig. 5 is structural representation after epitaxial growth in embodiment described in Fig. 1;
Fig. 6 prepares upper strata semiconductor device structure schematic diagram in embodiment described in Fig. 1;
Fig. 7 forms ILD layer structural representation in embodiment described in Fig. 1;
Fig. 8 prepares contact hole structure schematic diagram in embodiment described in Fig. 1;
Fig. 9 prepares amorphous carbon through-hole structure schematic diagram in embodiment described in Fig. 1;
Figure 10 be described in Fig. 1 in embodiment by the structural representation after the ashing of AC layer;
Figure 11 is the two-layer semiconductor device structure schematic diagram of preparing in above-described embodiment.
Embodiment
The invention provides a kind of preparation method of two-layer semiconductor device and semiconductor device prepared by described method, Fig. 1 ~ Figure 11 has provided the schematic flow sheet of preparing two-layer semiconductor device in one embodiment of the invention; With reference to the accompanying drawings, by specific embodiment, the present invention is described in detail and is described, so that better understand content of the present invention, but should be understood that, following embodiment does not limit the scope of the invention.
In the present embodiment, the plane CMOS FET structure of take is example, but can be also various semiconductor device.
With reference to Fig. 1, lower layer support sheet 1 is graphical, and support chip 1 selective body silicon silicon chip, can be also soi wafer, or other semiconductor chips be as germanium wafer, germanium silicon chip, strain silicon chip etc.
The ILD layer 11 of lower layer support sheet 1 is amorphous carbon layer 11, prepares one deck spacer insulator dielectric layer 13 in amorphous carbon layer, and in the present embodiment, spacer insulator dielectric layer 13 is positioned at the top (Fig. 1 bend part) of sti structure.This operation can realize by Damascene technique.
Spacer insulator dielectric layer is preferably SiO
2(also can for thering is the low κ silicon dioxide layer of carbon containing of microcellular structure), in order to guarantee a layer transfer mass, must guarantee the ILD of lower floor enough little surface roughness CMP after, employing FACMP(Fixed Abrasive CMP), make surface roughness be less than 10nm.
For the needs of follow-up bonding, stringer SiO on ILD layer 11
2 layer 12.
In upper strata silicon 2, containing boron-rich, hydrogen layer 21, is wherein SiO for the part with lower layer support sheet 1 bonding
2layer 22.
Always there is oxide layer in silicon chip surface, some silica covalent bond in surperficial silicon dioxide molecules can rupture, and makes silicon atom form dangling bonds.The aobvious electropositive of silicon atom hanging, can regard silicon face one deck charge layer as.During through hydrophilic treated, silicon face absorption OH-group forms silanol key.Two silicon chips that form silanol keys near time, between silanol key, hydrone and silanol key, can attract each other by formation hydrogen bond.The laminating period of Here it is bonding.What silicon chip interface existed is (Si-OH) and hydrone.When temperature raises, there is following reaction:
2SiOH→Si-O-Si+H
2O
Be that silanol key transforms to silicon oxygen bond.This reaction is reversible reaction, and temperature is higher, and the Direction of Reaction more carries out to the right.Here it is, and why high annealing can strengthen bond strength.Process annealing is exactly to require at lower temperature, and reaction can be carried out to the right more fully.This just has following two requirements: (1) silicon chip surface multiform of will trying one's best becomes silanol key, make silicon chip when laminating in conjunction with closely and have enough reactants; (2) the process annealing time will be grown, and is beneficial to hydrone and escapes and spread, and reaction is constantly carried out to positive direction.For above second point, extend annealing time.And the first point requires silicon chip to have as far as possible many dangling bonds before hydrophilic treated, to adsorb a large amount of (OH) groups.Take oxygen plasma Activiation method as example, and it can have on oxide layer surface following reaction:
Si-O+O
+→(Si)
++O
2
Thereby reach the object that forms a large amount of silicon dangling bonds, this is the main cause that process annealing can strengthen bonded interface intensity.
Therefore, first the silicon dioxide layer 22 of the bonding surface of lower layer support sheet 1 and upper strata silicon chip is carried out to activation processing (as chemistry or plasma treatment), hydrophilic treated, so that bonding face forms a large amount of silanol keys.
With reference to Fig. 2, the SiO by the silicon dioxide layer of upper strata silicon 2 22 with lower layer support sheet 1
2 layer 12 laminating (arrow is laminating direction), this step can at room temperature be carried out.
With reference to Fig. 3, low-temperature bonding, reinforces upper strata silicon 2 on lower layer support sheet 1.
This step can be carried out with reference to prior art.
With reference to Fig. 4, by low-temperature bonding technology, upper strata silicon is ruptured from boron-rich, hydrogen layer, thereby boron-rich in figure, more than hydrogen layer part is peeled off, and lower part (bonding part) is bonded to and is integrated with lower layer support sheet.
This step can be carried out with reference to prior art.Also there is now several different methods, if dosage is 5E16cm
-2to 9E16cm
-2notes hydrogen sheet or hydrogen helium note altogether sheet and can peel off 500 ℃ of left and right, and boron, hydrogen are noted altogether sheet exfoliation temperature and can be less than 400 ℃.Even, containing the bonding pad of noting hydrogen layer or porous silicon layer, can under mechanism, just can at room temperature successfully peel off, these technology are all for the support chip in layer transfer is that while being prepared with the device sheet of semiconductor device, required low temperature is peeled off technical foundation is provided.
Low Temperature Solid-Phase (or liquid phase) growing epitaxial silicon, key and part form upper strata silicon layer 3, as the basis of preparation upper strata semiconductor device, as shown in Figure 5.This growing epitaxial silicon step is optional step, in the situation that enough thick omissions of the upper strata silicon layer after bonding.
Step 4
In the upper strata silicon layer 3 obtaining, prepare upper strata semiconductor device in step 4, as shown in Figure 6.
On the upper strata semiconductor device obtaining, deposit ILD layer 23, as shown in Figure 7, and prepare upper strata contact hole 20He lower floor contact hole 10 simultaneously, (in subsequent figures, omit contact hole) as shown in Figure 8.
In this step 5, can adjust upper strata device position, for example will between upper layer device MOS district and lower layer device MOS district, be offset certain distance, thereby be the reserved enough spaces of preparation lower floor contact hole.
Step 5
In upper layer device, prepare amorphous carbon ashing through hole 24, amorphous carbon ashing through hole 24 connects upper layer device until the ILD layer in lower layer device.Amorphous carbon ashing through hole can be through hole and the position that can arrive arbitrarily lower layer device ILD layer, is chosen in the preparation of layer device sti structure top in the present embodiment, amorphous carbon ashing through hole 24 is connected to upper layer device ILD layer and sti structure, as shown in Figure 9.
Step 6
With reference to Figure 10, by amorphous carbon ashing through hole 24, by the ILD layer ashing in lower layer device, form cavity layer 15, preferably ashing completely of the ILD layer in lower layer device, but also allow a small amount of amorphous carbon of residue, as long as can form the cavity layer with upper strata device isolation.
Step 7
Above upper layer device, deposit dielectric (SiO for example
2), amorphous carbon through hole should be enough little, so that in dielectric deposition process, can not enter in the cavity layer forming in step 6; But the dielectric of deposition preferably can be packed in amorphous carbon ashing through hole, by the shutoff of amorphous carbon ashing through hole.
Because amorphous carbon ashing through hole in the present embodiment is in the preparation of the STI position of upper layer device, therefore, be positioned at the part of STI even without by shutoff completely, can not impact device yet.
Finally remove unnecessary dielectric, obtain two-layer semiconductor device, as shown in figure 11.
Above specific embodiments of the invention be have been described in detail, but it is just as example, the present invention is not restricted to specific embodiment described above.To those skilled in the art, any equivalent modifications that the present invention is carried out and alternative also all among category of the present invention.Therefore, equalization conversion and the modification done without departing from the spirit and scope of the invention, all should contain within the scope of the invention.
Claims (6)
1. with a preparation method for the two-layer semiconductor device of half empty structure, it is characterized in that, step comprises:
Step 1, patterned lower layer support sheet is provided, and in lower layer support sheet, the ILD layer of device is amorphous carbon layer, on the ILD of lower layer support sheet layer, deposits silica film layer, in lower layer support sheet, one deck insulating medium layer is prepared in device sti structure top, as the supporting construction of cavity layer; Upper strata silicon is provided, and wherein, described upper strata silicon comprises boron-rich, hydrogen layer, and comprises and be positioned at surperficial silicon dioxide layer; Silicon dioxide layer to the silicon dioxide layer of upper strata silicon and lower layer support sheet carries out activation processing and hydrophilic treated, to increase the silanol key for the treatment of surface;
Step 2, is fitted in the silicon dioxide layer of upper strata silicon on the lower layer support sheet surface silica dioxide layer after processing, and by low-temperature bonding, upper strata silicon is fixed on to lower layer support sheet surface;
Step 3, by low temperature lift-off technology, peels off upper strata silicon from boron-rich, the fracture of hydrogen layer, part boron-rich, hydrogen layer below is connected as a single entity with lower layer support sheet surface bond;
Step 4 is prepared upper strata semiconductor device in the silicon of upper strata; On the upper strata semiconductor device obtaining, form upper strata ILD layer, then prepare upper strata contact hole and lower floor's contact hole, upper strata contact hole and lower floor's contact hole can be disposable or successively form;
Step 5, then prepares amorphous carbon ashing through hole at upper layer device, and described amorphous carbon ashing through hole runs through layer device to the ILD layer of lower layer support sheet;
Step 6, carries out ashing processing by described amorphous carbon ashing through hole to the ILD layer in lower layer support sheet, forms cavity layer in the ILD position of lower layer support sheet;
Step 7, upwards deposits dielectric in the amorphous carbon ashing through hole in layer device, by the shutoff of amorphous carbon ashing through hole.
2. preparation method according to claim 1, is characterized in that, described amorphous carbon ashing through hole is prepared above the sti structure of upper layer device, and amorphous carbon ashing through hole runs through the ILD layer of layer device and STI layer until the ILD layer of lower layer support sheet.
3. preparation method according to claim 1, is characterized in that, described in step 7, dielectric is preferably SiO
2.
4. preparation method according to claim 1, is characterized in that, after step 3, in the part of upper strata silicon and lower layer support sheet bonding, carries out growing epitaxial silicon; Epitaxial growth temperature is controlled at≤and 650 ℃.
5. preparation method according to claim 1, is characterized in that, described lower layer support sheet is selected from body silicon silicon chip, soi wafer, germanium wafer, germanium silicon chip, strain silicon chip.
6. the two-layer semiconductor device that as claimed in claim 1 prepared by method.
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| US7812459B2 (en) * | 2006-12-19 | 2010-10-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Three-dimensional integrated circuits with protection layers |
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