Background technology
3GPP (3rd Generation Partnership Project, 3G (Third Generation) Moblie standardization body) introduce HSDPA (High Speed Downlink Packet Access, high-speed slender body theory) technology and HSUPA (High Speed Uplink Packet Access, High Speed Uplink Packet accesses) technology, HSDPA technology and HSUPA technology are all applicable to various mobile communication system, such as TD-SCDMA (Time Division Synchronized CDMA, time division synchronous CDMA; CDMA:Code DivisionMultiple Access, code division multiple access accesses) system, WCDMA (Wideband CDMA, wideband CDMA) system etc.
HSDPA technology is by AMC (Adaptive Modulation and Coding, adaptive modulation and coding), HARQ (Hybrid Automatic Repeat Request, hybrid automatic retransmission request) etc. series of key techniques, and MAC-hs (Media Access Control) is introduced in NodeB (base station), NodeB can be realized to different UEs (User Equipment, subscriber equipment) fast dispatch, obtain higher user's peak rate and cell data throughput simultaneously.In HSDPA technology, transmission channel HS-DSCH (High Speed Downlink Shared Channel, high speed descending sharing channel) is for transmitting the downlink data sent to UE.
HSUPA technology is by adopting HARQ, based on series of key techniques such as the fast dispatch of NodeB and multi-code transmissions, greatly strengthen message transmission rate and the availability of frequency spectrum of up link; Also increased a transmission channel E-DCII (Enhanced Dedicated Transport Channel, enhanced uplink dedicated transmission channel) newly, for transmitting the upstream data of UE (User Equipment, subscriber equipment) simultaneously.
The process of transmission channel comprises transmitting stage process and physical level process, to support that the TD-SCDMA system of HSUPA technology is described.E-DCH is main uplink data channels, at each TTI (Transmission Time Interval, Transmission Time Interval) a middle carrying transmitting stage deal with data bit, and be mapped to the data division of physical channel E-PUCH (enhanced uplink physical channel).Specify according to 3GPP agreement, the transmitting stage process of E-DCH comprises: add the steps such as CRC (Cyclic Redundancy Check, cyclic redundancy check (CRC) code), code block segmentation, chnnel coding (being generally TURBO coding), HARQ process, bit scramble, data interlacing, Constellation Rearrangement.Wherein, HARQ process comprises bit separation, rate-matched and bit and merges three steps, and rate-matched refers to that the data bit of transmission channel is perforated or repeats, to mate the bearing capacity of physical channel.Data bit number in a transmission channel, may change in different TTI.When in different TTI, when the data bit number that transmits changes, data bit will be perforated or repeat, to guarantee that the data bit-rate after transmission channel is multiplexing is identical with the data bit-rate of distributed physical channel.Punching is exactly removed by current data bit, follow-up each data bit is moved forward one successively simultaneously, repeats to be exactly insert a current data bit between current data bit and a rear data bit.
In prior art, the transmitting stage handling process of E-DCH performs every single stepping according to the regulation order of 3GPP agreement.As shown in Figure 1, the transmitting stage processing method of E-DCH, comprising: add CRC, carry out code block segmentation operation afterwards; Carry out Channel encoding operations after code block segmentation, HARQ process is carried out to the encoded data bits that chnnel coding obtains, then obtains transmitting stage deal with data bit through bit scramble, data interlacing, Constellation Rearrangement etc.
As shown in Figure 2, be HARQ process chart, HARQ handling process comprises bit separation, rate-matched and bit and merges.Concrete, after receiving the encoded data bits that chnnel coding obtains, encoded data bits being stored in a block storage such as RAM1, realizing bit separation when encoded data bits being write RAM1, obtain systematic bits, the first check bit and the second check bit three sequences; The rate adaptation operating punched or repeat is carried out when reading encoded data bits from RAM1; Encoded data bits after rate-matched sends to another block storage such as RAM2 again, and the interlacing rule merged according to bit can realize the bit union operation to the encoded data bits stored in RAM2; Encoded data bits after bit merges carries out subsequent treatment again.
In prior art, when realizing the transmitting stage process of E-DCH according to 3GPP protocol sequence, handling process is more clearly, and implementation method is fairly simple.But, the transmitting stage processing method of E-DCH, twice storage has been carried out to the encoded data bits after chnnel coding, thus need to take more memory space, such as, the transmission rate of E-DCH reaches as high as 2.23MHZ, and maximum transmitting stage deal with data bit is 11160 bits, then original transmitted block needs the data bit number stored to be 11160bit × 3 ≈ 34kbit to the maximum after chnnel coding (being generally TURBO coding); Encoded data bits after rate-matched can store again, causes the memory space that needs to take comparatively large, and for chip design, cause chip area comparatively large, especially for UE, larger chip area will have a strong impact on follow-up Integrated design.Further, the transmitting stage handling process of E-DCH is that order performs, and the processing time is longer, causes treatment effeciency lower.
According to 3GPP agreement regulation, the transmitting stage handling process of HS-DSCH and the transmitting stage handling process of E-DCH are basically identical, and that is, in the mobile communication system of support HSDPA technology, the problems referred to above exist equally.
From analyzing above, in the transmitting stage handling process of existing transmission channel, there is the memory space needing to take comparatively large, and the problem that treatment effeciency is lower.
Summary of the invention
Embodiments provide a kind of transmitting stage processing method and device of transmission channel, in order to reduce in handling process the memory space needing to take, and promote the transmitting stage treatment effeciency of transmission channel.
Embodiments provide a kind of subscriber equipment, in order to reduce chip area required in the chip design of subscriber equipment, promote the treatment effeciency of subscriber equipment.
A transmitting stage processing method for transmission channel, comprising:
Chnnel coding is carried out after original transmitted block is added check code;
When rate matching pattern is puncturing patterns, rate-matched punching pattern according to determining carries out rate adaptation operating to the encoded data bits that chnnel coding obtains, and the encoded data bits after memory rate coupling, the interlacing rule merged according to bit carries out bit merging and Scrambling Operation to the encoded data bits stored, data interlacing and Constellation Rearrangement are carried out to the encoded data bits after bit merging and scrambling, exports the transmitting stage deal with data bit obtained;
When rate matching pattern is repeat pattern, encoded data bits chnnel coding obtained stores, the interlacing rule merged according to bit carries out bit merging and Scrambling Operation to the encoded data bits stored, according to the rate-matched repetitions patterns determined, rate-matched and Scrambling Operation are carried out to the output data bit after bit merging, data interlacing and Constellation Rearrangement are carried out to the encoded data bits after rate-matched and scrambling, exports the transmitting stage deal with data bit obtained.
A transmitting stage processing unit for transmission channel, comprises check code and adds module, data interlacing and Constellation Rearrangement module, also comprises channel coding module, Rate Matching block, bit merging and scrambling module and memory, wherein:
Described check code adds module, after original transmitted block is added check code, sends to described channel coding module;
Described channel coding module, export after chnnel coding is carried out to the original transmitted block that with the addition of check code, when rate matching pattern is puncturing patterns, send output enable signal and start rate adaptation operating to described Rate Matching block, and the encoded data bits after rate-matched is stored in memory; When rate matching pattern is repeat pattern, encoded data bits chnnel coding obtained is stored in memory;
Described Rate Matching block, for when rate matching pattern is puncturing patterns, start under the triggering of the output enable signal sent in described channel coding module, and according to the rate-matched punching pattern determined, rate adaptation operating is carried out to the encoded data bits that chnnel coding obtains; When rate matching pattern is repeat pattern, start under the triggering of the output enable signal that described bit merges and scrambling module sends, and export to data interlacing and Constellation Rearrangement module after rate-matched, scrambling being carried out to the data after bit merging according to the rate-matched repetitions patterns determined;
Described bit merges and scrambling module, for when rate matching pattern is puncturing patterns, after the interlacing rule merged carries out bit merging and Scrambling Operation to the encoded data bits stored in memory, export to described data interlacing and Constellation Rearrangement module according to bit; When rate matching pattern is repeat pattern, export to described data interlacing and Constellation Rearrangement module after the interlacing rule merged according to bit carries out bit merging and Scrambling Operation to the encoded data bits stored in memory, and send output enable signal to described Rate Matching block startup rate adaptation operating;
Described data interlacing and Constellation Rearrangement module, for carrying out data interlacing and Constellation Rearrangement to the encoded data bits received, export the transmitting stage deal with data bit obtained.
A kind of subscriber equipment, comprises the transmitting stage processing unit of above-mentioned transmission channel.
The transmitting stage processing method of the transmission channel that the embodiment of the present invention provides and device, perform different transmitting stage parallel processing flow processs according to different rate matching pattern.When rate matching pattern is puncturing patterns, the executed in parallel rate adaptation operating when delivery channel encodes the encoded data bits obtained, encoded data bits again after memory rate coupling, after bit merging and Scrambling Operation are carried out to the encoded data bits stored, carry out data interlacing and Constellation Rearrangement, obtain transmitting stage deal with data bit; When rate matching pattern is repeat pattern, first memory encoding data bit, again bit merging and Scrambling Operation are carried out to the encoded data bits stored, export bit merge and encoded data bits after scrambling time executed in parallel rate adaptation operating, then carry out data interlacing and Constellation Rearrangement, obtain transmitting stage deal with data bit.Due in handling process, no matter be puncturing patterns or repeat pattern, only need store first encoding data bit, thus save the memory space needing to take, thus decrease the chip area in chip design.Further, when rate matching pattern is puncturing patterns, the executed in parallel rate adaptation operating when delivery channel encodes the encoded data bits obtained; When rate matching pattern is repeat pattern, export bit merge and encoded data bits after scrambling time executed in parallel rate adaptation operating, therefore, shorten the transmitting stage processing time of transmission channel, improve treatment effeciency.
The subscriber equipment that the embodiment of the present invention provides, adopt the transmitting stage processing unit of above-mentioned transmission channel, because this processing unit saves the memory space needing to take, so chip area required in the chip design of subscriber equipment can be reduced, because this processing unit adopts parallel processing flow process, shorten the transmitting stage processing time of transmission channel, so the treatment effeciency of subscriber equipment can be promoted.
Other features and advantages of the present invention will be set forth in the following description, and, partly become apparent from specification, or understand by implementing the present invention.Object of the present invention and other advantages realize by structure specifically noted in write specification, claims and accompanying drawing and obtain.
Embodiment
The embodiment of the present invention provides a kind of method of transmitting stage process of transmission channel, device and equipment, in order to reduce in handling process the memory space needing to take, and promotes the transmitting stage treatment effeciency of transmission channel.
The transmitting stage processing method of the transmission channel that the embodiment of the present invention provides, be applicable to the various mobile communication system based on HSUPA technology, and based on the various mobile communication system of HSDPA technology, concrete based on HSUPA technology time, described transmission channel refers to E-DCH, during based on HSDPA technology, described transmission channel refers to HS-DSCH.
It should be noted that, in the transmitting stage process of transmitting stage channel, rate matching pattern can comprise: puncturing patterns, repeat pattern or direct mode operation, wherein, lead directly to and refer to that data bit directly passes through, can think without rate adaptation operating, this situation of the embodiment of the present invention does not relate to.The rate matching pattern that the embodiment of the present invention relates to comprises puncturing patterns and repeat pattern.
Below in conjunction with Figure of description, the preferred embodiments of the present invention are described, be to be understood that, preferred embodiment described herein is only for instruction and explanation of the present invention, be not intended to limit the present invention, and when not conflicting, the embodiment in the present invention and the feature in embodiment can combine mutually.
As shown in Figure 3, embodiments provide a kind of transmitting stage processing method of transmission channel, comprise the steps:
S301, original transmitted block added after check code and carries out chnnel coding;
Wherein, described chnnel coding generally adopts TURBO to encode, and described interpolation check code is generally and adds CRC.
S302, when rate matching pattern is puncturing patterns, rate-matched punching pattern according to determining carries out rate adaptation operating to the encoded data bits that chnnel coding obtains, and the encoded data bits after memory rate coupling, the interlacing rule merged according to bit carries out bit merging and Scrambling Operation to the encoded data bits stored, data interlacing and Constellation Rearrangement are carried out to the encoded data bits after bit merging and scrambling, exports the transmitting stage deal with data bit obtained;
Preferably, in order to follow-up bit merges and the facility of scrambling, the encoded data bits after rate-matched can be carried out bit separation operation, obtain systematic bits, the first check bit and the second check bit; And the systematic bits obtained, the first check bit and the second check bit are stored in different address fields respectively.In concrete enforcement, memory can be divided into 3 address fields, first address field is used for storage system bit, and second address field is used for storage second check bit, and the 3rd address field is used for storage first check bit.After encoded data bits storage after rate-matched completes, the interlacing rule merged according to bit carries out bit merging and Scrambling Operation to the encoded data bits stored, and data interlacing and Constellation Rearrangement are carried out to the encoded data bits after bit merging and scrambling, export the transmitting stage deal with data bit obtained.
In concrete enforcement, when rate matching pattern is puncturing patterns, generally can determine rate-matched punching pattern according to the parameters of rate matching of high level configuration, described high level configuration is referred to and to be configured by RRC (Radio Resource Control, the wireless heterogeneous networks) signaling of RNC (radio network controller);
Described carries out rate adaptation operating according to the rate-matched punching pattern determined to the encoded data bits that chnnel coding obtains, and specifically comprises:
According to rate-matched punching pattern, determine the encoded data bits of redundancy in the encoded data bits that chnnel coding obtains;
The encoded data bits of the redundancy determined is given up.
S303, when rate matching pattern is repeat pattern, encoded data bits chnnel coding obtained stores, the interlacing rule merged according to bit carries out bit merging and Scrambling Operation to the encoded data bits stored, according to the rate-matched repetitions patterns determined, rate-matched and Scrambling Operation are carried out to the output data bit after bit merging, data interlacing and Constellation Rearrangement are carried out to the encoded data bits after rate-matched and scrambling, exports the transmitting stage deal with data bit obtained.
Preferably, in order to follow-up bit merges and the facility of scrambling, the encoded data bits that chnnel coding can be obtained carries out bit separation operation, obtains systematic bits, the first check bit and the second check bit; And the systematic bits obtained, the first check bit and the second check bit are stored in different address fields respectively.Concrete storage mode and rate matching pattern are similar when being puncturing patterns, and its implementation process with reference to the enforcement of puncturing patterns, can repeat no more here.
In concrete enforcement, when rate matching pattern is repeat pattern, generally can determine rate-matched repetitions patterns according to the parameters of rate matching of high level configuration, described carries out rate adaptation operating according to the rate-matched repetitions patterns determined to the output data bit after bit merging, specifically comprises:
According to the rate-matched repetitions patterns that the parameters of rate matching configured by high level is determined, determine the encoded data bits needing repetition in the output data bit after bit merging;
Repeat the encoded data bits reading the needs repetition determined.
In concrete enforcement, because HSDPA modulation and HSUPA modulation generally adopt QPSK (Quadrature Phase Shift Keying at present, quarternary phase-shift keying (QPSK)) and 16QAM (QuadratureAmplitude Modulation, quadrature amplitude modulation) two kinds of modes, described Constellation Rearrangement can be 16QAM Constellation Rearrangement, also can be QPSK Constellation Rearrangement.
Needs illustrate, just in order to express easily, and give concrete number of steps S302 and S303, do not represent the sequential relationship between two steps.
In the embodiment of the present invention, based on the consideration of the storage resources of saving hardware memory, several steps (chnnel coding, bit separation, rate-matched and bit merge and bit scramble) of the transmitting stage process of transmission channel are cooperatively interacted, adopt and change the handling process of transmitting stage process and the method for rate-matched initial time according to different rates match pattern, while the storage resources saving memory, also shorten the transmitting stage processing time.
Based on same inventive concept, embodiments provide a kind of transmitting stage processing unit of transmission channel, due to the principle of this device technical solution problem and the transmitting stage processing method of transmission channel similar, therefore the enforcement of this device can see the enforcement of method, repeats part and repeat no more.
As shown in Figure 4, the one possibility structure of the transmitting stage processing unit of the transmission channel that the embodiment of the present invention provides, comprise check code and add module 401, data interlacing and Constellation Rearrangement module 402, also comprise channel coding module 403, Rate Matching block 404, bit merging and scrambling module 405 and memory 406, wherein:
Check code adds module 401, after original transmitted block is added check code, sends to channel coding module 403;
Channel coding module 403, export after chnnel coding is carried out to the original transmitted block that with the addition of check code, when rate matching pattern is puncturing patterns, send output enable signal and start rate adaptation operating to Rate Matching block 404, and the encoded data bits after rate-matched is stored in memory 406; When rate matching pattern is repeat pattern, encoded data bits chnnel coding obtained is stored in memory 406;
Rate Matching block 404, for when rate matching pattern is puncturing patterns, start under the triggering of the output enable signal of described channel coding module 403 transmission, and according to the rate-matched punching pattern determined, rate adaptation operating is carried out to the encoded data bits that chnnel coding obtains; When rate matching pattern is repeat pattern, start under the triggering of the output enable signal that described bit merges and scrambling module 405 sends, and export to data interlacing and Constellation Rearrangement module 402 after rate-matched, scrambling being carried out to the data bit after bit merging according to the rate-matched repetitions patterns determined;
Bit merges and scrambling module 405, for when rate matching pattern is puncturing patterns, the interlacing rule merged according to bit exports to data interlacing and Constellation Rearrangement module 402 after carrying out bit merging and Scrambling Operation to the encoded data bits stored in memory 406; When rate matching pattern is repeat pattern, the interlacing rule merged according to bit exports to described data interlacing and Constellation Rearrangement module 402 after carrying out bit merging and Scrambling Operation to the encoded data bits stored in memory 406, and sends output enable signal and start rate adaptation operating to Rate Matching block 404;
Data interlacing and Constellation Rearrangement module 402, for carrying out data interlacing and Constellation Rearrangement to the encoded data bits received, export the transmitting stage deal with data bit obtained.
Preferably, channel coding module 403, specifically for when rate-matched mode is for punching, carries out bit separation operation, obtains systematic bits, the first check bit and the second check bit by the encoded data bits after rate-matched; And the systematic bits obtained, the first check bit and the second check bit are stored in the different address fields of memory respectively.
Preferably, channel coding module 403, specifically for when rate matching pattern is for repeating, coded data chnnel coding obtained carries out bit separation operation, obtains systematic bits, the first check bit and the second check bit; And the systematic bits obtained, the first check bit and the second check bit are stored in the different address fields of memory respectively.
In concrete enforcement, Rate Matching block 404, after starting under the triggering of the output enable signal of described channel coding module 403 transmission, according to the rate-matched punching pattern that the parameters of rate matching configured by high level is determined, determine the encoded data bits of redundancy in the encoded data bits that chnnel coding obtains; The encoded data bits of the redundancy determined is given up.
Concrete, when rate matching pattern is puncturing patterns, when exporting after channel coding module 403 carries out chnnel coding to the original transmitted block that with the addition of check code, send output enable signal triggering rate matching module 404 and start rate adaptation operating, Rate Matching block 404 is while encoded data bits exports, the parameters of rate matching determination rate-matched punching pattern configured according to high level, and the encoded data bits of redundancy in the encoded data bits obtained according to this rate-matched punching pattern determination chnnel coding; The encoded data bits of the redundancy determined is given up.
In concrete enforcement, Rate Matching block 404, after starting under the triggering of the output enable signal that described bit merges and scrambling module sends, according to the rate-matched repetitions patterns that the parameters of rate matching configured by high level is determined, determine the encoded data bits needing repetition in the output data bit after bit merging; Again the encoded data bits of the needs repetition determined is read.
Concrete, when rate matching pattern is repeat pattern, when exporting to data interlacing and Constellation Rearrangement module 402 after bit merging and scrambling module 405 carry out bit merging and Scrambling Operation according to the interlacing rule that bit merges to the encoded data bits stored in memory, send output enable signal and start rate adaptation operating to Rate Matching block 404, while the encoded data bits of Rate Matching block 404 after merging and scrambling reads encoded data bits output from memory, according to the parameters of rate matching determination rate-matched punching pattern that high level configures, and determine that the encoded data bits of current reading is the need of repetition according to this rate-matched punching pattern, if when determining that the encoded data bits of current reading needs repetition, then bit merging reads first encoding data bit with scrambling module 405 again from the memory address identical with current encoded data bit.
The memory related in the embodiment of the present invention is generally RAM (random access memory), also can be the memory of other type.
For convenience of description, each several part of the transmitting stage processing unit of above transmission channel is divided into each module (or unit) according to function and describes respectively.Certainly, the function of each module (or unit) can be realized in same or multiple software or hardware when implementing of the present invention.
In concrete enforcement, for the mobile communication system supporting HSUPA technology, the transmitting stage processing unit of described transmission channel is generally arranged in UE (subscriber equipment), because this processing unit saves the memory space needing to take, so chip area required in the chip design of UE can be reduced, because this processing unit adopts parallel processing flow process, shorten the transmitting stage processing time of transmission channel, so the treatment effeciency of UE can be promoted.For the mobile communication system supporting HSDPA technology, the transmitting stage processing unit of described transmission channel is generally arranged in NodeB (base station), chip area required in the chip design of NodeB can be reduced accordingly, promote the treatment effeciency of NodeB.
The execution mode of embodiment for a better understanding of the present invention, is described the method flow that the embodiment of the present invention provides below by concrete device block diagram.
Embodiment one
As shown in Figure 5, for rate matching pattern be puncturing patterns time, the transmitting stage process flow figure of transmission channel, comprising:
S501, check code add module and the original transmitted block received are added check code;
S502, check code add module and the original transmitted block that with the addition of check code are sent to channel coding module;
S503, channel coding module obtain encoded data bits after carrying out chnnel coding to the original transmitted block that with the addition of check code received;
While S504, channel coding module outputting encoded data bit, send output enable signal to Rate Matching block;
S505, Rate Matching block, according to the output enable signal enabling received, carry out rate-matched to encoded data bits;
Concrete, the rate-matched punching pattern that the parameters of rate matching that Rate Matching block generates high-rise configuration according to the parameter that high level configures is determined, determine the encoded data bits of redundancy in the encoded data bits that chnnel coding obtains, while channel coding module outputting encoded data bit, the encoded data bits of redundancy is given up.
Encoded data bits after S506, rate-matched is stored in memory;
S507, bit merge and the encoded data bits of scrambling module from memory after reading rate coupling carries out bit merging and Scrambling Operation;
S508, bit merge and the encoded data bits after bit merging and scrambling is exported to data interlacing and Constellation Rearrangement module by scrambling module.
Embodiment two
As shown in Figure 6, for rate matching pattern be repeat pattern time, the transmitting stage process implementing procedure schematic diagram of transmission channel, comprising:
S601, check code add module and the original transmitted block received are added check code;
S602, check code add module and the original transmitted block that with the addition of check code are sent to channel coding module;
S603, channel coding module obtain encoded data bits after carrying out chnnel coding to the original transmitted block that with the addition of check code received;
Encoded data bits is stored in memory by S604, channel coding module;
S605, memory memory encoding data bit;
The merging of S606, bit and scrambling module read after encoded data bits carries out bit merging and Scrambling Operation and export from memory, send output enable signal to Rate Matching block simultaneously;
S607, Rate Matching block, according to the output enable signal enabling received, carry out rate-matched to the encoded data bits after bit merging and scrambling;
Concrete, the rate-matched repetitions patterns that the parameters of rate matching that Rate Matching block generates high-rise configuration according to the parameter that high level configures is determined, determine the encoded data bits needing repetition in the encoded data bits that chnnel coding obtains, again read the encoded data bits of the needs repetition determined.
S608, carried out rate-matched after encoded data bits export to data interlacing and Constellation Rearrangement module.
The transmitting stage processing method of the transmission channel that the embodiment of the present invention provides and device, perform different transmitting stage parallel processing flow processs according to different rate matching pattern.When rate matching pattern is puncturing patterns, the executed in parallel rate adaptation operating when delivery channel encodes the encoded data bits obtained, encoded data bits again after memory rate coupling, after bit merging and Scrambling Operation are carried out to the encoded data bits stored, carry out data interlacing and Constellation Rearrangement, obtain transmitting stage deal with data bit; When rate matching pattern is repeat pattern, first memory encoding data bit, again bit merging and Scrambling Operation are carried out to the encoded data bits stored, export bit merge and encoded data bits after scrambling time executed in parallel rate adaptation operating, then carry out data interlacing and Constellation Rearrangement, obtain transmitting stage deal with data bit.Due in handling process, no matter be puncturing patterns or repeat pattern, only need store first encoding data bit, thus save the memory space needing to take, thus decrease the chip area in chip design.Further, when rate matching pattern is puncturing patterns, the executed in parallel rate adaptation operating when delivery channel encodes the encoded data bits obtained; When rate matching pattern is repeat pattern, export bit merge and encoded data bits after scrambling time executed in parallel rate adaptation operating, therefore, shorten the transmitting stage processing time of transmission channel, improve treatment effeciency.
Obviously, those skilled in the art can carry out various change and modification to the present invention and not depart from the spirit and scope of the present invention.Like this, if these amendments of the present invention and modification belong within the scope of the claims in the present invention and equivalent technologies thereof, then the present invention is also intended to comprise these change and modification.