CN102572436B - Intra-frame compression method based on CUDA (Compute Unified Device Architecture) - Google Patents
Intra-frame compression method based on CUDA (Compute Unified Device Architecture) Download PDFInfo
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- CN102572436B CN102572436B CN201210013335.8A CN201210013335A CN102572436B CN 102572436 B CN102572436 B CN 102572436B CN 201210013335 A CN201210013335 A CN 201210013335A CN 102572436 B CN102572436 B CN 102572436B
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Abstract
The invention discloses an intra-frame compression method based on a CUDA (Compute Unified Device Architecture). The method comprises the following steps of: firstly, respectively carrying out quadruple down-sampling and duplex down-sampling on the current frame to form three predicted frames with different resolution ratios, and directly carrying out nondestructive PCM (Pulse Code Modulation) coding on quadruple down-sampled data; then, carrying out bilinear interpolation on an image with low resolution ratio by using a texture memory to approach to the pixel value of an image with high resolution ratio, and carrying out DCT (Discrete Cosine Transform), quantization, scanning and entropy coding on a residual error; and finally, carrying out entropy coding on a CPU (Central Processing Unit), and multiplexing and outputting a code stream. The intra-frame compression method specially aims at a concurrent design and is high in data processing density and large concurrent processing line scale; and a special filtering function of the texture memory of a GPU (Graphics Processing Unit) is utilized, therefore, no programmable unit is occupied.
Description
Technical field
The invention belongs to communication technical field, relate to information source coding, is compression method in a kind of frame of realizing based on CUDA.
Background technology
At present, the processor in main flow computer is mainly central processor CPU and graphic process unit GPU.Be subject to the traction of Game Market and military vision simulation demand, it is very fast that GPU performance improves speed.In recent years, each year of the performance of GPU just can be double, substantially exceeded CPU and followed the development speed of Moore's Law (performance was double in every 18～24 months).In order to realize graphical effect more true to nature, GPU supports the computing becoming increasingly complex, and its programmability and function have all been expanded greatly.Traditionally, GPU is only responsible for graph rendering, and CPU has all been given in most processing.But overcome because improving the heat dissipation problem after clock frequency along with CPU is more and more difficult, then use the method that increases arithmetic core to accelerate.Before, GPU, as the special processor of graph rendering, has the parallel characteristics of height, and GPU is also converted into the coprocessor as general-purpose computations from single graph rendering equipment.
In 2007, the formal CUDA issuing (Compute Unified Device Archi-tecture calculates unified equipment framework) was that the first need to just can not be used class C language to carry out development environment and the software architecture of general-purpose computations by graphics API in NVIDIA company.Compared with traditional GPGPU development scheme in the past, CUDA has very significantly and improves.Performance, cost and on the development time more traditional CPU solution have significant advantage, the release of CUDA has caused ardent repercussion in academia and industrial circle.Now, CUDA is applied widely in a lot of fields, and has obtained great successes.Texture storage device (Texture memory) is a kind of read-only memory, and the figure special cell that has GPU to use to play up with texture develops, and the functions such as address mapping, data filtering, buffer memory are provided.
Existing infra-frame prediction is all difficult to carry out large-scale parallel computation, and in standard H.264, infra-frame prediction is block-based thinking, in order to the adjacent block pixel prediction current block of the reconstruct of encoding, adopts the multiple predictive mode that represents spatial domain grain direction.This prediction mode has been utilized the correlation between sub-block pixel, and current block prediction is based on the reconstructed blocks of encoding, and causes the encoding operation between piece serial to carry out.In this frame, method can effectively be approached its actual value, and image subjective quality is also better, but this method can not be carried out large-scale parallel computation.
Summary of the invention
The technical problem to be solved in the present invention is to provide compression method in a kind of frame based on CUDA Parallel Implementation.
Basic thought of the present invention is: pixel value is that the spatial sampling of analog video signal is formed, between discrete pixel values, there is continuity, so just can approach high-definition picture by GPU texture storage device interpolation to the low resolution image of down-sampling, part is eliminated spatial redundancy in frame, thereby realizes compression in fast frame.
Technical scheme of the present invention is as follows:
Compression method in the frame of realizing based on CUDA, the prediction steps of luminance signal:
(1) the texture storage device T from host side memory copying to equipment end by the luminance signal of present frame
0in;
(2) in equipment end, luminance signal is carried out respectively to 4 times and 2 times of down-samplings, 1/16 1/4 image in different resolution, the pixel number that forms respectively pixel number and be luminance signal is luminance signal 1/4 1/2 image in different resolution;
(3) 1/4 image in different resolution is carried out to harmless I_PCM coding;
(4) 1/4 image in different resolution is copied to texture storage device T
1in, and utilize the filter function of texture storage device to carry out interpolation to 1/4 image in different resolution, form 1/2 resolution reference picture;
(5) 1/2 image in different resolution and 1/2 resolution reference picture are carried out to difference operation, form three residual error planes, and it is encoded;
(6) three residual error planes of decoding, and form 1/2 resolution reconstructed image with it;
(7) copy 1/2 resolution reconstructed image to texture storage device T
2in, and utilize its filter function to carry out interpolation to 1/2 resolution reconstructed image, form original resolution reference picture;
(8) original resolution image and original resolution reference picture are carried out to difference operation, form three residual error planes, and it is encoded;
(9) three residual error planes of decoding, and form original resolution reconstructed image with it;
The prediction steps of color difference signal is identical with luminance signal.
Wherein, described harmless I_PCM coding, be to pixel value without conversion, quantization operation, directly lossless coding original pixel value.
Wherein, described interpolation is bilinear interpolation, interpolation result be each reference pixel right-hand, below, lower right can produce three interpolating pixels.
Wherein, described texture storage device T
0, the addressing mode in the texture referential of its statement and filter patterns attribute are set to respectively clamper addressing and closest approach sampling mode.
Wherein, described texture storage device T
1with texture storage device T
2, the addressing mode in the texture referential of its statement and filter patterns attribute are set to respectively clamper addressing and linear filtering sampling mode.
Wherein, the process that forms three residual error planes after described execution difference operation is: according to reference pixel around the direction of three interpolation reconfigure residual values, be equidirectionally combined in same plane.
Wherein, describedly to three residual error plane codings be: each residual error plane is carried out respectively to dct transform, quantification, scanning, entropy encoding operation; Decode procedure is: after the quantization operations of coding executes, data are carried out to inverse quantization, the operation of anti-dct transform.
Compared with prior art, tool of the present invention has the following advantages in the present invention:
(1) this algorithm is specially for CUDA design, and the closeness of deal with data is high, and parallel processing thread scale is large; Utilize asynchronous mechanism, when GPU end carries out computing or transfer of data, CPU is upper can encode by asynchronous execution entropy, thereby reduces the scramble time in complete frames.
(2) utilize continuity and the spatial coherence between pixel, by surveying on the GPU in NVIDIA company: than directly primary signal being carried out to integer transform, quantification, scanning, entropy coding formation compressed bit stream, the present invention can improve the compression ratio of 2～3 times, has compression effectiveness in good frame.
(3) utilize the distinctive filter function of texture storage device on GPU, make the calculating of interpolation utilize extra floating-point disposal ability, do not take programmable unit.
(4) three residual error planes after dct transform, quantification, inverse quantization, anti-dct transform are the high-resolution Interpolation with Planars of compensation that interweave, and blocking effect can weaken the impact of subjective quality.
Brief description of the drawings
Fig. 1 is system block diagram of the present invention;
Fig. 2 is bilinear interpolation method figure;
Fig. 3 is the time flow chart of the present invention's asynchronous execution between CPU and GPU;
Fig. 4 is 1/4 resolution to restructuring graph in the infra-frame prediction in 1/2 conversion of resolution process and frame;
Fig. 5 is the memory model figure of the whole implementation procedure of the present invention.
Embodiment
Below in conjunction with specific embodiment, the present invention is described in detail.
Below the specific implementation process of only describing luminance signal compression, color difference signal compression process is similar to it.
The texture storage device of GPU can carry out buffer memory and accelerate access, and the random of mass data or non-alignment access are also had to good acceleration effect.And its most characteristic be to have extra floating-point processing place ability, do not occupy the linear filtering of complete paired data in the situation of programmable unit, and pick up function coordinates by adjusting texture, can be simply, realization of High Speed is to being tied to the pixel execution bilinear interpolation of texture.The most basic principle of the present invention is: pixel value is that the spatial sampling of analog video signal is formed, between the pixel value after so discrete, there is continuity, so just can carry out interpolation to the low resolution image of down-sampling and approach high-definition picture, part is eliminated frame spatial redundancy.With reference to Fig. 1, be system block diagram of the present invention, as can be seen from the figure the process of enforcement of the present invention is: first, present frame is carried out respectively to 4 times and 2 times of down-samplings, form the predictive frame of 3 different resolutions, and 4 times of down-sampled data are directly carried out to harmless pcm encoder; Then, utilize texture storage device to carry out bilinear interpolation to low-resolution image and approach high-definition picture pixel value, and residual error is carried out to dct transform, quantification, scanning, entropy coding; Finally, on CPU, carry out entropy coding, and carry out code stream multiple connection output.
With reference to Fig. 2, bilinear interpolation method has been described, the value on arrow is the weighted value to each reference pixel.Pick up for the 2 d texture in texture storage device, its return value formula is:
tex(x，y)＝(1-α)(1-β)T[i，j]+α(1-β)T[i+1，j]+(1-α)βT[i，j+1]+αβT[i+1，j+1]
In formula: T representative is tied to the texture array of texture reference, and x, y are the coordinates that 2 d texture function picks up.
i＝floor(xB)，α＝frac(xB)，xB＝x-0.5；
j＝floor(yB)，β＝frac(yB)，yB＝y-0.5；
Frac (x)=x-floor (x), floor (x) is the maximum integer that is not more than x.
In infra-frame prediction process of the present invention, complete after twice down-sampling, can experience reconstruct in twice infra-frame prediction and frame, be respectively that 1/4 resolution is to 1/2 resolution, 1/2 resolution to original resolution.With reference to Fig. 4, be 1/4 resolution to reconstruct in the infra-frame prediction in 1/2 conversion of resolution process and frame.Process is: by interpolative prediction high-resolution pixel, and formed three residual error plane R
41, R
42, R
43, then, to R
41, R
42, R
43carry out respectively dct transform, quantification, inverse quantization, anti-dct transform; Finally, utilize decoded residual values by Interpolation with Planar I
i2be reconstructed into 1/2 image in different resolution I
c2.1/2 resolution is identical with it to original resolution transfer process.
In each infra-frame prediction and frame, reconstruct will be completed by three kernel functions, and a kernel is responsible for an interpolation direction.So, whole process of the present invention can be carried out six kernel functions, for convenience of description, six kernel functions is named as respectively: gpuKernel1, gpuKernel2, gpuKernel3, gpuKernel4, gpuKernel5, gpuKernel6; GpuKernel1, gpuKernel2, gpuKernel3 are responsible for 1/4 resolution to reconstruct in the infra-frame prediction of 1/2 resolution and frame, and gpuKernel4, gpuKernel5, gpuKernel6 are responsible for 1/2 resolution to reconstruct in the infra-frame prediction of original resolution and frame.
The task that single kernel completes: by utilizing texture storage device to carry out interpolation, ask residual error low-resolution image, produce a residual error plane, and residual error plane is carried out to dct transform, quantification, inverse quantization, anti-dct transform, and last, with this residual error planar reconstruction high-definition picture.Can bring like this benefit of two aspects: maximize and reduce brought by transfer of data consuming time; Because the startup of kernel is asynchronous, can allow like this entropy coding and the next residual error plane calculating asynchronous parallel on GPU of a residual error plane on CPU carry out.With reference to Fig. 3, be the time flow chart of the present invention's asynchronous execution between CPU and GPU, wherein, and the entropy coding function that cpuFunctionx is x residual error plane, dataCopy is by I
c2copy in texture storage device.
Specifically describe the specific implementation process of 1/4 resolution to the gpuKernel1 in 1/2 conversion of resolution process below, below set forth by three parts: the execution flow process of the institutional framework of thread, memory model, thread.
1. the organizational form of thread:
1/4 resolution is to the thread structure of the kernel function of 1/2 conversion of resolution:
Thread grid grid is divided into two-dimentional block form;
X dimension and the y dimension of thread grid (Grid) are respectively:
gridDim.x＝(Frame_width/4)/16；
gridDim.y＝(Frame_height/4)/16；
In formula, Frame_width and Frame_height are respectively width and the height of present frame.
In kernel function, needing to carry out block adds up to:
Block_num＝gridDim.x*gridDim.y；
16x16 in a thread block block sets of threads is made into three dimensional form:
blockDim.x＝4；
blockDim.y＝4；
blockDim.z＝16；
2. memory model:
With reference to Fig. 5, it is the memory model of the whole implementation procedure of the present invention.Present frame I
0be stored in texture storage device T
0in, three different resolution image I that form in sampling process
0, I
1, I
2be stored in respectively global storage G
0, G
1, G
2in.In the interior restructuring procedure of infra-frame prediction and frame, first carry out a data transfer, by image I for the first time
0copy texture storage device T to
1in, belong to the data copy in device end; For realizing the high speed access of thread, by three residual error plane R
41, R
42, R
43deposit respectively the shared storage S in block in
4in; Through the data R` of dct transform, quantification
41, R`
42, R`
43first be temporary in shared storage S`
4, then, import global storage G`
4, last, pass through G`
4copy back host side internal memory; Utilize decoded residual values reconstruct 1/2 image in different resolution I
c2, and be stored in texture storage device T
2in, as the reference picture of reconstruct in infra-frame prediction and frame next time.For the second time in infra-frame prediction and frame the memory module of compensation process to similar for the first time, wherein, R
21, R
22, R
23represent respectively three residual error planes that produce in process for the second time; R`
21, R`
22, R`
23representative is through three residual error planes of dct transform, quantification; I
c0for the original resolution frame of final reconstruct.The positional information of scanning is stored in constant storage (constant memory).
3. the execution flow process of thread:
(1) texture storage device T is set
1texture pick up function coordinates, the texture that block thread is carried out once linear filter patterns picks up.The original pixel value of the bilinear interpolation of returning and current location of interpolation is done to difference computing, and store residual values into distributed shared storage S
4in;
(2) carry out a conditional statement and change the number of threads that participates in computing, retain 2 warp and carry out dct transform, the value after conversion covers shared storage S
4middle data with existing;
(3) reactivate 16x16 thread, during block is individual, each thread is responsible for taking out S
4residual values after the conversion of correspondence position, and each value is carried out and once quantized and inverse quantization operation; Each thread obtains quantized data and is preserved by register temporarily, and the data after inverse quantization are stored in S
4in;
(4) data after quantification are carried out scan operation, and the each thread in block obtains data at shared storage S` by access constant storage
4in address information, and store value into S`
4in relevant position;
(5) carry out a conditional statement and change participation number of calculations, retain 2 warp to S
4middle data are carried out anti-dct transform, and result memory is arrived to S
4;
(6) reactivate 16x16 thread, during block is individual, each thread is responsible for taking out S
4the decoded residual values of correspondence position, and again carry out a texture with linear filtering pattern and pick up to return bilinear interpolation, carry out residual values and bilinear interpolation summation, do pixel reconstruction one time, and store reconstruction result into global storage G
2in, it is original that memory location meets this pixel image, and thread execution finishes;
The execution flow process of the thread institutional framework of other gpuKernelx function, memory model, thread is similar to gpuKernel1, is no longer repeated in this description.
Above embodiment does not form any restriction to invention, and the developer of correlative technology field can be without any creative work, and utilizes technical conceive of the present invention, develops efficient, real-time HD video coded system.
Claims (4)
1. a compression method in the frame of realizing based on CUDA, is characterized in that, comprising:
The prediction steps of luminance signal:
(1) the texture storage device T from host side memory copying to equipment end by the luminance signal of present frame
0in;
(2) in equipment end, luminance signal is carried out respectively to 4 times and 2 times of down-samplings, 1/16 1/4 image in different resolution, the pixel number that forms respectively pixel number and be luminance signal is luminance signal 1/4 1/2 image in different resolution;
(3) 1/4 image in different resolution is carried out to harmless I_PCM coding, described harmless I_PCM coding, be to original pixel value without conversion, quantization operation, and directly carry out lossless coding;
(4) 1/4 image in different resolution is copied to texture storage device T
1in, and utilize the filter function of texture storage device to carry out interpolation to 1/4 image in different resolution, form 1/2 resolution reference picture;
(5) 1/2 image in different resolution and 1/2 resolution reference picture are carried out to difference operation, form three residual error planes, and it is encoded;
(6) three residual error planes of decoding, and form 1/2 resolution reconstructed image with it;
(7) copy 1/2 resolution reconstructed image to texture storage device T
2in, and utilize its filter function to carry out interpolation to 1/2 resolution reconstructed image, form original resolution reference picture;
(8) original resolution image and original resolution reference picture are carried out to difference operation, form three residual error planes, and it is encoded;
(9) three residual error planes of decoding, and form original resolution reconstructed image with it;
The prediction steps of color difference signal is identical with luminance signal;
The process that described execution difference operation forms three residual error planes is: according to reference pixel around the direction of three interpolation reconfigure residual values, be equidirectionally combined in same plane; Described to three residual error plane coding processes is: each residual error plane is carried out respectively to dct transform, quantification, scanning, entropy encoding operation; Described to three residual error plane decode procedures is: after the quantization operations of each residual error plane coding executes, coded data is carried out to inverse quantization, the operation of anti-dct transform.
2. compression method in frame according to claim 1, it is characterized in that, in described step (4) and (7), described interpolation is bilinear interpolation, interpolation result be each reference pixel right-hand, below, lower right can produce three interpolating pixels.
3. compression method in frame according to claim 1, is characterized in that described texture storage device T
0, the addressing mode in the texture referential of its statement and filter patterns attribute are set to respectively clamper addressing and closest approach sampling mode.
4. compression method in frame according to claim 1, is characterized in that described texture storage device T
1with texture storage device T
2, the addressing mode in the texture referential of its statement and filter patterns attribute are set to respectively clamper addressing and linear filtering sampling mode.
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| CN108184116A (en) * | 2017-12-18 | 2018-06-19 | 西南技术物理研究所 | A kind of image rebuilding method suitable for the transmission of wireless data chain |
| CN109640084B (en) * | 2018-12-14 | 2021-11-16 | 网易（杭州）网络有限公司 | Video stream noise reduction method and device and storage medium |
| CN114827614B (en) * | 2022-04-18 | 2024-03-22 | 重庆邮电大学 | Method for realizing LCEVC video coding optimization |
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