CN102571137B - Fully-digital direct sequence spread spectrum communication system and rapid pseudo code capturing method thereof - Google Patents
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Abstract
The invention discloses a fully-digital direct sequence spread spectrum communication system and a rapid pseudo code capturing method thereof. A digital signal is processed by using an FPGA (Field Programmable Gate Array) which comprises a pseudo code capturing module, a sampling signal of an ADC (Analog To Digital Converter) is subjected to frequency mixing with a signal of a local carrier NCO (Numerically Controlled Oscillator) and filtered to obtain a baseband signal, residual carrier Doppler frequency is eliminated from the baseband signal by adopting a differential multiplying mode, thus the phase deviation of a receiving signal and a local pseudo code is further obtained through an FFT (Fast Fourier Transform) algorithm without scanning on a carrier frequency domain; and when the phase deviation of the pseudo code is obtained, a local pseudo code phase is modified and is subjected to correlation degree of dissociation with the receiving signal, and the carrier Doppler frequency is figured out by using the FFT algorithm, and is compensated to a carrier NCO and a pseudo code NCO, thus carrier frequency capturing and pseudo code capturing are realized.
Description
Technical field
The present invention relates to radio communication and digital processing field, relate in particular to a kind of digital direct sequence spread spectrum communication system and pseudo-code quick capturing method thereof be applied under large Doppler's condition.
Background technology
Direct Sequence Spread Spectrum Communication, because have strong anti-interference ability, strong anti-interception capability, confidentiality, be convenient to realize the advantage such as multiple access communication, becomes the major technique of modern communications gradually.
The principle of spread spectrum communication is to use the frequency spectrum of the frequency expansion sequence of two-forty at the transmitting terminal spread signal, and carries out despreading at receiving terminal with identical spread spectrum code sequence, and the spread-spectrum signal launched is reduced into to original signal.The direct sequence spread spectrum mode is directly modulated carrier wave by pseudo noise sequence, and the data message that transmit need to, after chnnel coding, carry out mould 2 and generate compound key with pseudo noise sequence removing modulated carrier.The pseudo noise sequence here is called pseudo-code, and the most frequently used have a GOLD code.
Catching of pseudo-code is the prerequisite that realizes spread spectrum communication, and more common method for acquiring pseudo code has at present: serial search methods and parallel search method.Serial search methods also is sliding correlation method, respectively pseudo-code phase and carrier doppler frequency is searched for, and searching times is many, and capture time is long.Parallel search method is divided into pseudo-code phase parallel search and carrier frequency parallel search, it reduces to linear search by the bidimensional search, reduces searching times, thereby has reduced capture time, but the situation long for the pseudo-code cycle, that Doppler frequency is large, still need the regular hour to be caught.For very short situations of time of passing by such as low-orbit satellite (LE0), rocket, guided missiles, it is very significant reducing as best one can capture time.
Summary of the invention
The invention provides a kind of digital direct sequence spread spectrum communication system and pseudo-code quick capturing method thereof, energy fast Acquisition pseudo-code also realizes demodulation, is applicable to low-orbit satellite (LE0), rocket, guided missile etc. and has large Doppler frequency deviation and pass by very short situation of time.
At first the present invention has disclosed a kind of digital direct sequence spread spectrum communication system, its receiving terminal comprises connected successively reception antenna, radio-frequency filter, low noise amplifier, frequency mixer, intermediate-frequency filter, and the frequency synthesizer be connected with described frequency mixer, with intermediate-frequency filter automatic gain control circuit in addition successively, AD analog to digital converter and a FPGA field programmable gate array module, described FPGA is connected with described frequency synthesizer, described FPGA is processed input signal, catch pseudo-code and carrier wave, and input signal is carried out to despreading, demodulated output data.
Further, this FPGA module comprises lower frequency mixing module, low pass filter blocks, carrier number controlled oscillator module, acquiring pseudo code module, Doppler effect correction module, pseudo-code recovery ring module, pseudo-code digital controlled oscillator module, pseudo-code generation module, despreading module, carrier wave FFT module and carrier recovery loop module; Wherein, the local carrier signal that the input signal of described FPGA and carrier number controlled oscillator module produce is sent into respectively lower frequency mixing module output mixed frequency signal, mixed frequency signal is through low pass filter blocks filtering two harmonic output baseband signals, described acquiring pseudo code module is processed baseband signal, obtain the pseudo-code phase signal, an input that outputs to the pseudo-code generation module is controlled pseudo-code phase; The output of described low pass filter blocks baseband signal be connected to described pseudo-code and recover the ring module, pseudo-code is recovered ring module generation phase demodulation error signal and is outputed to described pseudo-code digital controlled oscillator module controls digital controlled oscillator frequency, and the output of pseudo-code digital controlled oscillator module is as the clock signal of pseudo-code generation module; The output of the output of described low pass filter blocks and described pseudo-code generation module is connected with two inputs of described despreading module respectively, described despreading module despreading baseband signal demodulated output data; After despreading, signal is sent into carrier wave FFT module, delivers to the Doppler effect correction module after calculating the carrier doppler frequency deviation, produces two different compensating frequency values and outputs to respectively carrier number controlled oscillator module and pseudo-code digital controlled oscillator module; The output of described despreading module is connected with the input of described carrier recovery loop module simultaneously, and the output of carrier recovery loop module is connected with carrier number controlled oscillator module.
Further, described acquiring pseudo code module comprises Doppler's cancellation module, the FFT module, dot product module, the IFFT module, absolute value block, maximum module and threshold judgement module, the Doppler frequency that described Doppler's cancellation module makes to receive signal is 0, output to again the FFT module, the Output rusults of FFT and the local pseudo-code FFT result calculated are connected respectively to two inputs of described dot product module, output to the IFFT module after dot product, described absolute value block and maximum module the Output rusults of IFFT module is taken absolute value and after get maximum, whether described threshold judgement module relatively maximum surpasses thresholding, if maximum does not surpass thresholding, continue computing until have over threshold value and occur, catch if maximum over thresholding, is judged pseudo-code phase, obtain PRN phase error by the maximum position simultaneously.
Preferably, described Doppler's cancellation module realizes by the mode of difference, receives the signal multiplication after signal and the pseudo-code phase time delay of himself.
Preferably, after described acquiring pseudo code module obtains the poor estimated value of pseudo-code phase, revise local pseudo-code phase, output to described pseudo-code generation module, in described despreading module, to the baseband signal despreading, the signal after despreading obtains the carrier doppler frequency after described carrier wave FFT module.
Preferably, after carrier wave and acquiring pseudo code, carrier recovery loop and pseudo-code are recovered the ring closure and are realized loop-locking.
The present invention has also disclosed a kind of digital direct sequence spread spectrum pseudo-code quick capturing method, fast Acquisition pseudo-code phase in aforesaid direct sequence spread spectrum communication system, comprise the steps: that the local carrier signal that the input signal of (1) FPGA and carrier number controlled oscillator module produce sends into respectively lower frequency mixing module output mixed frequency signal, mixed frequency signal, through low pass filter blocks filtering two harmonic output baseband signals, is input to described acquiring pseudo code module;
(2) Doppler frequency that described acquiring pseudo code module makes to receive signal by described Doppler's cancellation module is 0, output to again the FFT module, the Output rusults of FFT and the local pseudo-code FFT result calculated are connected respectively to two inputs of described dot product module, the dot product module output is connected to the IFFT module, described absolute value block and maximum module the Output rusults of IFFT module is taken absolute value and after get maximum, whether described threshold judgement module relatively maximum surpasses thresholding, if maximum does not surpass thresholding, continue computing until have over threshold value and occur, catch if maximum over thresholding, is judged pseudo-code phase, obtain PRN phase error by the maximum position simultaneously,
(3), according to this phase difference, revise local pseudo-code phase.
After described acquiring pseudo code module obtains the poor estimated value of pseudo-code phase, revise local pseudo-code phase, output to described pseudo-code generation module, in described despreading module, to the baseband signal despreading, the signal after despreading obtains the carrier doppler frequency after described carrier wave FFT module.
Visible, in the present invention, on hardware, adopt and once descend the mixing structure, receive signal and be mixed to intermediate-freuqncy signal after amplification filtering, after AGC amplifies, by the ADC modulus conversion chip, realize the conversion from the analog domain to the numeric field.Digital Signal Processing realizes with the FPGA of an xilinx, the ADC sampled signal at first with the mixing of local carrier NCO signal, obtain afterwards after filtering baseband signal, baseband signal adopts the mode that difference multiplies each other to eliminate remaining carrier doppler frequency, thereby without in the enterprising line scanning in carrier frequency territory, just can once obtaining and receive signal and local pseudo-code phase deviation by fft algorithm, after obtaining the pseudo-code phase deviation, revise local pseudo-code phase, with reception signal correction, again utilize fft algorithm to calculate the carrier doppler frequency, and this frequency values is compensated on carrier wave NCO and pseudo-code NCO, thereby realize carrier frequency acquisition and acquiring pseudo code.
Compared with prior art, the present invention has following useful technique effect:
1) the present invention adopts the down-conversion structure one time, and ADC is owed sampling to higher intermediate-freuqncy signal, thereby has simplified the design of circuit, has reduced power consumption and the complexity of circuit, realizes Miniaturization Design;
2) the present invention realizes acquiring pseudo code, carrier wave and pseudo-code tracing and data demodulates in FPGA, bit rate, data rate can be arranged by the FPGA parameter, and receive the local oscillation signal frequency also by the FPGA configuration, can adapt to neatly the task of different carrier frequencies, different bit rate or different pieces of information speed.
3) the present invention adopts the method for difference and FFT combination, first utilize difference to remove carrier doppler, the method of recycling FFT pseudo-code phase parallel search is determined reception signal and local pseudo-code phase deviation, obtain pseudo-code phase poor after, revise local pseudo-code phase, and carry out related operation with the reception signal that does not carry out difference processing, the related operation result is not done to integral processing, but do the FFT computing, thereby obtain the carrier doppler frequency.The present invention realizes respectively the parallel search of pseudo-code phase and carrier frequency by twice FFT computing, thereby greatly reduces capture time.
The accompanying drawing explanation
Fig. 1 is the structural representation block diagram of the digital direct sequence spread spectrum communication system of the present invention;
Fig. 2 is FPGA internal module schematic block diagram in the present invention;
Fig. 3 is acquiring pseudo code modular structure schematic block diagram in the present invention;
Fig. 4 is the acquiring pseudo code signal flow diagram;
Fig. 5 is that pseudo-code phase is caught rear carrier frequency acquisition schematic diagram;
Fig. 6 is snr loss's schematic diagram that Doppler's cancellation module produces.
Embodiment
Describe the present invention in detail below in conjunction with embodiment and accompanying drawing, but the present invention is not limited to this.
As shown in Figure 1, a kind of digital direct sequence spread spectrum communication system, comprise radio-frequency filter, low noise amplifier, frequency synthesizer, frequency mixer, intermediate-frequency filter, AGC (automatic gain control circuit), AD analog to digital converter and FPGA (Field Programmable Gate Array, field programmable gate array) on hardware.Wherein, radio-frequency filter is connected with low noise amplifier, and the output of low noise amplifier is connected with two inputs of frequency mixer with the output of frequency synthesizer, and frequency mixer, intermediate-frequency filter, AGC, AD analog to digital converter and FPGA are connected successively.
Wherein analog circuit comprises radio-frequency filter, low noise amplifier, frequency synthesizer, frequency mixer, intermediate-frequency filter and AGC, purpose be by antenna reception to weak radio-frequency signal carry out filtering, amplification, down-conversion, and the intermediate-freuqncy signal after down-conversion is carried out to automatic gain and control that to make power output be constant, to realize large dynamic range.The frequency of frequency synthesizer is configured by FPGA when system initialization.
The analog signal of AGC output transforms to digital signal through the AD analog to digital converter and gives FPGA, the digital signal samples frequency f
s=40MHz, if require the intermediate-freuqncy signal frequency f of simulation
iFmeet nyquist sampling theorem and require to be less than f
s/ 2, down-conversion structure of the too low employing of IF-FRE can't the filtering image frequency so.So, in order to adapt to the down-conversion structure one time, adopted and owed sampling thheorem, IF-FRE f
s=Nf
iF+ f
c, wherein N is integer, as long as meet f
c<f
s/ 2 can be by the undistorted sampling of signal.
To the processing of digital signal, comprise acquiring pseudo code and tracking, carrier track, data demodulates etc., all complete in FPGA inside.As shown in Figure 2, FPGA inside comprises lower frequency mixing module, low pass filter blocks, carrier number controlled oscillator (carrier wave NCO) module, acquiring pseudo code module, Doppler effect correction module, pseudo-code recovery ring module, pseudo-code digital controlled oscillator (pseudo-code NCO) module, pseudo-code generation module, despreading module, carrier wave FFT module and carrier recovery loop module.The local carrier signal mixing that the input signal of FPGA and carrier wave NCO module produce is also exported baseband signals through low pass filter blocks filtering two harmonics, after the acquiring pseudo code module is processed baseband signal, obtain the pseudo-code phase signal, pseudo-code signal and reception signal correction despreading by this phase place, and do the FFT computing and obtain the carrier doppler frequency, thereby realize catching of carrier wave and pseudo-code; After carrier wave and acquiring pseudo code, carrier recovery loop and pseudo-code are recovered the ring closure and are realized loop-locking.
The acquiring pseudo code module comprises Doppler's cancellation module, FFT module, dot product module, IFFT module, absolute value block, maximum module and threshold judgement module.Their annexation as shown in Figure 3.
Fig. 4 has drawn the signal link of acquiring pseudo code, in the block diagram of dotted line, is the principle of Doppler's cancellation module, and time delay TD can be an integer pseudo-code chip lengths, a desirable chip time T C.
The mathematic(al) representation of the signal at first received is:
Wherein P is signal power, t
kfor sampling instant, d () means modulated information data, and c () means pseudo-code data, and η means the Doppler frequency deviation of pseudo-code, ω
iFmean IF-FRE, ω
dmean the carrier doppler frequency, θ
kfor carrier phase, n
kmean white Gaussian noise, wherein pseudo-code Doppler frequency deviation and carrier doppler frequency deviation meet and concern η=ω
d/ 2 π f
r, f
rfor the radio frequency receiving signal carrier frequency.
After down-conversion mixer module and low pass filter blocks, obtain:
D wherein
kd (t
k) abbreviation, c
k(τ) be c (t
k-τ) abbreviation, after Doppler cancels module, obtains:
A
k＝PVcos(Δω
dt
k-θ
k)cos[Δω
d(t
k-T
D)-θ
k)]+n
Ak (4)
B
k＝PVsin(Δω
dt
k-θ
k)cos[Δω
d(t
k-T
D)-θ
k)]+n
Bk (5)
C
k＝PVcos(Δω
dt
k-θ
k)sin[Δω
d(t
k-T
D)-θ
k)]+n
Ck (6)
D
k＝PVsin(Δω
dt
k-θ
k)sin[Δω
d(t
k-T
D)-θ
k)]+n
Dk (7)
V=d wherein
kd
k(T
d) c
k(τ) c
k(τ+T
d).D
k, d
k(T
d) sampling time poor be T
d, generally be far smaller than the information data cycle, so d
kd
k(T
d) approximate equal 1 always.And according to the shifter-adder theorem of m sequence: the multiply each other sequence that obtains of m sequence and the time delay sequence of himself remains himself another time delay sequence, i.e. c (t
k) c (t
k-d
1t
c)=c (t
k-d
2t
c), d wherein
1, d
2∈ [1, L-1], L is the m sequence length.Also meet this characteristic through emulation GOLD sequence.So V=c
k(τ+T
d) be still the reception pseudo-code sequence, just increased a constant time lag.
Signal after Doppler is eliminated is respectively got the two-way addition and subtracts each other, and obtains I, the Q two paths of signals is respectively:
I
k＝A
k+D
k＝PVcos(Δω
dT
D)+N
Ik (8)
Q
k＝C
k-B
k＝PVsin(Δω
dT
D)+N
Qk (9)
Δ ω in above formula
dt
dfor constant, can see in formula that the two-way I, the Q signal that make new advances do not have Doppler frequency, adopt so common FFT pseudo-code phase parallel capturing method just can obtain pseudo-code phase poor, as shown in Figure 4.
After the IFFT module calculates the poor estimated value of pseudo-code phase, revise local pseudo-code phase, and be used for and receive the signal correction despreading, obtain demodulating data.I after despreading, Q two paths of signals only comprise unknown quantity of carrier doppler frequency, as long as a FFT computing can obtain, through carrier wave FFT, calculate, and obtain Doppler frequency.
By twice FFT computing and an IFFT computing, all realize parallel search in pseudo-code phase and two search volumes of carrier doppler frequency, with respect to pseudo-code phase parallel search or carrier doppler frequency parallel search, acquiring pseudo code speed has improved 2～3 orders of magnitude, with respect to two traditional search volumes mode of the search of serial all, acquiring pseudo code speed has improved 4～5 orders of magnitude especially.
In above narration process, noise all not have to consideration, below separately the impact of noise is analyzed.
Expressions of noise in formula (1) is:
N wherein
ck, n
skbe separate zero-mean, variance is σ
2/ 2 white Gaussian noise.Obtaining expressions of noise in formula (2), formula (3) after lower mixing and filtering is:
v
ck＝n
ckcosΔω
dt
k-n
sksinΔω
dt
k (11)
v
sk＝n
cksinΔω
dt
k+n
skcosΔω
dt
k (12)
Because n
ck, n
skrelative Δ ω
dbroadband noise, to Δ ω
dinsensitive, so for simplicity, can be at Δ ω
din=0 situation, analyzed, thus v
ck=n
ck, v
sk=n
sk.C in addition
k, d
kvalue be random distribution+1/-1, can the distribution character of noise not exerted an influence, so do not need to consider yet.Therefore the noise that can derive in formula (4～7) is:
N in above formula
c1=n
c(t
k-T
d), n
c2=n
c(t
k), n
s1=n
s(t
k-T
d), n
s2=n
s(t
k), α
1=Δ ω
dt
d-θ
k, α
2=Δ ω
d(t
k-T
d)-θ
k, n wherein
c1, n
c2, n
s1, n
s2separate, and Normal Distribution.So have:
E(n
c1n
c2)＝E(n
c1)·E(n
c2)＝0(17)
Var(n
c1n
c2)＝E[(n
c1n
c2)
2]＝σ
4/4(18)
According to above formula, and the noise N in formula (8～9)
iK=n
ak+ n
dk, N
qK=n
ck-n
bk, obtain:
E(N
IK)＝E(N
QK)＝0(19)
Var(N
IK)＝Var(N
QK)＝Pσ
2+σ
4/2(20)
Can find out N in above formula
iK, N
qKno longer obey Gauss normal distribution, and noise variance is also relevant with input signal.Consider that the signal to noise ratio (SNR) that in Fig. 4, Z is ordered is
relevant with the signal to noise ratio that receives signal, their relation as shown in Figure 6.Dotted line reference line in Fig. 6 means is the signal to noise ratio that receives signal, can find out that in the situation that low signal-to-noise ratio, the snr loss that in Fig. 4, Z is ordered is very serious.(approximately be greater than 0dB) when signal to noise ratio is larger, the relative input signal of the signal to noise ratio that in Fig. 4, Z is ordered has the reduction of 3dB, illustrates that Doppler's cancellation module only introduced the snr loss of 3dB.
Claims (8)
1. a digital direct sequence spread spectrum communication system, its receiving terminal comprises connected successively reception antenna, radio-frequency filter, low noise amplifier, frequency mixer, intermediate-frequency filter, and the frequency synthesizer be connected with described frequency mixer, it is characterized in that: described receiving terminal also comprises connected successively automatic gain control circuit, AD analog to digital converter and a FPGA, the input of described automatic gain control circuit is connected with the output of described intermediate-frequency filter, described FPGA is connected with described frequency synthesizer, described FPGA is processed input signal, catch pseudo-code and carrier wave, and input signal is carried out to despreading, demodulated output data, described FPGA comprises lower frequency mixing module, low pass filter blocks, carrier number controlled oscillator module, acquiring pseudo code module, Doppler effect correction module, pseudo-code recovery ring module, pseudo-code digital controlled oscillator module, pseudo-code generation module, despreading module, carrier wave FFT module and carrier recovery loop module, wherein, the local carrier signal that the input signal of described FPGA and carrier number controlled oscillator module produce is sent into respectively lower frequency mixing module output mixed frequency signal, mixed frequency signal is through low pass filter blocks filtering two harmonic output baseband signals, described acquiring pseudo code module is processed baseband signal, obtain the pseudo-code phase signal, an input that outputs to the pseudo-code generation module is controlled pseudo-code phase, the output of described low pass filter blocks baseband signal be connected to described pseudo-code and recover the ring module, pseudo-code is recovered ring module generation phase demodulation error signal and is outputed to described pseudo-code digital controlled oscillator module controls digital controlled oscillator frequency, and the output of pseudo-code digital controlled oscillator module is as the clock signal of pseudo-code generation module, the output of the output of described low pass filter blocks and described pseudo-code generation module is connected with two inputs of described despreading module respectively, described despreading module despreading baseband signal demodulated output data, after despreading, signal is sent into carrier wave FFT module, delivers to the Doppler effect correction module after calculating the carrier doppler frequency deviation, produces two different compensating frequency values and outputs to respectively carrier number controlled oscillator module and pseudo-code digital controlled oscillator module, the output of described despreading module is connected with the input of described carrier recovery loop module simultaneously, and the output of carrier recovery loop module is connected with carrier number controlled oscillator module.
2. a kind of digital direct sequence spread spectrum communication system as claimed in claim 1, it is characterized in that: described acquiring pseudo code module comprises Doppler's cancellation module, the FFT module, dot product module, the IFFT module, absolute value block, maximum module and threshold judgement module, the Doppler frequency that described Doppler's cancellation module makes to receive signal is 0, output to again the FFT module, the Output rusults of FFT and the local pseudo-code FFT result calculated are connected respectively to two inputs of described dot product module, output to the IFFT module after dot product, described absolute value block and maximum module the Output rusults of IFFT module is taken absolute value and after get maximum, whether described threshold judgement module relatively maximum surpasses thresholding, if maximum does not surpass thresholding, continue computing until have over threshold value and occur, if maximum surpasses thresholding, judge the pseudo-code phase acquisition success, obtain PRN phase error by the maximum position simultaneously.
3. a kind of digital direct sequence spread spectrum communication system as claimed in claim 2 is characterized in that: described Doppler's cancellation module realizes by the mode of difference, receives the signal multiplication after signal and the pseudo-code phase time delay of himself.
4. a kind of digital direct sequence spread spectrum communication system as claimed in claim 2, it is characterized in that: after described acquiring pseudo code module obtains the poor estimated value of pseudo-code phase, revise local pseudo-code phase, output to described pseudo-code generation module, in described despreading module, to the baseband signal despreading, the signal after despreading obtains the carrier doppler frequency after described carrier wave FFT module.
5. a kind of digital direct sequence spread spectrum communication system as claimed in claim 4 is characterized in that: after carrier wave and acquiring pseudo code, carrier recovery loop and pseudo-code are recovered the ring closure and are realized loop-locking.
6. a digital direct sequence spread spectrum pseudo-code quick capturing method, in a kind of direct sequence spread spectrum communication system as claimed in claim 2, the fast Acquisition pseudo-code phase is poor, it is characterized in that, comprise the steps: that the local carrier signal that the input signal of (1) described FPGA and carrier number controlled oscillator module produce sends into respectively lower frequency mixing module output mixed frequency signal, mixed frequency signal, through low pass filter blocks filtering two harmonic output baseband signals, is input to described acquiring pseudo code module;
(2) Doppler frequency that described acquiring pseudo code module makes to receive signal by described Doppler's cancellation module is 0, output to again the FFT module, the Output rusults of FFT and the local pseudo-code FFT result calculated are connected respectively to two inputs of described dot product module, the dot product module output is connected to the IFFT module, described absolute value block and maximum module the Output rusults of IFFT module is taken absolute value and after get maximum, whether described threshold judgement module relatively maximum surpasses thresholding, if maximum does not surpass thresholding, continue computing until have over threshold value and occur, if maximum surpasses thresholding, judge the pseudo-code phase acquisition success, obtain PRN phase error by the maximum position simultaneously,
(3) pseudo-code phase obtained according to step (2) is poor, revises local pseudo-code phase.
7. a kind of digital direct sequence spread spectrum pseudo-code quick capturing method as claimed in claim 6 is characterized in that: described Doppler's cancellation module realizes by the mode of difference, receives the signal multiplication after signal and the pseudo-code phase time delay of himself.
8. a kind of digital direct sequence spread spectrum pseudo-code quick capturing method as claimed in claim 6, it is characterized in that: described step (3) is after described acquiring pseudo code module obtains the poor estimated value of pseudo-code phase, revise local pseudo-code phase, output to described pseudo-code generation module, in described despreading module, to the baseband signal despreading, the signal after despreading obtains the carrier doppler frequency after described carrier wave FFT module.
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| US7830991B2 (en) * | 2005-10-03 | 2010-11-09 | Harris Corporation | Frequency selective automatic gain control with dual non-symmetric attack and release times and interference detection feature |
| CN101082664B (en) * | 2007-07-03 | 2011-09-28 | 浙江大学 | Devices and methods for fast catching signal in high dynamic satellite navigation receiving machine |
| CN101267242A (en) * | 2008-05-04 | 2008-09-17 | 浙江大学 | A remote sensing data receiver for satellite territorial station |
| CN201315585Y (en) * | 2008-11-17 | 2009-09-23 | 中国人民解放军国防科学技术大学 | BD-I receiver module |
| CN101718874A (en) * | 2009-12-14 | 2010-06-02 | 浙江大学 | Method and device for fast capturing signal in high-sensitivity navigational satellite receiver |
| CN102104411B (en) * | 2010-12-29 | 2013-06-05 | 浙江大学 | Receiver circuit used for pico-satellite |
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| FR3091434A1 (en) * | 2018-12-27 | 2020-07-03 | Thales | Digitization process, associated digitizer and platform |
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