CN102571107B - System and method for decoding high-speed parallel Turbo codes in LTE (Long Term Evolution) system - Google Patents
System and method for decoding high-speed parallel Turbo codes in LTE (Long Term Evolution) system Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
- H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
- H03M13/3972—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using sliding window techniques or parallel windows
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
- H03M13/2957—Turbo codes and decoding
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Abstract
The invention provides a decoding method for Turbo codes. The method comprises the following steps of: firstly judging whether the length K of a code block is larger than 768, if so, storing the input three paths of soft information into an input storage unit segmentally, if not, storing the three paths of soft information into a preset input storage unit, then acquiring the values of the soft information from the preset input storage unit through a preset MAP (Maximum posterior probability) unit to carry out iteration decoding calculation, wherein the values generated during the decoding calculation is stored in a preset local storage unit; continuously judging whether the eight MAP units of a Turbo code decoder are in a ready state, if so, acquiring the values of the soft information from different input storage units by each MAP unit for carrying out iteration decoding calculation, wherein the values generated during the decoding calculation are respectively stored in a plurality of local storage units; finally, determining whether reaching the maximum times of iterations or whether passing the CRC (cyclic redundancy check), if so, carrying out hard decision output on the soft information, and storing the K output results in an output storage.
Description
Technical field
The present invention relates to a kind of decode system and method, relate in particular to decode system and the method for the parallel Turbo code of Long Term Evolution (Long TermEvolution, LTE) system high speed.
Background technology
In LTE system, require descending peak rate to reach 100Mb/s, up peak rate reaches 50Mb/s, this decoding speed to chnnel coding is had higher requirement, be applied at present the Turbo decoding algorithm in chip design, great majority are for Rel 6, if LTE continues to use the Turbo code coding/decoding method in Rel 6, cannot meet the requirement of above-mentioned data rate.
Implementation for the Turbo code decoding accelerator of LTE system is a lot, and known common method is as follows:
A kind of is that the sliding window method that Turbo code is decoded conventional is expanded as parallel method realization, and in Rel 6, the decoder of Turbo code adopts sliding window method conventionally, window and window are serial implementations, go up a window and calculate the complete calculating of carrying out again next window.And parallel sliding window method to be multiple sliding windows start simultaneously calculates, the training sequence of the reserved certain length of each window is as initial value.Aspect interleaver designs, according to the feature of the function that interweaves of LTE system, the function that interweaves of LTE is decomposed, the function that interweaves of LTE system is P (i)=(f
1* i+f
2* i
2) modK, wherein K is the length of decoder input bit, f
1, f
2get different values according to the value of block length K, specifically follow the example of the table 5.1.3-3 referring in LTE agreement 3GPP TS 36.212V8.5.0.Conventionally adopt the mode of iteration to obtain interleaving address, the i=i+1 that order interweaves in function, obtains P (i+1)=P (i)+(f
1+ f
2+ f
22i) modK, has avoided power operation.
Above-mentioned sliding window method, the number of window is at least 4, when enforcement, the number of common window is 8 or 16, so cause the length of window to shorten, because each window all will be reserved the training sequence of certain length (being at least 16 bits), when window length itself is not in situation about growing very much, expense computing time that training sequence takies can not be ignored, and the length of window and the length of training sequence shorten, and decoding performance can be greatly affected.The account form of above-mentioned interleaving address although avoided power operation, is calculated interleaving address at every turn, also can reduce the speed of decoder.
Also have some researchers to propose the immediate processing method of Radix-4 and Radix-8, but because these method critical paths increase, and the system cost resource magnitude such as also increases, in fact still exchange speed at double for by increase computing unit and memory cell at double, the performance of decoding accelerator is not had to essential improvement.
Summary of the invention
The object of the invention is to propose a kind of decode system and method for parallel Turbo code, apply system and method provided by the invention, can apply little memory cell, realize high-speed decoding, meet the demand of LTE system high-throughput, and there is good decoding performance.
For addressing the above problem, according to the decode system of a kind of Turbo code of the present invention, this system comprises:
Input store, in order to receive the soft information through coding of input;
Input control device, is connected with input store, the exporting in Turbo code decoder to soft input information and by information of control inputs memory;
Turbo code decoder, has multiple maximal posterior probability algorithms and realizes unit (MAP unit), and this MAP unit takes out the soft value of information from input store and carries out iterative decoding calculating;
Local memory, the value producing for storing Turbo code decoder computational process;
O controller, sentences Output rusults firmly in order to control Turbo code decoder;
Firmly sentence output storage, storage Turbo code decoder is sentenced Output rusults firmly.
According to above-mentioned principal character, described system is the Turbo code decode system of 8 parallel-by-bits in a kind of LTE of being applied to system.
According to above-mentioned principal character, described input store comprises 8 input memory cell.
According to above-mentioned principal character, described soft information is divided into three tunnel information according to system bits, the first check digit 1 and the second check digit 2.
According to above-mentioned principal character, described code block length is less than at 768 o'clock, does not carry out segment processing, and Jiang San road information leaves in the first input memory cell of input store; In the time that code block length is greater than 768, Jiang San road information is divided into respectively in 8 sections of 8 different input memory cell that leave this input store in.
According to above-mentioned principal character, described Turbo code decoder has 8 MAP unit, when these 8 MAP are after ready (Ready) state, takes out the soft value of information respectively carry out iterative decoding calculating from 8 different input memory cell.
According to above-mentioned principal character, described each MAP unit comprise first soft enter soft go out unit, the first external information computing unit, interleave unit, second soft enter soft go out unit, the second external information computing unit, deinterleaving unit, iteration control unit and softly enter firmly to go out firmly to sentence unit, wherein said first soft enter soft go out unit according to system bits, the first check digit 1 and external information are calculated log-likelihood information; The first described external information computing unit according to first soft enter soft go out the log-likelihood information of unit output and the external information of input calculate new external information; Described interleave unit interweaves system bits information and new external information; Described second soft enter soft go out unit calculate log-likelihood information according to interweaving information and the second check digit 2; The second described external information computing unit according to second soft enter soft go out the output of unit calculate an external information more accurately; Described deinterleaving unit accurately external information carries out deinterleaving; Described iteration control unit determines whether and stops iteration according to the external information after deinterleaving; Described softly enter firmly to go out firmly to sentence that unit sends according to iteration control unit stops the external information of iterative instruction after to deinterleaving and carry out hard decision output.
According to above-mentioned principal character, described local memory has 8 LSU local store units.
According to above-mentioned principal character, described 8 MAP unit and 8 LSU local store units are not one to one, and synchronization, do not have two MAP unit can access same LSU local store unit.
According to above-mentioned principal character, in the time that code block length is less than 768, do not carry out segment processing, only use a MAP unit and the first LSU local store unit.
For achieving the above object, the invention provides a kind of method of utilizing the decode system of above-mentioned Turbo code to decode to Turbo code, wherein the method comprises the steps:
Judge whether code block length K is greater than 768, i.e. step 1; In this way, the input three soft information in tunnel are left in the input memory cell of this input store;
Whether the multiple MAP unit that continues to judge Turbo code decoder is in Ready state;
When multiple MAP unit is all after Ready state, each MAP unit takes out the soft value of information from multiple different input memory cell respectively and carries out iterative decoding calculating, separates the value producing in Calculative Process and is stored in respectively in multiple LSU local store units;
Judging whether to reach maximum iteration time or cyclic redundancy (CRC) verification passes through; Soft information is sentenced to output firmly in this way, K Output rusults is kept in output storage, as otherwise return to step 1;
As code block length, K is less than or equal to 768, and code block does not carry out segment processing, and Jiang San road information leaves in a predetermined input memory cell of input store, continues afterwards to judge that whether a predetermined MAP unit of Turbo code decoder is in Ready state; So predetermined MAP unit is in Ready state, and this MAP unit takes out the soft value of information and carries out iterative decoding calculating from predetermined input memory cell, separates the value producing in Calculative Process and is stored in a predetermined LSU local store unit; Judge whether to reach maximum iteration time or CRC check is passed through; Soft information is sentenced to output firmly in this way, K Output rusults is kept in output storage, as otherwise return to step 1.
According to above-mentioned principal character, this Turbo code decoder has 8 MAP unit, be respectively the first to the 8th MAP unit, the decode system of this Turbo code is also provided with 8 LSU local store units accordingly, be respectively the first to the 8th LSU local store unit, and input store has 8 input memory cell, be respectively the first to the 8th input memory cell, as code block length, K is less than or equal to 768, Ze Jiang tri-tunnel information leave in the first input memory cell of input store, follow-uply from the first input memory cell, take out the soft value of information by a MAP unit and carry out iterative decoding calculating, separating the value producing in Calculative Process is stored in the first LSU local store unit.
According to above-mentioned principal character, in step 2, the soft information of input is divided into three road d1, d2, d3, wherein the length of d1, d2, d3 is respectively K+4, and Jiang San road information is divided into respectively in 8 sections of 8 different input memory cell that leave this input store in.
According to above-mentioned principal character, in step 5, described each MAP unit comprise first soft enter soft go out unit, the first external information computing unit, interleave unit, second soft enter soft go out unit, the second external information computing unit, deinterleaving unit, iteration control unit and softly enter firmly to go out firmly to sentence unit, the handling process of inside, each MAP unit comprises:
Step 1: by system bits d1
(i), check information d2
(i)and external information be input to first soft enter soft go out unit, calculate log-likelihood information, wherein i=1 ..., 8, represent the input of 8 different input memory cell;
Step 2: the first external information computing unit calculates new external information according to the external information of log-likelihood information and input;
Step 3: interleave unit is by system bits d1
(i), after new external information interweaves, with check information d3
(i)be input to together second soft enter soft go out unit, calculate log-likelihood information;
Step 4: the second external information computing unit utilize second soft enter soft go out the output of unit calculate an external information more accurately;
Step 5: deinterleaving unit carries out deinterleaving to the external information calculating;
Step 6: iteration control unit first carries out CRC computing to the external information after deinterleaving, if CRC check is not passed through, then judges whether to reach maximum iteration time;
Step 7: if CRC check by or reach maximum iteration time, carry out hard decision output decoded result, as do not reach maximum iteration time and return to step 1.
According to above-mentioned principal character, described first and second soft enter soft go out unit adopt the maximal posterior probability algorithm (Max-Log-MAP algorithm) of revising and the correction maximal posterior probability algorithm (Max*-Log-MAP algorithm) of simplifying add operation with Jacobi's formula.
According to above-mentioned principal character, soft enter soft go out unit is inner adopts forward-facing branch tolerance α value and backward bifurcation to measure β value to carry out the scheme to pushing away simultaneously; Its specific practice be from single soft enter soft go out the end of data segment of cell processing utilize reverse recursion formula to calculate the β value in each moment, calculate first symbol of this section always, and the β value that each moment calculates stored.Meanwhile, start to calculate the α value in each moment of this section from the beginning of data segment with forward recursive formula, until last symbol of this section stores the α value in this section moment.Each moment after decoding proceeds to middle moment of this section all can utilize the summation of multiplying each other of the α value that calculates and the β value in corresponding moment to obtain corresponding likelihood output, and now each moment can obtain the likelihood output of two bits.
According to above-mentioned principal character, the Initialization Algorithms of described forward-facing branch tolerance α value and backward bifurcation tolerance β value is: the result that the border initial value of this iteration adopts last iteration to obtain, and the while calculates the border initial value of next iteration in this iteration; Its concrete implementation method is as follows:
(1) for iteration for the first time, α and the β on border are all assumed to be and are uniformly distributed, wherein except the α initial value of first paragraph and the β initial value of final stage, both of these case is nought state maximum probability, under the initial condition of the border of this supposition, each MAP unit by soft enter soft go out the forward-facing branch tolerance α value of inside, unit and backward bifurcation measure the algorithm that β value carries out pushing away simultaneously and carry out decoding, calculate the border initial value of next iteration simultaneously and store;
(2) for non-iteration first, the result that the α on border and β all adopt last iteration to calculate, wherein except the α initial value of first paragraph and the β initial value of final stage, both of these case is nought state maximum probability, under this initial condition, each MAP unit by soft enter soft go out the forward-facing branch tolerance α value of inside, unit and backward bifurcation measure the algorithm that β value carries out pushing away simultaneously and carry out decoding, calculate the border initial value of next iteration simultaneously and upgrade the value of last stored.
According to above-mentioned principal character, the method utilizes same module realization to interweave and deinterleaving process, first address generator is for generating the address of reading of external information memory, first soft enter soft go out when the each external information of unit latches, read address latch simultaneously, when first soft enter soft go out after unit calculates the external information value making new advances, this new external information is write back to it and reads address; In later half iterative process, when second soft enter soft go out unit calculate after the external information making new advances, just this external information is stored again into the address of initial latch, the deinterleaving process completing like this; And each code block, and the code block of length only carries out primary address calculating equally, is not that each iteration all will be carried out address computation.
Compared with prior art, tool of the present invention has the following advantages:
(1) the inner parallel processing mode that adopts of parallel block, the inner mode that adopts forward-facing branch tolerance α and the parallel relative calculating of backward bifurcation tolerance of parallel block, has so improved processing speed;
(2) grey iterative generation interleaving address at every turn in de-interweaving method, has improved processing speed;
(3) compared with common sliding window method, do not need increase to push away in advance length, greatly reduce computation complexity and improved processing speed;
(4) compare with the method that pushes away in advance of common sliding window method, employing last iteration result provided by the invention, as the method for initial value, has higher decoding performance;
(5) in the time that code length is less than 768, automatically transfer the executive mode of serial to, processing has met the requirement of processing speed like this, makes again performance increase.
Brief description of the drawings
Fig. 1 is for implementing system architecture diagram of the present invention.
Fig. 2 is for implementing flow chart of the present invention.
Fig. 3 is the structure composed figure that implements MAP of the present invention unit.
Fig. 4 is the details flow chart of a step shown in Fig. 2.
Fig. 5 to Fig. 8 is the details flow chart of a step shown in Fig. 2.
Fig. 9 is the performance comparison diagram of sliding window method and the method provided by the invention of prior art.
Embodiment
Below in conjunction with accompanying drawing, decode system and the method for implementing the parallel Turbo code of LTE system high speed of the present invention are specifically described.
Refer to shown in Fig. 1, for implementing system architecture diagram of the present invention, this decode system comprises:
Input store, in order to receive the soft information through coding of input, this input store comprises 8 input memory cell in the present embodiment, be respectively the first to the 8th input memory cell, this soft information comprises system bits, check digit 1 and check digit 2, specify according to LTE agreement, its length is 3*K+12, wherein K is code block length, d1, d2, the length of d3 is respectively K+4, Jiang San road information is divided into respectively in 8 sections of 8 different input memory cell that leave this input store in, in the time of code block length K < 768, do not carry out segment processing, Jiang San road information leaves in the first input memory cell of input store,
Input control device, is connected with input store, the exporting in Turbo code decoder to soft input information and by information of control inputs memory;
Turbo code decoder, has 8 MAP unit, is respectively the first to the 8th MAP unit, when these 8 MAP are after Ready state, takes out the soft value of information respectively carry out iterative decoding calculating from 8 different input memory cell;
Local memory, there are 8 LSU local store units, the value producing for store M AP unit decodes computational process, due to the interior existence interweaving, 8 MAP unit and 8 LSU local store units are not one to one, namely not necessarily first LSU local store unit of LSU local store unit of a MAP unit read-write, but synchronization, do not have two MAP unit can access same LSU local store unit, this is that LTE determines without the feature of the interleaver of contention, in the time that code block length K is less than 768, do not carry out segment processing, only use a MAP unit and the first LSU local store unit,
O controller, sentences Output rusults firmly in order to control Turbo code decoder;
Firmly sentence output storage, storage Turbo code decoder is sentenced Output rusults firmly.
Refer to shown in Fig. 2, for implementing flow chart of the present invention, comprise the steps:
Step 200: judge whether code block length K is greater than 768; In this way, carry out step 201, be about to the input three soft information d1 in tunnel, d2, d3 (length is respectively K+4) and be divided into respectively in 8 sections of 8 different input memory cell that leave this input store in;
Step 203: whether 8 MAP unit that continue to judge Turbo code decoder are in Ready state;
Step 204: when 8 MAP unit are all after Ready state, each MAP unit takes out the soft value of information from 8 different input memory cell respectively and carries out iterative decoding calculating, separates the value producing in Calculative Process and is stored in respectively in 8 LSU local store units;
Step 206: judge whether to reach maximum iteration time or CRC check is passed through; Carry out step 207 in this way, be about to soft information is sentenced to output firmly, K Output rusults is kept in output storage, as otherwise return to step 200;
As code block length, K is less than or equal to 768, carry out step 202, code block does not carry out segment processing, and Jiang San road information leaves in the first input memory cell of input store, whether a MAP unit that continues afterwards to judge Turbo code decoder is in Ready state, i.e. step 208; Carry out step 205 afterwards, only from the first input memory cell, taking out the soft value of information by a MAP unit carries out iterative decoding calculating, separates the value producing in Calculative Process and is stored in the first LSU local store unit; Judge whether afterwards to reach maximum iteration time or CRC check is passed through; Carry out step 209 in this way, be about to soft information is sentenced to output firmly, K Output rusults is kept in output storage, as otherwise return to step 200.
Refer to shown in Fig. 3, for implementing the structure composed figure of MAP of the present invention unit, this MAP unit by first soft enter soft go out unit, the first external information computing unit, interleave unit, second soft enter soft go out unit, the second external information computing unit, deinterleaving unit, iteration control unit, softly enter firmly to go out firmly to sentence unit composition, wherein:
Described first soft enter soft go out unit according to system bits, the first check digit 1 and external information are calculated log-likelihood information;
The first described external information computing unit according to first soft enter soft go out the log-likelihood information of unit output and the external information of input calculate new external information;
Described interleave unit interweaves system bits information and new external information;
Described second soft enter soft go out unit calculate log-likelihood information according to interweaving information and the second check digit 2;
The second described external information computing unit according to second soft enter soft go out the output of unit calculate an external information more accurately;
Described deinterleaving unit accurately external information carries out deinterleaving;
Described iteration control unit determines whether and stops iteration according to the external information after deinterleaving;
Described softly enter firmly to go out firmly to sentence that unit sends according to iteration control unit stops the external information of iterative instruction after to deinterleaving and carry out hard decision output.
Refer to shown in Fig. 4, for each MAP unit in Fig. 3 carries out the details flow chart of iterative decoding, comprise the steps:
Step 400: by system bits d1
(i), check information d2
(i)and external information is input to the first soft soft cell S ISO1 of going out of entering, calculate log-likelihood information, wherein i=1 ..., 8, represent the input of 8 different input memory cell;
Step 401: the first external information computing unit calculates new external information according to the external information of log-likelihood information and input;
Step 402: interleave unit is by system bits d1
(i), after new external information interweaves, with check information d3
(i)be input to together the second soft soft cell S ISO2 of going out of entering, calculate log-likelihood information;
Step 403: the second external information computing unit utilizes the output of SISO2 to calculate an external information more accurately;
Step 404: deinterleaving unit carries out deinterleaving to the external information calculating;
Step 405: iteration control unit first carries out CRC computing (CRC specifying in LTE system) to the external information after deinterleaving, if CRC check is not passed through, then judges whether to reach maximum iteration time.
Step 406: if CRC check by or reach maximum iteration time, carry out hard decision output decoded result, as do not reach maximum iteration time and forward step 400 to.
Referring to shown in Fig. 5 to Fig. 8, is the flow chart of SISO1 computational methods in Fig. 2, and SISO2 is similar to SISO1 computational methods, no longer repeated description.In the method, adopt the maximal posterior probability algorithm (Max-Log-MAP algorithm) of the correction of conventionally using in engineering application, Max-Log-MAP algorithm is mainly that forward-facing branch tolerance α and backward bifurcation tolerance β are calculated, realize iterative decoding by state transitions, other guide has announcement in the prior art, no longer describe in detail herein, mainly illustrate how α value and β value realize parallel computation.
Soft enter soft go out (SISO) inner α value and β value of adopting carry out the scheme to pushing away simultaneously.Specific practice is to utilize reverse recursion formula to calculate the β value in each moment from the end of the data segment of single SISO processing, calculates first symbol of this section always, and the β value that each moment calculates is stored.Meanwhile, start to calculate the α value in each moment of this section from the beginning of data segment with forward recursive formula, until last symbol of this section stores the α value in this section moment.Said process as shown in Figure 5.In the time that decoding proceeds to the middle moment of this section, each moment all can utilize the summation of multiplying each other of the α value that calculates and the β value in corresponding moment to obtain corresponding likelihood output backward, and now each moment can obtain the likelihood output of two bits, as shown in Figure 7.
In force, suppose that code length is N, degree of parallelism is P, is equivalent to have P MAP decoder to decode simultaneously, and it is N/P that each decoder needs code word number to be processed.Be equivalent to original code length to be divided into P section, each section is decoded by a decoder respectively.Because P MAP decoder decoded simultaneously, therefore therefore all uncertain (except the α initial value of first paragraph and β initial value of final stage) of the α initial value of each segment encode and β initial value need to solve each data section boundary initial-value problem.
The present invention, by the result that makes the border initial value of this iteration adopt last iteration to obtain, calculates the border initial value of next iteration simultaneously in this iteration, and concrete implementation method is as follows:
1. for iteration for the first time, the α on border and β are all assumed to be and are uniformly distributed (except the α initial value of first paragraph and the β initial value of final stage, both of these case is nought state maximum probability), under the initial condition of the border of this supposition, decode by the single MAP unit internal algorithm shown in Fig. 5 and Fig. 6 in each MAP unit, calculate the border initial value of next iteration simultaneously and store, as shown in Figure 7.
2. for non-iteration first, the α on border and β all adopt result that last iteration calculates (except the α initial value of first paragraph and the β initial value of final stage, both of these case is nought state maximum probability), under this initial condition, decode according to the single MAP unit internal algorithm shown in Fig. 5 and Fig. 6 in each MAP unit, calculate the border initial value of next iteration simultaneously and upgrade the value of last stored, as shown in Figure 8.
Completing above-mentioned forward-facing branch tolerance α and backward bifurcation tolerance β calculates output likelihood information and just can carry out the calculating of external information.
In addition, the reconciliation interleaving process that interweaves of the present invention can be realized by same module, as interweaving in Fig. 3 can be merged into an address generator module with deinterleaving.First address generator, for generating the address of reading of external information memory, when the each external information of SISO1 latch, is read address latch simultaneously, after SISO1 calculates the external information value making new advances, this new external information is write back to it and read address.In later half iterative process, when SISO2 calculates after the external information making new advances, just this external information is stored again into the address of initial latch, the deinterleaving process completing like this, and each code block, and the code block of length only carries out primary address calculating equally, is not that each iteration all will be carried out address computation.
In the time implementing, the present invention realizes with 8 bits, and main memory is constructed as follows shown in table
| Title | Number | Type | The degree of depth | Bit bit wide |
| The soft bit of system | 8×2 | Twoport | 768 | 8 |
| The soft bit of check digit 1 | 8×2 | Twoport | 768 | 8 |
| The soft bit of check digit 2 | 8×2 | Twoport | 768 | 8 |
| α and β | 8 | Single port | 384 | 128 |
| The soft bit of external information | 8×2 | Twoport | 768 | 9 |
| Interleaving address table | 2 | ROM | 44387/2 | 34 |
According to the standard of LTE, per secondly to transmit 102K information bit, if be to calculate for 9 times according to maximum iteration time, clock frequency is 102*1000*1000*2*9/8=229.5MHZ, considers other expenses, main clock frequency requires to be not less than 240MHZ.
Compared with prior art, tool of the present invention has the following advantages:
(1) the inner parallel processing mode that adopts of parallel block, the inner mode that adopts forward-facing branch tolerance α and the parallel relative calculating of backward bifurcation tolerance of parallel block, has so improved processing speed;
(2) grey iterative generation interleaving address at every turn in de-interweaving method, has improved processing speed;
(3) compared with common sliding window method, do not need increase to push away in advance length, greatly reduce computation complexity and improved processing speed;
(4) compare with the method that pushes away in advance of common sliding window method, employing last iteration result provided by the invention, as the method for initial value, has higher decoding performance, and concrete simulation result as shown in Figure 9;
(5) in the time that code length is less than 768, automatically transfer the executive mode of serial to, processing had both met the requirement of processing speed like this, made again performance increase.
Claims (15)
1. a decode system for Turbo code, is characterized in that, comprising:
Input store, in order to receive the soft information through coding of input;
Input control device, is connected with input store, and control inputs memory exports in Turbo code decoder to soft input information and by information;
Turbo code decoder, has multiple MAP unit, and this MAP unit takes out the soft value of information from input store and carries out iterative decoding calculating;
Local memory, the value producing for storing Turbo code decoder computational process;
O controller, sentences Output rusults firmly in order to control Turbo code decoder;
Firmly sentence output storage, storage Turbo code decoder is sentenced Output rusults firmly;
Wherein, described soft information is divided into three tunnel information according to system bits, the first check digit 1 and the second check bit 2;
In the time that code block length K is less than 768, do not carry out segment processing, Jiang San road information leaves in the first input memory cell of input store; In the time that code block length K is greater than 768, Jiang San road information is divided into respectively in 8 sections of 8 different input memory cell that leave this input store in;
Described Turbo code decoder has 8 MAP unit, when these 8 MAP are after Ready state, takes out the soft value of information respectively carry out iterative decoding calculating from 8 different input memory cell.
2. the decode system of Turbo code according to claim 1, is characterized in that, described decode system is the Turbo code decode system of 8 parallel-by-bits in a kind of LTE of being applied to system.
3. the decode system of Turbo code according to claim 1, is characterized in that, described input store comprises 8 input memory cell.
4. the decode system of Turbo code according to claim 1, it is characterized in that, described each MAP unit comprise first soft enter soft go out unit, the first external information computing unit, interleave unit, second soft enter soft go out unit, the second external information computing unit, deinterleaving unit, iteration control unit and softly enter firmly to go out firmly to sentence unit, wherein
Described first soft enter soft go out unit according to system bits, the first check digit 1 and external information are calculated log-likelihood information;
The first described external information computing unit according to first soft enter soft go out the log-likelihood information of unit output and the external information of input calculate new external information;
Described interleave unit interweaves system bits information and new external information;
Described second soft enter soft go out unit calculate log-likelihood information according to interweaving information and the second check digit 2;
The second described external information computing unit according to second soft enter soft go out the output of unit calculate an external information more accurately;
Described deinterleaving unit accurately external information carries out deinterleaving;
Described iteration control unit determines whether and stops iteration according to the external information after deinterleaving;
Described softly enter firmly to go out firmly to sentence that unit sends according to iteration control unit stops the external information of iterative instruction after to deinterleaving and carry out hard decision output.
5. the decode system of Turbo code according to claim 1, is characterized in that, described local memory has 8 LSU local store units.
6. the decode system of Turbo code according to claim 5, is characterized in that, described 8 MAP unit and 8 LSU local store units are not one to one, and synchronization, do not have two MAP unit can access same LSU local store unit.
7. the decode system of Turbo code according to claim 5, is characterized in that, in the time that code block length is less than 768, does not carry out segment processing, only uses a MAP unit and the first LSU local store unit.
8. a method of utilizing the decode system of the Turbo code described in claim 1 to decode to Turbo code, is characterized in that the method comprises the steps:
Judge whether code block length K is greater than 768, i.e. step 1; In this way, the input three soft information in tunnel are left in the input memory cell of this input store;
Whether the multiple MAP unit that continues to judge Turbo code decoder is in Ready state;
When multiple MAP unit is all after Ready state, each MAP unit takes out the soft value of information from multiple different input memory cell respectively and carries out iterative decoding calculating, separates the value producing in Calculative Process and is stored in respectively in multiple LSU local store units;
Judge whether to reach maximum iteration time or CRC check is passed through; Soft information is sentenced to output firmly in this way, K Output rusults is kept in output storage, as otherwise return to step 1;
As code block length, K is less than or equal to 768, and code block does not carry out segment processing, and Jiang San road information leaves in a predetermined input memory cell of input store, continues afterwards to judge that whether a predetermined MAP unit of Turbo code decoder is in Ready state; So predetermined MAP unit is in Ready state, and this MAP unit takes out the soft value of information and carries out iterative decoding calculating from predetermined input memory cell, separates the value producing in Calculative Process and is stored in a predetermined LSU local store unit; Judge whether to reach maximum iteration time or CRC check is passed through; Soft information is sentenced to output firmly in this way, K Output rusults is kept in output storage, as otherwise return to step 1.
9. method according to claim 8, it is characterized in that, this Turbo code decoder has 8 MAP unit, be respectively the first to the 8th MAP unit, the decode system of this Turbo code is also provided with 8 LSU local store units accordingly, be respectively the first to the 8th LSU local store unit, and input store has 8 input memory cell, be respectively the first to the 8th input memory cell, as code block length, K is less than or equal to 768, Ze Jiang tri-tunnel information leave in the first input memory cell of input store, follow-uply from the first input memory cell, take out the soft value of information by a MAP unit and carry out iterative decoding calculating, separating the value producing in Calculative Process is stored in the first LSU local store unit.
10. method according to claim 9, it is characterized in that, in step 2, the soft information of input is divided into three road d1, d2, d3, wherein the length of d1, d2, d3 is respectively K+4, and Jiang San road information is divided into respectively in 8 sections of 8 different input memory cell that leave this input store in.
11. methods according to claim 9, it is characterized in that, in the present invention, described each MAP unit comprise first soft enter soft go out unit, the first external information computing unit, interleave unit, second soft enter soft go out unit, the second external information computing unit, deinterleaving unit, iteration control unit and softly enter firmly to go out firmly to sentence unit, the handling process of inside, each MAP unit comprises:
Step 1: by system bits d1
(i), the first check information d2
(i)and external information be input to first soft enter soft go out unit, calculate log-likelihood information, wherein i=1 ..., 8, represent the input of 8 different input memory cell;
Step 2: the first external information computing unit calculates new external information according to the external information of log-likelihood information and input;
Step 3: interleave unit is by system bits d1
(i), after new external information interweaves, with the second check information d3
(i)be input to together second soft enter soft go out unit, calculate log-likelihood information;
Step 4: the second external information computing unit utilize second soft enter soft go out the output of unit calculate an external information more accurately;
Step 5: deinterleaving unit carries out deinterleaving to the external information calculating;
Step 6: iteration control unit first carries out CRC computing to the external information after deinterleaving, if CRC check is not passed through, then judges whether to reach maximum iteration time;
Step 7: if CRC check by or reach maximum iteration time, carry out hard decision output decoded result, as do not reach maximum iteration time and return to step 1.
12. methods according to claim 11, is characterized in that, described first and second soft enter soft go out unit adopt the maximal posterior probability algorithm of revising and the correction maximal posterior probability algorithm of simplifying add operation with Jacobi's formula.
13. methods according to claim 12, is characterized in that, soft enter soft go out unit is inner adopts forward-facing branch tolerance α value and backward bifurcation to measure β value to carry out the scheme to pushing away simultaneously; Its specific practice be from single soft enter soft go out the end of data segment of cell processing utilize reverse recursion formula to calculate the β value in each moment, calculate first symbol of this section always, and the β value that each moment calculates stored.Meanwhile, start to calculate the α value in each moment of this section from the beginning of data segment with forward recursive formula, until last symbol of this section stores the α value in this section moment.Each moment after decoding proceeds to middle moment of this section all can utilize the summation of multiplying each other of the α value that calculates and the β value in corresponding moment to obtain corresponding likelihood output, and now each moment can obtain the likelihood output of two bits.
14. methods according to claim 13, it is characterized in that, the Initialization Algorithms of described forward-facing branch tolerance α value and backward bifurcation tolerance β value is: the result that the border initial value of this iteration adopts last iteration to obtain, and the while calculates the border initial value of next iteration in this iteration; Its concrete implementation method is as follows:
(1) for iteration for the first time, α and the β on border are all assumed to be and are uniformly distributed, wherein except the α initial value of first paragraph and the β initial value of final stage, both of these case is nought state maximum probability, under the initial condition of the border of this supposition, each MAP unit by soft enter soft go out the forward-facing branch tolerance α value of inside, unit and backward bifurcation measure the algorithm that β value carries out pushing away simultaneously and carry out decoding, calculate the border initial value of next iteration simultaneously and store;
(2) for non-iteration first, the result that the α on border and β all adopt last iteration to calculate, wherein except the α initial value of first paragraph and the β initial value of final stage, both of these case is nought state maximum probability, under this initial condition, each MAP unit by soft enter soft go out the forward-facing branch tolerance α value of inside, unit and backward bifurcation measure the algorithm that β value carries out pushing away simultaneously and carry out decoding, calculate the border initial value of next iteration simultaneously and upgrade the value of last stored.
15. methods according to claim 12, it is characterized in that, the method utilizes same module realization to interweave and deinterleaving process, first address generator is for generating the address of reading of external information memory, first soft enter soft go out when the each external information of unit latches, read simultaneously latch of address, when first soft enter soft go out after unit calculates the external information value making new advances, this new external information is write back to it and reads address; In later half iterative process, when second soft enter soft go out unit calculate after the external information making new advances, just this external information is stored again into the address of initial latch, the deinterleaving process completing like this; And each code block, and the code block of length only carries out primary address calculating equally, is not that each iteration all will be carried out address computation.
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| CN1349357A (en) * | 2000-10-16 | 2002-05-15 | Lg电子株式会社 | Method for executing Tebo decoding in mobile communication system |
| CN1349361A (en) * | 2000-10-16 | 2002-05-15 | Lg电子株式会社 | Method for decoding Tebo code |
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| CN1349357A (en) * | 2000-10-16 | 2002-05-15 | Lg电子株式会社 | Method for executing Tebo decoding in mobile communication system |
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