CN102570784B - Power on/reset circuit and method for controlling start/reset state of digital circuit - Google Patents
Power on/reset circuit and method for controlling start/reset state of digital circuit Download PDFInfo
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Abstract
The invention discloses a power on/reset circuit and a method for controlling the start/reset state of a digital circuit. The power on/reset circuit comprises a voltage follow-up module, a reverse amplifying module, and at least one first transistor connected in series in a cascode manner, wherein the voltage follow-up module generates a first analog signal, and the potential level of the first analog signal changes with that of a first DC voltage source; the reverse amplifying module is used for reversing the potential logic of the first analog signal, generating a second analog signal; and the first transistor is used for adjusting the second analog signal, so as to enable the potential of a start/reset signal controlled by the second analog signal to be enough for rightly operating the digital circuit at the rear end.
Description
Technical field
The present invention discloses a kind of method of electric power starting/reset circuit and the unlatching/Reset Status of relevant control figure circuit, espespecially one include at least one with string transistorized electric power starting/reset circuit that repeatedly (Stack) mode is connected the method to the unlatching/Reset Status of relevant control figure circuit.
Background technology
General integrated circuit is in order to integrate more function, is mostly system single chip (System-on-a-chip, SOC) with the kenel of mixed mode (mixed-mode), consist essentially of digital circuit and analog circuit, and digital circuit part is except providing control, logical operation, data storing etc. function, also need to comprise the setting of integrated circuit initial conditions (initial condition), and the setting of the initial value of initial conditions need to there is a so-called unlatching/reset signal (Power on/Reset Signal).
Refer to Fig. 1 and Fig. 2, it is the schematic diagram of disclosed two kinds of integrated circuits in prior art.The illustrated integrated circuit 100 of Fig. 1 comprises electric power starting/reset circuit (Power On/Reset Circuit) 110, pressurizer (Regulator) 120, electric power starting/replacement pulse generator 130 and digital circuit 140.Electric power starting/reset circuit 110 is supplied power supply with pressurizer 120 with direct voltage source VDD.Electric power starting/reset circuit 110 is used for producing unlatching/reset signal, with in good time decision unlatching or the opportunity of replacement digital circuit 140; The power supply that unlatching/reset signal that electric power starting/replacement pulse generator 130 can produce according to electric power starting/reset circuit 110 and pressurizer 120 provide produces replacement pulse, makes digital circuit 140 to be activated or to reset according to the time of enabling corresponding to described unlatching/reset signal.In like manner, the illustrated integrated circuit 200 of Fig. 2 comprises electric power starting/reset circuit 110, pressurizer 120, electric power starting/replacement pulse generator 230 and digital circuit 140.Electric power starting/replacement pulse generator 230 described unlatching/reset signal that the power supply that provides according to pressurizer 120 and electric power starting/reset circuit 110 produce is also provided and produces described replacement pulse, with the opportunity that determines that digital circuit 140 is unlocked or is reset.General integrated circuit is realized its replacement to digital circuit in the mode shown in Fig. 1 or Fig. 2.
In ideal conditions, supply with the voltage source V DD of integrated circuit 100 and 200 and only can be unlocked once, follow and continue to carry out its running.But when actual use or test, have nonideal situation and occur, make electric power starting repeat continuously to produce with closing.For example: the voltage source that offers integrated circuit is unlocked by initial state, voltage source current potential rises to 3 volts by 0 volt, and then be closed because of voltage source, the current potential of described voltage source drops to 0.9 volt by 3 volts, at this moment voltage source is just unlocked again, the current potential of voltage source rises to 3 volts by 0.9 volt, nonideal variation like this.
Refer to Fig. 3, its electric power starting/reset circuit 250 for normal use in prior art is used for producing the schematic diagram of above-mentioned unlatching/reset signal.As shown in Figure 3, electric power starting/reset circuit 250 comprises voltage follower module 310, P type MOS (metal-oxide-semiconductor) transistor QS1, N-type MOS (metal-oxide-semiconductor) transistor QS2 and reverser INV, and wherein voltage follower module 310 is powered with a direct current voltage source V CC.The potential change that the current potential of the voltage V1 that voltage follower module 310 produces can followed direct voltage source VCC.P type MOS (metal-oxide-semiconductor) transistor QS1 and N-type MOS (metal-oxide-semiconductor) transistor QS2 implement the function of reverser to voltage V1, make the current potential of produced voltage V2 contrary with voltage V1.Last voltage V2 is converted into the unlatching/reset signal shown in Fig. 3 via the running of reverser INV again.For example, in electric power starting/reset circuit 250, the current potential of voltage source V CC rises to 3 volts by 0 volt, the current potential of voltage V1 can followed voltage source V CC and risen, when the voltage quasi position of voltage V1 not yet rises to while being enough to trigger the reverser being made up of transistor QS 1 and transistor QS2, the potential change of voltage V2 is equal to the potential change of voltage source V CC, make to be coupled to reverser INV thereafter output now and maintain low-voltage level 0V, that is the now digital circuit of output LOW voltage level replacement rear end of unlatching/reset signal.Then voltage V1 rises to while being enough to trigger the reverser being made up of transistor QS1 and transistor QS2, voltage V2 transition is low-voltage level, be coupled to 3 volts of reverser INV output HIGH voltage levels thereafter, to finish the replacement of electric power starting/reset circuit 250 to digital circuit.
But when producing as mentioned above by 3 volts, the current potential of voltage source V CC next drops to 0.9 volt while rising to again the situation of change of 3 volts, electric power starting/the reset circuit 250 of prior art by can not be again to the digital circuit of rear end in to reset, but 0.9 volt of the potential minimum of voltage source V CC in this potential change process is concerning general digital circuit, lower than minimum voltage level that can normal operation, therefore make recorded data in described digital circuit enter a unknown state (Unknown Status), finally cause described digital circuit cannot continue normal operation, this is to follow because of the voltage V1 in electric power starting/reset circuit 250 voltage quasi position that voltage source V CC changes, be not enough to make the reverser being formed by transistor QS1 and transistor QS2 again to trigger due to transition.
Summary of the invention
The object of the present invention is to provide the method for the unlatching/Reset Status of a kind of power-on circuit and relevant control digital circuit, so that the current potential of unlatching/replacement signal can be opened the digital circuit of rear end really, and solve the problem that cannot reopen smoothly digital circuit in known technology.
Based on above-mentioned purpose, the present invention discloses a kind of electric power starting/reset circuit.Described electric power starting/reset circuit comprises voltage follower module, reverse amplification module and at least one is with the string the first transistor that repeatedly mode is connected.Described voltage follower module is coupled to the first direct voltage source.Described voltage follower module produces the first analog signal.The current potential height of described the first analog signal changes the current potential height variation of following described the first direct voltage source.Described reverse amplification module is used for receiving described the first analog signal and produces the second analog signal.Described in the current potential logical AND of described the second analog signal, the current potential logic of the first analog signal is contrary.Described electric power starting/reset circuit carrys out the unlatching/Reset Status of control figure circuit according to described the second analog signal.The described reverse amplification module utilization string transistorized mode that changes goes to adjust described the second analog signal.
Described reverse amplification module comprises one first N-type MOS (metal-oxide-semiconductor) transistor and one the one P type MOS (metal-oxide-semiconductor) transistor.The grid of described the first N-type MOS (metal-oxide-semiconductor) transistor is coupled to an output of described voltage follower module to receive described the first analog signal.The grid of a described P type MOS (metal-oxide-semiconductor) transistor is coupled to the grid of described the first N-type MOS (metal-oxide-semiconductor) transistor.The source electrode of a described P type MOS (metal-oxide-semiconductor) transistor is coupled to one second direct voltage source.And the drain electrode of a described P type MOS (metal-oxide-semiconductor) transistor is coupled to the drain electrode of described the first N-type MOS (metal-oxide-semiconductor) transistor and exports described the second analog signal.The described the first transistor that is coupled to described reverse amplification module in described at least one the first transistor is coupled to the source electrode of described the first N-type MOS (metal-oxide-semiconductor) transistor.
The current potential of described the second direct voltage source is higher than the current potential of described the first direct voltage source.
Described electric power starting/reset circuit separately comprises that at least one is with the string transistor seconds that repeatedly mode is connected, and wherein a transistor seconds is coupled to described the second direct voltage source, and separately has a transistor seconds to be coupled to the source electrode of a described P type MOS (metal-oxide-semiconductor) transistor.
Described at least one the first transistor is N-type MOS (metal-oxide-semiconductor) transistor, and described at least one transistor seconds is P type MOS (metal-oxide-semiconductor) transistor.
Described at least one the first transistor is P type MOS (metal-oxide-semiconductor) transistor, and described at least one transistor seconds is N-type MOS (metal-oxide-semiconductor) transistor.
Described at least one the first transistor is npn type bipolar junction transistor, and described at least one transistor seconds is pnp type bipolar junction transistor.
Described at least one the first transistor is pnp type bipolar junction transistor, and described at least one transistor seconds is npn type bipolar junction transistor.
Described reverse amplification module comprises one first N-type MOS (metal-oxide-semiconductor) transistor and one the one P type MOS (metal-oxide-semiconductor) transistor.The grid of described the first N-type MOS (metal-oxide-semiconductor) transistor is coupled to an output of described voltage follower module to receive described the first analog signal.The grid of a described P type MOS (metal-oxide-semiconductor) transistor is coupled to the grid of described the first N-type MOS (metal-oxide-semiconductor) transistor, the source electrode of a described P type MOS (metal-oxide-semiconductor) transistor is coupled to one second direct voltage source, and the drain electrode of a described P type MOS (metal-oxide-semiconductor) transistor is coupled to the drain electrode of described the first N-type MOS (metal-oxide-semiconductor) transistor and exports described the second analog signal.The described the first transistor that is coupled to described reverse amplification module in described at least one the first transistor is coupled to the source electrode of a described P type MOS (metal-oxide-semiconductor) transistor.
The current potential of described the second direct voltage source is higher than the current potential of described the first direct voltage source.
Described electric power starting/reset circuit separately comprises that at least one is with the string transistor seconds that repeatedly mode is connected, and wherein a transistor seconds is coupled to the source electrode of described the first N-type MOS (metal-oxide-semiconductor) transistor.
Described at least one the first transistor is N-type MOS (metal-oxide-semiconductor) transistor, and described at least one transistor seconds is P type MOS (metal-oxide-semiconductor) transistor.
Described at least one the first transistor is P type MOS (metal-oxide-semiconductor) transistor, and described at least one transistor seconds is N-type MOS (metal-oxide-semiconductor) transistor.
Described at least one the first transistor is npn type bipolar junction transistor, and described at least one transistor seconds is pnp type bipolar junction transistor.
Described at least one the first transistor is pnp type bipolar junction transistor, and described at least one transistor seconds is npn type bipolar junction transistor.
Described voltage follower module comprises one the one P type MOS (metal-oxide-semiconductor) transistor, one the 2nd P type MOS (metal-oxide-semiconductor) transistor, one the 3rd P type MOS (metal-oxide-semiconductor) transistor, one first N-type MOS (metal-oxide-semiconductor) transistor, one second N-type MOS (metal-oxide-semiconductor) transistor, one the 3rd N-type MOS (metal-oxide-semiconductor) transistor, one the 4th N-type MOS (metal-oxide-semiconductor) transistor and one the 5th N-type MOS (metal-oxide-semiconductor) transistor.The source electrode of a described P type MOS (metal-oxide-semiconductor) transistor is coupled to described the first direct voltage source.The source electrode of described the 2nd P type MOS (metal-oxide-semiconductor) transistor is coupled to drain electrode and the grid of a described P type MOS (metal-oxide-semiconductor) transistor.The base stage of described the 2nd P type MOS (metal-oxide-semiconductor) transistor is coupled to the base stage of a described P type MOS (metal-oxide-semiconductor) transistor.The source electrode of described the 3rd P type MOS (metal-oxide-semiconductor) transistor is coupled to the source electrode of a described P type MOS (metal-oxide-semiconductor) transistor.The grid of described the 3rd P type MOS (metal-oxide-semiconductor) transistor is coupled to the grid of a described P type MOS (metal-oxide-semiconductor) transistor.The drain electrode of described the 3rd P type MOS (metal-oxide-semiconductor) transistor is coupled to the grid of described the 2nd P type MOS (metal-oxide-semiconductor) transistor.The drain electrode of described the first N-type MOS (metal-oxide-semiconductor) transistor is coupled to the drain electrode of described the 3rd P type MOS (metal-oxide-semiconductor) transistor and the grid of described the 2nd P type MOS (metal-oxide-semiconductor) transistor.The drain electrode of described the second N-type MOS (metal-oxide-semiconductor) transistor is coupled to the source electrode of described the first N-type MOS (metal-oxide-semiconductor) transistor and the grid of described the second N-type MOS (metal-oxide-semiconductor) transistor, and the source ground of described the second N-type MOS (metal-oxide-semiconductor) transistor.The source ground of described the 3rd N-type MOS (metal-oxide-semiconductor) transistor, the grid of described the 3rd N-type MOS (metal-oxide-semiconductor) transistor is coupled to the grid of described the second N-type MOS (metal-oxide-semiconductor) transistor, and the drain electrode of described the 3rd N-type MOS (metal-oxide-semiconductor) transistor is coupled to the grid of described the first N-type MOS (metal-oxide-semiconductor) transistor.The drain electrode of described the 4th P type MOS (metal-oxide-semiconductor) transistor is coupled to the drain electrode of described the 3rd N-type MOS (metal-oxide-semiconductor) transistor, and the grid of described the 4th P type MOS (metal-oxide-semiconductor) transistor is coupled to the grid of described the second N-type MOS (metal-oxide-semiconductor) transistor.The drain electrode of described the 5th P type MOS (metal-oxide-semiconductor) transistor is coupled to the source electrode of described the 4th P type MOS (metal-oxide-semiconductor) transistor, the grid of described the 5th P type MOS (metal-oxide-semiconductor) transistor is coupled to the grid of described the 4th P type MOS (metal-oxide-semiconductor) transistor, and the source electrode of described the 5th P type MOS (metal-oxide-semiconductor) transistor is coupled to the source electrode of a described P type MOS (metal-oxide-semiconductor) transistor.
Described electric power starting/reset circuit separately comprises an electric current supply device and an inverted logic module.Described electric current supply device is coupled to described the first direct voltage source, and is used for producing an electric current.Described inverted logic module is coupled to described reverse amplification module to receive described the second analog signal, and is coupled to described electric current supply device to be driven by described electric current.The intensity that described electric current supply device is also used for controlling described electric current is below a critical current intensity.Described inverted logic module is reversed the current potential logic of described the second analog signal to produce one unlatching/reset signal, makes described electric power starting/reset circuit control the unlatching/Reset Status of described digital circuit by described unlatching/reset signal.
Described electric current supply device comprises one second N-type MOS (metal-oxide-semiconductor) transistor, one the 3rd N-type MOS (metal-oxide-semiconductor) transistor, one the 4th N-type MOS (metal-oxide-semiconductor) transistor, one the 5th P type MOS (metal-oxide-semiconductor) transistor, one the 6th P type MOS (metal-oxide-semiconductor) transistor.The drain electrode of described the second N-type MOS (metal-oxide-semiconductor) transistor is coupled to the grid of described the first direct voltage source and described the second N-type MOS (metal-oxide-semiconductor) transistor.The grid of described the 3rd N-type MOS (metal-oxide-semiconductor) transistor is coupled to the grid of described the second N-type MOS (metal-oxide-semiconductor) transistor.The grid of described the 4th N-type MOS (metal-oxide-semiconductor) transistor is coupled to the grid of described the 3rd N-type MOS (metal-oxide-semiconductor) transistor.The grid of described the 5th P type MOS (metal-oxide-semiconductor) transistor and drain electrode are coupled to the drain electrode of described the 3rd N-type MOS (metal-oxide-semiconductor) transistor, and the source electrode of described the 5th P type MOS (metal-oxide-semiconductor) transistor is coupled to described the first direct voltage source.The grid of described the 6th P type MOS (metal-oxide-semiconductor) transistor is coupled to the grid of described the 5th P type MOS (metal-oxide-semiconductor) transistor, and the source electrode of described the 6th P type MOS (metal-oxide-semiconductor) transistor is coupled to described the first direct voltage source.Described inverted logic module comprises one the 7th P type MOS (metal-oxide-semiconductor) transistor and one the 5th N-type MOS (metal-oxide-semiconductor) transistor.The grid of described the 7th P type MOS (metal-oxide-semiconductor) transistor is coupled to described CMOS.The source electrode of described the 7th P type MOS (metal-oxide-semiconductor) transistor is coupled to the drain electrode of described the 6th P type MOS (metal-oxide-semiconductor) transistor.The grid of described the 5th N-type MOS (metal-oxide-semiconductor) transistor is coupled to the grid of described the 7th P type MOS (metal-oxide-semiconductor) transistor.The drain electrode of described the 5th N-type MOS (metal-oxide-semiconductor) transistor is coupled to the drain electrode of described the 7th P type MOS (metal-oxide-semiconductor) transistor.The source electrode of described the 5th N-type MOS (metal-oxide-semiconductor) transistor is coupled to the drain electrode of described the 4th N-type MOS (metal-oxide-semiconductor) transistor.The base stage of described the 7th P type MOS (metal-oxide-semiconductor) transistor is coupled to described the first direct voltage source, and the base stage of described the 5th N-type MOS (metal-oxide-semiconductor) transistor is coupled to the base stage of described the 4th N-type MOS (metal-oxide-semiconductor) transistor.
Based on above-mentioned purpose, the present invention discloses a kind of method of unlatching/Reset Status of control figure circuit.Described method comprises makes the current potential height of the first analog signal change the current potential height variation of following the first direct voltage source; The current potential logic of described the first analog signal of reversing, and improve or reduce the current potential of described first analog signal of reversal potential logic, to produce the second analog signal; Adjust the beginning condition that opens in when reversion, and adjust described the second analog signal in the string transistorized mode that changes; And with described the second open/reset signal of analog signal control one, and by the unlatching/Reset Status of described unlatching/reset signal control one digital circuit.
Described method separately comprises that the current potential logic of described the second analog signal of reversing is to produce described unlatching/reset signal, to control the unlatching/Reset Status of described digital circuit by described unlatching/reset signal.
According to technique scheme, scanning means of the present invention at least has following advantages and beneficial effect: the current potential logic of reversion the first analog signal is to produce the second analog signal, and adjust the second analog signal with the first transistor, make the current potential of unlatching/reset signal that the second analog signal controls be enough to correctly operate the digital circuit of rear end.
Brief description of the drawings
Fig. 1 and Fig. 2 are the schematic diagram of disclosed two kinds of integrated circuits in prior art.
Fig. 3 is the normal schematic diagram that uses electric power starting/reset circuit in prior art.
Fig. 4 is for disclosing the detailed maps of the electric power starting/reset circuit shown in Fig. 3 according to embodiments of the invention.
Fig. 8-13 are the schematic diagram of the different embodiment of reverse amplification module shown in Fig. 4.
Fig. 5 is that the transistor group that comprises of the reverse amplification module shown in Fig. 8 is by comprising at least one with the string transistor that repeatedly mode is connected, the schematic diagram that the voltage transitions indicatrix of anti-phase amplification module is moved right.
Fig. 6 and Fig. 7 signal are inputted respectively a nonideal voltage source after the electric power starting/reset circuit shown in the electric power starting/reset circuit shown in Fig. 3 and Fig. 4, separately the waveform schematic diagram of output unlatching/replacement signal.
The generalized schematic of the How It Works of Figure 14 is Fig. 4-13 exposure electric power starting/reset circuit.
Wherein, description of reference numerals is as follows:
100,200 integrated circuits
250,300 electric power startings/reset circuit
120 pressurizers
130 electric power startings/replacement pulse generator
140 digital circuits
230 electric power startings/replacement pulse generator
310 voltage follower modules
330 electric current supply devices
340 inverted logic modules
402,404,406,408 steps
I1, I2, I3 equivalent current source
C1, C2, C3 electric capacity
Q11, Q12, Q13, Q14, Q15, Q16, transistor
Q17、Q18、Q21、Q22、Q31、Q32、
Q33、Q34、Q35、Q36、Q37、Q38、
Q39、Q40、QN1、QNm、QP1、QPm、
Qnpn1、Qnpnm、Qpnp1、Qpnpm、
QS?1、QS2
V1, V2 analog voltage
Vout unlatching/reset signal
TN, TP, Tnpn, Tpnp transistor group
VDD1, VDD2, VCC direct voltage source
CM, INV reverser
Embodiment
Refer to Fig. 4, it is the schematic diagram of electric power starting/reset circuit 300 disclosed in this invention.As shown in Figure 4, electric power starting/reset circuit 300 comprises voltage follower module 310, reverse amplification module 320, electric current supply device 330 and inverted logic module 340.Please refer to Fig. 8, it is according to the detailed maps of the reverse amplification module 320 shown in the disclosed Fig. 4 of embodiments of the invention.As shown in Figure 8, reverse amplification module 320 comprises reverser CM and transistor group TN.
Voltage follower module 310 comprises P type MOS (metal-oxide-semiconductor) transistor Q12, Q13, Q14, Q17, Q18, N-type MOS (metal-oxide-semiconductor) transistor Q11, Q15, Q16 and capacitor C 1, and is coupled to direct voltage source VDD1 to form the equivalent current source I1 shown in Fig. 4.The source electrode of P type MOS (metal-oxide-semiconductor) transistor Q12 is coupled to direct voltage source VDD1.The source electrode of P type MOS (metal-oxide-semiconductor) transistor Q13 is coupled to drain electrode and the grid of P type MOS (metal-oxide-semiconductor) transistor Q12.The base stage of P type MOS (metal-oxide-semiconductor) transistor Q13 is coupled to the base stage of P type MOS (metal-oxide-semiconductor) transistor Q12.The source electrode of P type MOS (metal-oxide-semiconductor) transistor Q14 is coupled to the source electrode of P type MOS (metal-oxide-semiconductor) transistor Q12.The grid of P type MOS (metal-oxide-semiconductor) transistor Q14 is coupled to the grid of P type MOS (metal-oxide-semiconductor) transistor Q12.The drain electrode of P type MOS (metal-oxide-semiconductor) transistor Q14 is coupled to the grid of P type MOS (metal-oxide-semiconductor) transistor Q13.The drain electrode of N-type MOS (metal-oxide-semiconductor) transistor Q11 is coupled to the drain electrode of P type MOS (metal-oxide-semiconductor) transistor Q14 and the grid of P type MOS (metal-oxide-semiconductor) transistor Q13.The drain electrode of N-type MOS (metal-oxide-semiconductor) transistor Q15 is coupled to the source electrode of N-type MOS (metal-oxide-semiconductor) transistor Q11 and the grid of N-type MOS (metal-oxide-semiconductor) transistor Q15.The source ground of N-type MOS (metal-oxide-semiconductor) transistor Q15.The source ground of N-type MOS (metal-oxide-semiconductor) transistor Q16.The grid of N-type MOS (metal-oxide-semiconductor) transistor Q16 is coupled to the grid of N-type MOS (metal-oxide-semiconductor) transistor Q15.The drain electrode of N-type MOS (metal-oxide-semiconductor) transistor Q16 is coupled to the grid of N-type MOS (metal-oxide-semiconductor) transistor Q11.The drain electrode of P type MOS (metal-oxide-semiconductor) transistor Q17 is coupled to the drain electrode of N-type MOS (metal-oxide-semiconductor) transistor Q16.The grid of P type MOS (metal-oxide-semiconductor) transistor Q17 is coupled to the grid of N-type MOS (metal-oxide-semiconductor) transistor Q15.The drain electrode of P type MOS (metal-oxide-semiconductor) transistor Q18 is coupled to the source electrode of P type MOS (metal-oxide-semiconductor) transistor Q17.The grid of P type MOS (metal-oxide-semiconductor) transistor Q18 is coupled to the grid of P type MOS (metal-oxide-semiconductor) transistor Q17.The source electrode of P type MOS (metal-oxide-semiconductor) transistor Q18 is coupled to the source electrode of P type MOS (metal-oxide-semiconductor) transistor Q12.In voltage follower module 310, the potential change of analog signal V1 can be followed the potential change of direct voltage source VDD1, that is the current potential of unlatching/reset signal Trig1 is followed the situation of the current potential of direct voltage source VDD1 described in prior art.
Transistor group TN comprise at least one with string repeatedly mode (Stack) series connection N-type MOS (metal-oxide-semiconductor) transistor QN1 ..., QNm.Wherein transistor QN1 is coupled to CMOS CM, the source ground of transistor QNm.Reverser CM comprises P type MOS (metal-oxide-semiconductor) transistor Q21 and N-type MOS (metal-oxide-semiconductor) transistor Q22.The grid of N-type MOS (metal-oxide-semiconductor) transistor Q22 is coupled to the output of voltage follower module 310 to receive analog signal V1.The grid of P type MOS (metal-oxide-semiconductor) transistor Q21 is coupled to the grid of N-type MOS (metal-oxide-semiconductor) transistor Q22.The source electrode of P type MOS (metal-oxide-semiconductor) transistor Q21 is coupled to direct voltage source VDD2, and the Q21 of P type MOS (metal-oxide-semiconductor) transistor drain electrode is coupled to drain electrode the outputting analog signal V2 of N-type MOS (metal-oxide-semiconductor) transistor Q22, wherein the polarities of potentials of analog signal V2 is in contrast to analog signal V1, and the foundation of analog signal V2 its unlatching/Reset Status of Digital Circuit Control that is rear end.The drain electrode of transistor QN1 is coupled to the source electrode of N-type MOS (metal-oxide-semiconductor) transistor Q22.
Electric current supply device 330 comprises N-type MOS (metal-oxide-semiconductor) transistor Q31, Q32, Q37 and P type MOS (metal-oxide-semiconductor) transistor Q33, Q34.The equivalent current source I2 that the drain electrode of N-type MOS (metal-oxide-semiconductor) transistor Q31 produces by electric current supply device 330 is coupled to the grid of direct voltage source VDD1 and N-type MOS (metal-oxide-semiconductor) transistor Q31.The grid of N-type MOS (metal-oxide-semiconductor) transistor Q32 is coupled to the grid of N-type MOS (metal-oxide-semiconductor) transistor Q31.The grid of N-type MOS (metal-oxide-semiconductor) transistor Q37 is coupled to the grid of N-type MOS (metal-oxide-semiconductor) transistor Q32.The grid of P type MOS (metal-oxide-semiconductor) transistor Q33 and drain electrode are coupled to the drain electrode of N-type MOS (metal-oxide-semiconductor) transistor Q32.And the source electrode of P type MOS (metal-oxide-semiconductor) transistor Q33 is coupled to direct voltage source VDD1.The grid of P type MOS (metal-oxide-semiconductor) transistor Q34 is coupled to the grid of P type MOS (metal-oxide-semiconductor) transistor Q33.The source electrode of P type MOS (metal-oxide-semiconductor) transistor Q34 is coupled to direct voltage source VDD1.Electric current supply device comprises three P type MOS (metal-oxide-semiconductor) transistor Q38, Q39, Q40 in addition.The grid of P type MOS (metal-oxide-semiconductor) transistor Q38, Q39, Q40 couples and ground connection all each other mutually.The source electrode of P type MOS (metal-oxide-semiconductor) transistor Q38 is coupled to direct voltage source VDD1.The drain electrode of P type MOS (metal-oxide-semiconductor) transistor Q38 is coupled to the source electrode of P type MOS (metal-oxide-semiconductor) transistor Q39.The drain electrode of P type MOS (metal-oxide-semiconductor) transistor Q39 is coupled to the source electrode of P type MOS (metal-oxide-semiconductor) transistor Q40.The drain electrode of P type MOS (metal-oxide-semiconductor) transistor Q40 is coupled to the drain electrode of N-type MOS (metal-oxide-semiconductor) transistor Q31.
Inverted logic module 340 comprises P type MOS (metal-oxide-semiconductor) transistor Q35 and N-type MOS (metal-oxide-semiconductor) transistor Q36.The grid of P type MOS (metal-oxide-semiconductor) transistor Q35 is coupled to reverser CM.The source electrode of P type MOS (metal-oxide-semiconductor) transistor Q35 is coupled to the drain electrode of P type MOS (metal-oxide-semiconductor) transistor Q34.The grid of N-type MOS (metal-oxide-semiconductor) transistor Q36 is coupled to the grid of P type MOS (metal-oxide-semiconductor) transistor Q35.The drain electrode of N-type MOS (metal-oxide-semiconductor) transistor Q36 is coupled to the drain electrode of P type MOS (metal-oxide-semiconductor) transistor Q35.The source electrode of N-type MOS (metal-oxide-semiconductor) transistor Q36 is coupled to the drain electrode of N-type MOS (metal-oxide-semiconductor) transistor Q37.The base stage of P type MOS (metal-oxide-semiconductor) transistor Q35 is coupled to direct voltage source VDD1.The base stage of N-type MOS (metal-oxide-semiconductor) transistor Q36 is coupled to the base stage of N-type MOS (metal-oxide-semiconductor) transistor Q37.Wherein transistor Q34, Q35 produce an equivalent capacitor C 2 at output voltage V out place, and transistor Q36, Q37 produce equivalent capacity C3 at output voltage V out place.Inverted logic module 340 obtains its needed operating current by electric current supply device 330 included transistor Q32, Q33, Q34, Q37, electric current supply device 330 is also used for described operating current to be controlled at below critical current intensity, to produce unlatching/reset signal Vout of node between capacitor C 2 and C3 as shown in Figure 4; Current potential logical AND the second analog signal V2 of unlatching/reset signal Vout is contrary, and is directly used in unlatching/Reset Status of controlling above-mentioned digital circuit, in other words, can indirectly control the unlatching/Reset Status of above-mentioned digital circuit by the second analog signal V2.
In the reverse amplification module 320 shown in the unlatching/reset circuit 300 shown in Fig. 4 and Fig. 8, at the voltage of node N1 (being positioned at the grid of N-type MOS (metal-oxide-semiconductor) transistor Q11) along with voltage source V DD1 provides and rises, when the voltage of node N1 rises to after enough unlatchings (turn on) Q11 transistor, current source I1 charges to capacitor C 1 through P type MOS (metal-oxide-semiconductor) transistor Q12 and Q13.Because of the charging of capacitor C1, produce analog signal V1 and offer reverse amplification module 320 in drain electrode place of transistor Q13.The current potential of analog signal V1 can directly have influence on the current potential of the analog signal V2 that reverse amplification module 320 exports, and the current potential of analog signal V2 also can have influence on the current potential being used to provide to unlatching/reset signal Vout of rear end digital circuit.Fig. 5 is that the transistor group that comprises of the reverse amplification module shown in Fig. 8 is by comprising that at least one is with the string transistor that repeatedly mode is connected, the schematic diagram that the voltage transitions indicatrix of anti-phase amplification module is moved right.
Refer to Fig. 5, the transistor group TN that reverse amplification module 320 comprises, by comprising that at least one is with the string transistor that repeatedly mode is connected, the voltage transitions feature of anti-phase amplification module 320 (voltagetransfer characteristic) curve L1 is moved right to L2, make analog signal V1 aforementioned direct voltage source VDD1 because of power-off (for example current potential is die-offed to 0.9 volt by 3 volts) and then direct voltage source VDD1 for example by chance open again, in (current potential rises to 3 volts again by 0.9 volt) process, analog signal V2 is triggered transition again, that is to say that reverse amplification module 320 can be via inverted logic module 340, send unlatching/reset signal Vout to open/replacement of numeral as shown in Figure 1-2 pulse generator 230, and then generation one replacement pulse, with by the digital circuit shown in Fig. 1-2 140 in reset.
Refer to Fig. 6 and Fig. 7, wherein two figure input respectively a nonideal voltage source V DD1 (voltage source V DD1 repeat continuously produce open and close situation, as mentioned in prior art) after the electric power starting/reset circuit 300 shown in the electric power starting/reset circuit 250 as shown in Fig. 3 and Fig. 8, the waveform schematic diagram of output unlatching/reset signal Vout separately.Observation Fig. 6 is known, unlatching/reset signal Vout is also following by 3 volts and is dropping to 0.9 volt in the time that the current potential of imperfect voltage source V DD1 drops to 0.9 volt by 3 volts, and directly go up to 3 volts by 0.9 volt immediately, therefore can produce unlatching/reset signal as described in the prior art and cannot effectively reopen the problem of the digital circuit of rear end.And it is known to review Fig. 7, unlatching/reset signal Vout drops to 0.9 volt and following while dropping to 0.9 volt by 3 volts at the current potential of imperfect voltage source V DD1 by 3 volts, can be subject to the impact of reverser CM and transistor group TN and of short duration be pulled down to 0 volt, then just by 0 volt of rise to 3 volt, therefore the current potential of unlatching/reset signal Vout is enough to make the digital circuit of rear end to produce once effectively unlatching, and has avoided the problem that cannot reopen smoothly as described in the prior art.
In other embodiments of the invention, transistor group TN shown in Fig. 8 can be replaced by the transistor group TP shown in transistor group Tpnp, the Figure 11 shown in transistor group Tnpn, the Figure 10 shown in Fig. 9 separately, and reaches the object identical with the group of transistor shown in Fig. 8 TN; Wherein transistor group Tnpn include at least one with string npn type double carrier transistor Qnpn1 that repeatedly mode is connected ..., Qnpnm, transistor group Tpnp include at least one with string pnp type double carrier transistor Qnpn1 that repeatedly mode is connected ..., Qnpnm, and transistor group TP include at least one with string P type MOS (metal-oxide-semiconductor) transistor QP1 that repeatedly mode is connected ..., QPm.
In addition, in part embodiment of the present invention, the setting position of transistor group TN, TP, Tnpn, Tpnp is not the limited N-type MOS (metal-oxide-semiconductor) transistor Q22 that is coupled to yet.As shown in figure 12, transistor group TN is directly coupled to P type MOS (metal-oxide-semiconductor) transistor Q21, and the drain electrode of transistor QN1 is coupled to direct voltage source VDD1, and the source electrode of transistor QNm is coupled to the source electrode of P type MOS (metal-oxide-semiconductor) transistor Q21.In the time that the transistor group TN shown in Figure 12 replaces with transistor group TP, Tnpn or Tpnp, its set-up mode is similar to the group of transistor shown in Fig. 8 TN, no longer adds to repeat herein.Moreover, as shown in figure 13, in CMOS CM, P type MOS (metal-oxide-semiconductor) transistor Q21 and N-type MOS (metal-oxide-semiconductor) transistor Q22 also can be coupled to transistor group TP and TN separately, and in other embodiments of the invention, the group TP of transistor shown in Figure 13 and TN can also other above-mentioned transistor group replace.Therefore other embodiment transistor group shown in Figure 12,13 being replaced with the transistor group shown in Fig. 8-11 and produce, must belong to category of the present invention.
Refer to Figure 14, it is the generalized schematic of the How It Works of the disclosed electric power starting/reset circuit in Fig. 4-13.As shown in figure 14, described method comprises that step is as follows:
Step 402: make the current potential height of the first analog signal change the current potential height variation of following the first direct voltage source.
Step 404: the current potential logic of reversion the first analog signal, to produce the second analog signal.
Step 406: the beginning condition that opens while adjusting reversion, to adjust the voltage transitions characteristic curve of the second analog signal.
Step 408: with the current potential logic of the second analog signal to produce unlatching/reset signal, and by the unlatching/Reset Status of unlatching/reset signal control figure circuit.
The foregoing is only the preferred embodiments of the present invention, all equalizations of doing according to the claims in the present invention change and modify, and all should belong to covering scope of the present invention.
Claims (20)
1. electric power starting/reset circuit, comprising:
One voltage follower module, is coupled to one first direct voltage source, and described voltage follower module produces one first analog signal, and the current potential of described the first analog signal height changes the current potential height variation of following described the first direct voltage source; And
One reverse amplification module, be used for receiving described the first analog signal and produce one second analog signal, described in the current potential logical AND of described the second analog signal, the current potential logic of the first analog signal is contrary, and described electric power starting/reset circuit is controlled the unlatching/Reset Status of a digital circuit according to described the second analog signal, the wherein said reverse amplification module utilization string transistorized mode that changes goes to adjust described the second analog signal, and described reverse amplification module comprises:
One first N-type MOS (metal-oxide-semiconductor) transistor, its grid is coupled to an output of described voltage follower module to receive described the first analog signal;
One the one P type MOS (metal-oxide-semiconductor) transistor, its grid is coupled to the grid of described the first N-type MOS (metal-oxide-semiconductor) transistor, the source electrode of a described P type MOS (metal-oxide-semiconductor) transistor is coupled to one second direct voltage source, and the drain electrode of a described P type MOS (metal-oxide-semiconductor) transistor is coupled to the drain electrode of described the first N-type MOS (metal-oxide-semiconductor) transistor and exports described the second analog signal; And
A first transistor at least one the first transistor is coupled to the source electrode of described the first N-type MOS (metal-oxide-semiconductor) transistor.
2. electric power starting/reset circuit as claimed in claim 1, is characterized in that:
The current potential of described the second direct voltage source is higher than the current potential of described the first direct voltage source.
3. electric power starting/reset circuit as claimed in claim 1, is characterized in that:
Described electric power starting/reset circuit separately comprises:
At least one is with the string transistor seconds that repeatedly mode is connected, and wherein a transistor seconds is coupled to described the second direct voltage source, and separately has a transistor seconds to be coupled to the source electrode of a described P type MOS (metal-oxide-semiconductor) transistor.
4. electric power starting/reset circuit as claimed in claim 3, is characterized in that:
Described at least one the first transistor is N-type MOS (metal-oxide-semiconductor) transistor, and described at least one transistor seconds is P type MOS (metal-oxide-semiconductor) transistor.
5. electric power starting/reset circuit as claimed in claim 3, is characterized in that:
Described at least one the first transistor is P type MOS (metal-oxide-semiconductor) transistor, and described at least one transistor seconds is N-type MOS (metal-oxide-semiconductor) transistor.
6. electric power starting/reset circuit as claimed in claim 3, is characterized in that:
Described at least one the first transistor is npn type bipolar junction transistor, and described at least one transistor seconds is pnp type bipolar junction transistor.
7. electric power starting/reset circuit as claimed in claim 3, is characterized in that:
Described at least one the first transistor is pnp type bipolar junction transistor, and described at least one transistor seconds is npn type bipolar junction transistor.
8. electric power starting/reset circuit as claimed in claim 1, is characterized in that:
Described voltage follower module comprises:
One the one P type MOS (metal-oxide-semiconductor) transistor, its source electrode is coupled to described the first direct voltage source;
One the 2nd P type MOS (metal-oxide-semiconductor) transistor, its source electrode is coupled to drain electrode and the grid of a described P type MOS (metal-oxide-semiconductor) transistor, and the base stage of described the 2nd P type MOS (metal-oxide-semiconductor) transistor is coupled to the base stage of a described P type MOS (metal-oxide-semiconductor) transistor;
One the 3rd P type MOS (metal-oxide-semiconductor) transistor, its source electrode is coupled to the source electrode of a described P type MOS (metal-oxide-semiconductor) transistor, the grid of described the 3rd P type MOS (metal-oxide-semiconductor) transistor is coupled to the grid of a described P type MOS (metal-oxide-semiconductor) transistor, and the drain electrode of described the 3rd P type MOS (metal-oxide-semiconductor) transistor is coupled to the grid of described the 2nd P type MOS (metal-oxide-semiconductor) transistor;
One first N-type MOS (metal-oxide-semiconductor) transistor, its drain electrode is coupled to the drain electrode of described the 3rd P type MOS (metal-oxide-semiconductor) transistor and the grid of described the 2nd P type MOS (metal-oxide-semiconductor) transistor;
One second N-type MOS (metal-oxide-semiconductor) transistor, its drain electrode is coupled to the source electrode of described the first N-type MOS (metal-oxide-semiconductor) transistor and the grid of described the second N-type MOS (metal-oxide-semiconductor) transistor, and the source ground of described the second N-type MOS (metal-oxide-semiconductor) transistor;
One the 3rd N-type MOS (metal-oxide-semiconductor) transistor, its source ground, the grid of described the 3rd N-type MOS (metal-oxide-semiconductor) transistor is coupled to the grid of described the second N-type MOS (metal-oxide-semiconductor) transistor, and the drain electrode of described the 3rd N-type MOS (metal-oxide-semiconductor) transistor is coupled to the grid of described the first N-type MOS (metal-oxide-semiconductor) transistor;
One the 4th P type MOS (metal-oxide-semiconductor) transistor, its drain electrode is coupled to the drain electrode of described the 3rd N-type MOS (metal-oxide-semiconductor) transistor, and the grid of described the 4th P type MOS (metal-oxide-semiconductor) transistor is coupled to the grid of described the second N-type MOS (metal-oxide-semiconductor) transistor; And
One the 5th P type MOS (metal-oxide-semiconductor) transistor, its drain electrode is coupled to the source electrode of described the 4th P type MOS (metal-oxide-semiconductor) transistor, the grid of described the 5th P type MOS (metal-oxide-semiconductor) transistor is coupled to the grid of described the 4th P type MOS (metal-oxide-semiconductor) transistor, and the source electrode of described the 5th P type MOS (metal-oxide-semiconductor) transistor is coupled to the source electrode of a described P type MOS (metal-oxide-semiconductor) transistor.
9. electric power starting/reset circuit as claimed in claim 1, is characterized in that:
Described electric power starting/reset circuit separately comprises:
One electric current supply device, is coupled to described the first direct voltage source, and is used for producing an electric current; And
One inverted logic module, be coupled to described reverse amplification module to receive described the second analog signal, and be coupled to described electric current supply device to be driven by described electric current, the intensity that described electric current supply device is also used for controlling described electric current is below a critical current intensity, and described inverted logic module is reversed the current potential logic of described the second analog signal to produce one unlatching/reset signal, makes described electric power starting/reset circuit control the unlatching/Reset Status of described digital circuit by described unlatching/reset signal.
10. electric power starting/reset circuit as claimed in claim 9, is characterized in that:
Described electric current supply device comprises:
One second N-type MOS (metal-oxide-semiconductor) transistor, its drain electrode is coupled to the grid of described the first direct voltage source and described the second N-type MOS (metal-oxide-semiconductor) transistor;
One the 3rd N-type MOS (metal-oxide-semiconductor) transistor, its grid is coupled to the grid of described the second N-type MOS (metal-oxide-semiconductor) transistor;
One the 4th N-type MOS (metal-oxide-semiconductor) transistor, its grid is coupled to the grid of described the 3rd N-type MOS (metal-oxide-semiconductor) transistor;
One the 5th P type MOS (metal-oxide-semiconductor) transistor, its grid and drain electrode are coupled to the drain electrode of described the 3rd N-type MOS (metal-oxide-semiconductor) transistor, and the source electrode of described the 5th P type MOS (metal-oxide-semiconductor) transistor is coupled to described the first direct voltage source; And
One the 6th P type MOS (metal-oxide-semiconductor) transistor, its grid is coupled to the grid of described the 5th P type MOS (metal-oxide-semiconductor) transistor, and the source electrode of described the 6th P type MOS (metal-oxide-semiconductor) transistor is coupled to described the first direct voltage source;
Described inverted logic module comprises:
One the 7th P type MOS (metal-oxide-semiconductor) transistor, its grid is coupled to described reverse amplification module, and the source electrode of described the 7th P type MOS (metal-oxide-semiconductor) transistor is coupled to the drain electrode of described the 6th P type MOS (metal-oxide-semiconductor) transistor; And
One the 5th N-type MOS (metal-oxide-semiconductor) transistor, its grid is coupled to the grid of described the 7th P type MOS (metal-oxide-semiconductor) transistor, the drain electrode of described the 5th N-type MOS (metal-oxide-semiconductor) transistor is coupled to the drain electrode of described the 7th P type MOS (metal-oxide-semiconductor) transistor, and the source electrode of described the 5th N-type MOS (metal-oxide-semiconductor) transistor is coupled to the drain electrode of described the 4th N-type MOS (metal-oxide-semiconductor) transistor; And
The base stage of described the 7th P type MOS (metal-oxide-semiconductor) transistor is coupled to described the first direct voltage source, and the base stage of described the 5th N-type MOS (metal-oxide-semiconductor) transistor is coupled to the base stage of described the 4th N-type MOS (metal-oxide-semiconductor) transistor.
11. 1 kinds of electric power starting/reset circuits, comprising:
One voltage follower module, is coupled to one first direct voltage source, and described voltage follower module produces one first analog signal, and the current potential of described the first analog signal height changes the current potential height variation of following described the first direct voltage source; And
One reverse amplification module, be used for receiving described the first analog signal and produce one second analog signal, described in the current potential logical AND of described the second analog signal, the current potential logic of the first analog signal is contrary, and described electric power starting/reset circuit is controlled the unlatching/Reset Status of a digital circuit according to described the second analog signal, the wherein said reverse amplification module utilization string transistorized mode that changes goes to adjust described the second analog signal, and described reverse amplification module comprises:
One first N-type MOS (metal-oxide-semiconductor) transistor, its grid is coupled to an output of described voltage follower module to receive described the first analog signal;
One the one P type MOS (metal-oxide-semiconductor) transistor, its grid is coupled to the grid of described the first N-type MOS (metal-oxide-semiconductor) transistor, the source electrode of a described P type MOS (metal-oxide-semiconductor) transistor is coupled to one second direct voltage source, and the drain electrode of a described P type MOS (metal-oxide-semiconductor) transistor is coupled to the drain electrode of described the first N-type MOS (metal-oxide-semiconductor) transistor and exports described the second analog signal; And
A first transistor at least one the first transistor is coupled to the source electrode of a described P type MOS (metal-oxide-semiconductor) transistor.
12. electric power starting/reset circuits as claimed in claim 11, is characterized in that:
The current potential of described the second direct voltage source is higher than the current potential of described the first direct voltage source.
13. electric power starting/reset circuits as claimed in claim 11, is characterized in that:
Described electric power starting/reset circuit separately comprises:
At least one is with the string transistor seconds that repeatedly mode is connected, and wherein a transistor seconds is coupled to the source electrode of described the first N-type MOS (metal-oxide-semiconductor) transistor.
14. electric power starting/reset circuits as claimed in claim 13, is characterized in that:
Described at least one the first transistor is N-type MOS (metal-oxide-semiconductor) transistor, and described at least one transistor seconds is P type MOS (metal-oxide-semiconductor) transistor.
15. electric power starting/reset circuits as claimed in claim 13, is characterized in that:
Described at least one the first transistor is P type MOS (metal-oxide-semiconductor) transistor, and described at least one transistor seconds is N-type MOS (metal-oxide-semiconductor) transistor.
16. electric power starting/reset circuits as claimed in claim 13, is characterized in that:
Described at least one the first transistor is npn type bipolar junction transistor, and described at least one transistor seconds is pnp type bipolar junction transistor.
17. electric power starting/reset circuits as claimed in claim 13, is characterized in that:
Described at least one the first transistor is pnp type bipolar junction transistor, and described at least one transistor seconds is npn type bipolar junction transistor.
18. electric power starting/reset circuits as claimed in claim 11, is characterized in that:
Described voltage follower module comprises:
One the one P type MOS (metal-oxide-semiconductor) transistor, its source electrode is coupled to described the first direct voltage source;
One the 2nd P type MOS (metal-oxide-semiconductor) transistor, its source electrode is coupled to drain electrode and the grid of a described P type MOS (metal-oxide-semiconductor) transistor, and the base stage of described the 2nd P type MOS (metal-oxide-semiconductor) transistor is coupled to the base stage of a described P type MOS (metal-oxide-semiconductor) transistor;
One the 3rd P type MOS (metal-oxide-semiconductor) transistor, its source electrode is coupled to the source electrode of a described P type MOS (metal-oxide-semiconductor) transistor, the grid of described the 3rd P type MOS (metal-oxide-semiconductor) transistor is coupled to the grid of a described P type MOS (metal-oxide-semiconductor) transistor, and the drain electrode of described the 3rd P type MOS (metal-oxide-semiconductor) transistor is coupled to the grid of described the 2nd P type MOS (metal-oxide-semiconductor) transistor;
One first N-type MOS (metal-oxide-semiconductor) transistor, its drain electrode is coupled to the drain electrode of described the 3rd P type MOS (metal-oxide-semiconductor) transistor and the grid of described the 2nd P type MOS (metal-oxide-semiconductor) transistor;
One second N-type MOS (metal-oxide-semiconductor) transistor, its drain electrode is coupled to the source electrode of described the first N-type MOS (metal-oxide-semiconductor) transistor and the grid of described the second N-type MOS (metal-oxide-semiconductor) transistor, and the source ground of described the second N-type MOS (metal-oxide-semiconductor) transistor;
One the 3rd N-type MOS (metal-oxide-semiconductor) transistor, its source ground, the grid of described the 3rd N-type MOS (metal-oxide-semiconductor) transistor is coupled to the grid of described the second N-type MOS (metal-oxide-semiconductor) transistor, and the drain electrode of described the 3rd N-type MOS (metal-oxide-semiconductor) transistor is coupled to the grid of described the first N-type MOS (metal-oxide-semiconductor) transistor;
One the 4th P type MOS (metal-oxide-semiconductor) transistor, its drain electrode is coupled to the drain electrode of described the 3rd N-type MOS (metal-oxide-semiconductor) transistor, and the grid of described the 4th P type MOS (metal-oxide-semiconductor) transistor is coupled to the grid of described the second N-type MOS (metal-oxide-semiconductor) transistor; And
One the 5th P type MOS (metal-oxide-semiconductor) transistor, its drain electrode is coupled to the source electrode of described the 4th P type MOS (metal-oxide-semiconductor) transistor, the grid of described the 5th P type MOS (metal-oxide-semiconductor) transistor is coupled to the grid of described the 4th P type MOS (metal-oxide-semiconductor) transistor, and the source electrode of described the 5th P type MOS (metal-oxide-semiconductor) transistor is coupled to the source electrode of a described P type MOS (metal-oxide-semiconductor) transistor.
19. electric power starting/reset circuits as claimed in claim 11, is characterized in that:
Described electric power starting/reset circuit separately comprises:
One electric current supply device, is coupled to described the first direct voltage source, and is used for producing an electric current; And
One inverted logic module, be coupled to described reverse amplification module to receive described the second analog signal, and be coupled to described electric current supply device to be driven by described electric current, the intensity that described electric current supply device is also used for controlling described electric current is below a critical current intensity, and described inverted logic module is reversed the current potential logic of described the second analog signal to produce one unlatching/reset signal, makes described electric power starting/reset circuit control the unlatching/Reset Status of described digital circuit by described unlatching/reset signal.
20. electric power starting/reset circuits as claimed in claim 19, is characterized in that:
Described electric current supply device comprises:
One second N-type MOS (metal-oxide-semiconductor) transistor, its drain electrode is coupled to the grid of described the first direct voltage source and described the second N-type MOS (metal-oxide-semiconductor) transistor;
One the 3rd N-type MOS (metal-oxide-semiconductor) transistor, its grid is coupled to the grid of described the second N-type MOS (metal-oxide-semiconductor) transistor;
One the 4th N-type MOS (metal-oxide-semiconductor) transistor, its grid is coupled to the grid of described the 3rd N-type MOS (metal-oxide-semiconductor) transistor;
One the 5th P type MOS (metal-oxide-semiconductor) transistor, its grid and drain electrode are coupled to the drain electrode of described the 3rd N-type MOS (metal-oxide-semiconductor) transistor, and the source electrode of described the 5th P type MOS (metal-oxide-semiconductor) transistor is coupled to described the first direct voltage source; And
One the 6th P type MOS (metal-oxide-semiconductor) transistor, its grid is coupled to the grid of described the 5th P type MOS (metal-oxide-semiconductor) transistor, and the source electrode of described the 6th P type MOS (metal-oxide-semiconductor) transistor is coupled to described the first direct voltage source;
Described inverted logic module comprises:
One the 7th P type MOS (metal-oxide-semiconductor) transistor, its grid is coupled to described reverse amplification module, and the source electrode of described the 7th P type MOS (metal-oxide-semiconductor) transistor is coupled to the drain electrode of described the 6th P type MOS (metal-oxide-semiconductor) transistor; And
One the 5th N-type MOS (metal-oxide-semiconductor) transistor, its grid is coupled to the grid of described the 7th P type MOS (metal-oxide-semiconductor) transistor, the drain electrode of described the 5th N-type MOS (metal-oxide-semiconductor) transistor is coupled to the drain electrode of described the 7th P type MOS (metal-oxide-semiconductor) transistor, and the source electrode of described the 5th N-type MOS (metal-oxide-semiconductor) transistor is coupled to the drain electrode of described the 4th N-type MOS (metal-oxide-semiconductor) transistor; And
The base stage of described the 7th P type MOS (metal-oxide-semiconductor) transistor is coupled to described the first direct voltage source, and the base stage of described the 5th N-type MOS (metal-oxide-semiconductor) transistor is coupled to the base stage of described the 4th N-type MOS (metal-oxide-semiconductor) transistor.
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| US20020109535A1 (en) * | 2001-02-09 | 2002-08-15 | Telcom Semiconductor, Inc. | Power on reset circuit arrangement |
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| US5883532A (en) * | 1997-03-25 | 1999-03-16 | Analog Devices, Inc. | Power-on reset circuit based upon FET threshold level |
| US6744291B2 (en) * | 2002-08-30 | 2004-06-01 | Atmel Corporation | Power-on reset circuit |
| CN1642006A (en) * | 2004-09-14 | 2005-07-20 | 威盛电子股份有限公司 | Power-supply turn-on resetting circuit |
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| CN102570784A (en) | 2012-07-11 |
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