CN102569209B - Anti-cracking structure - Google Patents
Anti-cracking structure Download PDFInfo
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- CN102569209B CN102569209B CN201010610019.XA CN201010610019A CN102569209B CN 102569209 B CN102569209 B CN 102569209B CN 201010610019 A CN201010610019 A CN 201010610019A CN 102569209 B CN102569209 B CN 102569209B
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Abstract
The invention provides an anti-cracking structure, which is positioned on a semiconductor substrate in a wafer cutting channel. A wafer is spaced into a plurality of chips along the cutting channel; the anti-cracking structure has two parallel arranged lines along a direction of edges of the chips; each line consists of metal lines and connection hole lines, which are staggered with one another in a longitudinal direction; and each pair of metal line and connection hole line, which are arranged on the cutting channel alternatively corresponds to each layer of chips. By adopting the anti-cracking structure, the problems of uneven ground material layers of the chips and easy damage to the chips during cutting are solved.
Description
Technical field
The present invention relates to semiconductor device processing technology, particularly a kind of anti-cracking structure.
Background technology
At present, along with the develop rapidly of semiconductor fabrication, semiconductor device is in order to reach arithmetic speed, larger memory data output and more function faster, and wafer is towards higher component density, high integration future development, and on wafer, the quantity of chip increases gradually.
In manufacture of semiconductor, normally wafer is cut into chip one by one, then these chips are made the different semiconductor package of function.Fig. 1 is the vertical view of wafer.Wafer is made up of multiple chip 101, is then separated by with Cutting Road (scribe line) 102 between chip 101.Each chip 101 passes through the techniques such as deposition, micro-shadow, etching, doping and heat treatment, forming element, lamination, interconnection line and weld pad etc. on a semiconductor substrate; Cutting Road 102 is divided into chip one by one herein for prolonging, so there is not function element.
By the sawing along Cutting Road, wafer is cut into single chip, according to prior art, need the cleaning carrying out cutting blade after having been cut by whole wafer again, along with the increase of number of chips on wafer, a wafer is not cut toward contact, cutting blade has just sticked a lot of metal fragment, caused cutting blade to use.These metal fragments are generally the conduction redundancy structures be on Cutting Road, be made up of metallic copper, for increasing the pattern density of Cutting Road blank region, make the pattern density on Cutting Road and the pattern density on chip symmetrical, when preventing each material layer on grinding chip, occur grinding uneven problem.
It should be noted that, a kind of existing method solving cutting blade and just cannot use in the cutting also not completing a wafer, be exactly that the conduction redundancy structure on Cutting Road is removed, when such cutting blade is along Cutting Road sawing, insulating barrier completely on cutting Cutting Road, but, now just there will be even more serious problem: on the one hand, owing to there is not conduction redundancy structure in Cutting Road, Cutting Road region is different compared to chip area height, so during each material layer on grinding chip, the uneven problem of grinding described before occurring again; On the other hand; only there is insulating barrier in Cutting Road; so when cutting; the stress that cutting blade produces makes insulating barrier splitting quickly; be easy to extend to chip area, chip area is destroyed, even if chip edge is provided with sealing ring (seal ring); also probably the sealing ring for the protection of chip is washed away, and then be corrupted to chip.
Summary of the invention
In view of this, the technical problem that the present invention solves is: overcome the problem that the uneven and chip of each material layer on grinding chip is easily destroyed when cutting simultaneously.
For solving the problems of the technologies described above, technical scheme of the present invention is specifically achieved in that
The invention provides a kind of anti-cracking structure, be positioned in the Semiconductor substrate of wafer cutting path, along described Cutting Road, wafer is partitioned into multiple chip, this structure is two lines arranged in parallel along chip length of side direction, every bar line is made up of the metal wire arranged alternatively up and down and connecting hole line, every a pair metal wire be wherein alternately arranged on Cutting Road and connecting hole line and the corresponding setting of each layer on chip.
Described connecting hole line is the many rows being positioned at a row under same metal wire or parallel arranged.
Each layer on described chip to lower and on comprise multiple metal interconnecting layer and aluminum cushion layer successively, wherein each metal interconnecting layer comprises the groove and connecting hole that are filled with metal, and aluminum cushion layer comprises the groove and connecting hole that are filled with metallic aluminium.
Spacing between described two lines arranged in parallel is greater than 40 microns.
The width of described every bar line is 2 ~ 10 microns.
As seen from the above technical solutions, anti-cracking structure of the present invention, be two lines arranged in parallel along chip length of side direction, and be spaced a distance between these two lines, blade can carry out the cutting of chip just when not contacting anti-cracking structure, be attached on blade so do not have metal fragment; And arranged in parallel two lines have certain pattern density, when overcoming each material layer on grinding chip, occur grinding uneven problem; Anti-cracking structure, to lower and upper to be alternately arranged by metal wire and connecting hole line is arranged at the surrounding of chip, can not be damaged when cutting by protect IC well.
Accompanying drawing explanation
Fig. 1 is the vertical view of wafer.
Fig. 2 is the wafer schematic diagram being provided with anti-cracking structure of the present invention.
Fig. 3 is the profile of embodiment of the present invention anti-cracking structure.
Fig. 4 is the profile of preferred embodiment of the present invention anti-cracking structure.
Embodiment
For making object of the present invention, technical scheme and advantage clearly understand, to develop simultaneously embodiment referring to accompanying drawing, the present invention is described in more detail.
The present invention utilizes schematic diagram to be described in detail, when describing the embodiment of the present invention in detail, for convenience of explanation, represent that the schematic diagram of structure can be disobeyed general ratio and be made partial enlargement, should in this, as limitation of the invention, in addition, in the making of reality, the three-dimensional space of length, width and the degree of depth should be comprised.
The present invention arranges anti-cracking structure (crack stop structure) in Cutting Road, and this structure is two lines arranged in parallel along chip 101 length of side direction, as shown in Figure 2.Fig. 2 is the wafer schematic diagram being provided with anti-cracking structure of the present invention.The width of Cutting Road 102 is generally at 50 ~ 80 microns, and the spacing between two lines 200 that the present invention is arranged in parallel is greater than 40 microns, and the width of every bar line is 2 ~ 10 microns.According to common practise, the cutter seam width of cutting blade is approximately 20 microns, spacing between two lines of therefore anti-cracking structure of the present invention is greater than 40 microns, so that the cutting of cutting blade, can not as the conduction redundancy structure be in prior art on Cutting Road, the cutting through cutting blade is attached on blade; And arranged in parallel two lines have certain pattern density, when overcoming each material layer on grinding chip, occur grinding uneven problem.
Fig. 3 is the profile of embodiment of the present invention anti-cracking structure.According to prior art, chip comprises sandwich construction, to lower and on include source region (AA), multiple metal interconnecting layer and aluminium pad (Al pad) layer successively.Wherein each metal interconnecting layer is made up of the connecting hole and groove being filled with metal such as metallic copper.The aluminum cushion layer of top layer is made up of the connecting hole and groove being filled with metallic aluminium, and just the size of groove is larger compared with metal interconnecting layer, for connecting chip exterior circuit.The present invention is positioned at the anti-cracking structure of Cutting Road and chip is formed simultaneously, every bar line of anti-cracking structure, be positioned in the Semiconductor substrate of Cutting Road, be made up of the metal wire arranged alternatively up and down and connecting hole line, every a pair metal wire be wherein alternately arranged on Cutting Road and connecting hole line and the corresponding setting of each layer on chip, each layer on chip refer to lower and on multiple metal interconnecting layer of comprising successively and aluminum cushion layer.Metal wire and the connecting hole line of aluminium filling is comprised in the Cutting Road corresponding to aluminum cushion layer; Metal filled metal wire and connecting hole line is comprised in the Cutting Road corresponding to metal interconnecting layer, particularly, the first metal wire and the first connecting hole line is comprised in the Cutting Road corresponding to the first metal interconnecting layer, the second metal wire and the second connecting hole line is comprised in the Cutting Road corresponding to the second metal interconnecting layer, the like, comprise top wire and top layer connecting hole line in the Cutting Road corresponding to top-level metallic interconnection layer.The metal wire arranging connection alternatively up and down and connecting hole line are established in the insulating barrier in Cutting Road as a stifled solid wall; and according to Fig. 2; anti-cracking structure is arranged at chip surrounding; when diced chip; even if the stress that cutting blade produces makes insulating barrier splitting quickly; splitting also can be prevented from anti-cracking structure place, is unlikely to extend to chip area, and that is anti-cracking structure of the present invention can not be damaged when cutting in protect IC region well.
It should be noted that, for how to form anti-cracking structure, be identical with the method for the multiple metal interconnecting layer of formation and aluminum cushion layer.For example, when forming the first metal interconnecting layer, etch the first groove and the first connecting hole first in a insulating layer, then in the first groove and the first connecting hole, fill metal, and grind, the metal after grinding flushes with insulating barrier.In like manner, when forming the first metal wire and the first connecting hole line of anti-cracking structure, first in the insulating barrier of Cutting Road, etch the first metallic channel be connected hole slot with first, then be connected in hole slot at the first metallic channel and first and fill metal, and grind, metal after grinding flushes with insulating barrier, thus forms the first metal wire and the first connecting hole line.Wherein, connecting hole line width is substantially negligible, so the width of the metal wire of the present invention's restriction is 2 ~ 10 microns.
For protect IC is not damaged when cutting better; namely prevent splitting from extending to chip area; preferably connecting hole line corresponding under each metal wire is set to many rows of parallel arranged; as shown in Figure 4; Fig. 4 is the profile of preferred embodiment of the present invention anti-cracking structure, and the connecting hole line be positioned in figure under same metal wire is two rows.Many rows connecting hole line can stop the extension of splitting better compared with single connecting hole line.
To sum up, anti-cracking structure of the present invention, is two lines arranged in parallel along chip length of side direction, and is spaced a distance between these two lines, blade can carry out the cutting of chip just when not contacting anti-cracking structure, be attached on blade so do not have metal fragment; And arranged in parallel two lines have certain pattern density, when overcoming each material layer on grinding chip, occur grinding uneven problem; Anti-cracking structure, to lower and upper to be alternately arranged by metal wire and connecting hole line is arranged at the surrounding of chip, can not be damaged when cutting by protect IC well.
The foregoing is only preferred embodiment of the present invention, not in order to limit the present invention, within the spirit and principles in the present invention all, any amendment made, equivalent replacement, improvement etc., all should be included within the scope of protection of the invention.
Claims (5)
1. an anti-cracking structure, be positioned in the Semiconductor substrate of wafer cutting path, along described Cutting Road, wafer is partitioned into multiple chip, it is characterized in that, this structure is two lines arranged in parallel along chip length of side direction, and two lines run through whole wafer continuously, every bar line is made up of the metal wire arranged alternatively up and down and connecting hole line, every a pair metal wire be wherein alternately arranged on Cutting Road and connecting hole line and the corresponding setting of each layer on chip.
2. structure as claimed in claim 1, is characterized in that, described connecting hole line is the many rows being positioned at a row under same metal wire or parallel arranged.
3. structure as claimed in claim 2, it is characterized in that, each layer on described chip to lower and on comprise multiple metal interconnecting layer and aluminum cushion layer successively, wherein each metal interconnecting layer comprises the groove and connecting hole that are filled with metal, and aluminum cushion layer comprises the groove and connecting hole that are filled with metallic aluminium.
4. structure as claimed in claim 1, it is characterized in that, the spacing between described two lines arranged in parallel is greater than 40 microns.
5. structure as claimed in claim 2, it is characterized in that, the width of described every bar line is 2 ~ 10 microns.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010610019.XA CN102569209B (en) | 2010-12-28 | 2010-12-28 | Anti-cracking structure |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010610019.XA CN102569209B (en) | 2010-12-28 | 2010-12-28 | Anti-cracking structure |
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| CN102569209A CN102569209A (en) | 2012-07-11 |
| CN102569209B true CN102569209B (en) | 2015-01-28 |
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Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104752325B (en) * | 2013-12-30 | 2017-12-29 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor devices and forming method thereof, the method for improving wafer cutting yield rate |
| CN105514150A (en) * | 2016-01-22 | 2016-04-20 | 英麦科（厦门）微电子科技有限公司 | Anti-cracking wafer structure and scribing method |
| US11026325B2 (en) | 2017-05-25 | 2021-06-01 | Orpyx Medical Technologies Inc. | Flexible circuit package |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101640190A (en) * | 2008-07-29 | 2010-02-03 | 台湾积体电路制造股份有限公司 | Structure for reducing integrated circuit corner peeling |
| CN101685817A (en) * | 2008-09-22 | 2010-03-31 | 恩益禧电子股份有限公司 | Semiconductor chip and semiconductor wafer |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7741715B2 (en) * | 2005-03-14 | 2010-06-22 | Infineon Technologies Ag | Crack stop and moisture barrier |
| US7732897B2 (en) * | 2006-06-15 | 2010-06-08 | Taiwan Semiconductor Manufacturing Co., Ltd | Methods of die sawing and structures formed thereby |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101640190A (en) * | 2008-07-29 | 2010-02-03 | 台湾积体电路制造股份有限公司 | Structure for reducing integrated circuit corner peeling |
| CN101685817A (en) * | 2008-09-22 | 2010-03-31 | 恩益禧电子股份有限公司 | Semiconductor chip and semiconductor wafer |
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| CN102569209A (en) | 2012-07-11 |
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Effective date of registration: 20121116 Address after: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Applicant after: Semiconductor Manufacturing International (Shanghai) Corporation Applicant after: Semiconductor Manufacturing International (Beijing) Corporation Address before: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Applicant before: Semiconductor Manufacturing International (Shanghai) Corporation |
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