CN102565680B - The failure analysis method of semiconductor device - Google Patents
The failure analysis method of semiconductor device Download PDFInfo
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- CN102565680B CN102565680B CN201010605339.6A CN201010605339A CN102565680B CN 102565680 B CN102565680 B CN 102565680B CN 201010605339 A CN201010605339 A CN 201010605339A CN 102565680 B CN102565680 B CN 102565680B
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Abstract
The present invention is about the failure analysis method of a kind of semiconductor device, and it includes step: remove the layers of copper at the semiconductor device back side；The silicon layer at the semiconductor device back side is carried out thinning；And use the failpoint at low-light microscope (Emission Microscope, EMMI) and/or radium-shine optical beam induced change in impedance value test (OBIRCH) the electrically semiconductor device back side, location equipment location.The failure analysis method of semiconductor device of the present invention, by copper removal, silicon layer are thinning and failpoint positions by carrying out the back side of semiconductor device, have been saved the time, has been improve efficiency and success rate.
Description
Technical field
The present invention relates to semiconductor test technical field, particularly relate to the failure analysis side of a kind of semiconductor device
Method.
Background technology
Large-scale production for semiconductor device, it is desired to be able to profitable reliable process technology is provided.
Include designing semiconductor device for improving the process of the reliability and stability of Technology, manufacture quasiconductor
The sample of device and the step of the described sample of test.The failure analysis of semiconductor device is feedback procedure, design
Find that the root with correcting defect is to overcome the problem produced by defect.
Suitable failure analysis is crucial for improving the quality of semiconductor device.Incorrect failure analysis
Exploitation may be lengthened and promote the cycle needed for semiconductor device product.Usually, failure analysis includes outside
Inspection, non-destructive analysis, electrical property detection, destructive analysis etc..
Along with the raising of semiconductor device integrated level, the component structure forming semiconductor device becomes three-dimensional answering
Miscellaneous structure, in order to obtain sufficiently large capacity in the region limited.The increase of complexity of semiconductor devices,
Make can not accurately analyze the root of inefficacy only by methods such as visual examination or electrical property detections, this
Just require to use senior delamination treatment technology open semiconductor package part and remove the coating on wafer to be measured, example
Such as silicon layer, oxide layer, to expose the failure conditions of the laminated construction of semiconductor device.
But, semiconductor device surface is covered the failure analysis (such as DMOS) of bulk aluminum, also had
When a little semiconductor device surfaces are carried out failure analysis by BANG line and stannum ball when covering, lost efficacy and divided
Analysis (Failure Analysis, FA) lab analysis is got up the most difficult.Reason is mainly: existing
Low-light microscope (Emission Microscope, EMMI) can not to this type of sample defects positioning analysis,
Because photon can not pass through aluminum.If after using fuming nitric aicd method that semiconductor device is broken a seal, easily caused
Parameter drift is fallen, because the metal material of copper at the semiconductor device back side (Cu) thickness is very big, directly polishing is difficult to
Accomplish the removal of layers of copper.
Therefore, prior art generally has two kinds of ways:
One, for the semiconductor device of non-plastic packing forms, its back side encapsulation copper (Cu) material is the thinnest,
Full-automatic sample can be utilized to prepare (Automated Sample Prep, ASAP) equipment epoxy resin
Target drill is directly skimmed from the back side of semiconductor device epoxy resin, then changes mill Cu target drill,
Throw to Si (silicon) layer, thinning to this silicon layer the most again.
But, this technical scheme is not suitable for the semiconductor device of the Plastic Package form of back metal material
Polished backside, because the back side Cu layer of this kind of semiconductor device is the thickest, is directly difficult to successfully with drill bit polishing,
And drill bit loss ratio is more serious, the time of polishing is the longest.
Two, for the semiconductor device of Plastic Package form of back metal material, it is possible to use fuming nitric aicd
To its encapsulation Kaifeng, by tube core bonding (bonding) on PCCB plate, seal semiconductor device with black glue
The front of part, then according to the step in solution one progressively grinds Cu layer and silicon layer is thinning.
But this solution exists following not enough: 1) to high-voltage product, such as 600V DMOS, chip with
Acid solution is long for time of contact, directly boil easily cause semiconductor device parameter drift fall, it is impossible to semiconductor device
It is further analyzed, so that this solution lost efficacy；2) even if low voltage product uses this solution,
In its bonding (bonding) and encapsulation process, need to use PCCB plate, bonding machines and black glue etc., become
This height, and spend the time long, inefficiency.
Therefore, it is necessary to this technical problem is solved.
Summary of the invention
It is an object of the invention to provide the failure analysis method of a kind of semiconductor device, it realizes simple, effect
Rate is high.
For achieving the above object, the present invention is the failure analysis method about a kind of semiconductor device, and it includes
Step:
S101: remove the layers of copper at the semiconductor device back side；
S103: the silicon layer at the semiconductor device back side is carried out thinning；And
S105: use low-light microscope (Emission Microscope, EMMI) and/or radium-shine light beam to lure
Send out the failpoint at change in impedance value test (OBIRCH) the electrically semiconductor device back side, location equipment location.
As a further improvement on the present invention, described step S101 use the salpeter solution of 70% soak half
The back side of conductor device is to remove layers of copper.
As a further improvement on the present invention, the semiconductor device back of the body after layers of copper is removed in described step S101
Face forms U-shaped window.
As a further improvement on the present invention, described step S103 use full-automatic sample prepare
Silicon layer is carried out thinning by (Automated Sample Prep) equipment.
As a further improvement on the present invention, described step S101 is removed the semiconductor device back of the body after layers of copper
Face forms U-shaped window, and wherein silicon layer is ground thinning in this window by full-automatic sample preparation device.
As a further improvement on the present invention, described step S103 use three kinds of different drill bits to silicon layer
It is ground thinning.
The most described OBIRCH electrically position equipment have drain end probe,
Gate end probe and source end probe, semiconductor device include having front and the main part at the described back side and
Pin, wherein drain end probe directly contacts the back side of main part, gate end probe and source end probe
Connect the pin of semiconductor device.
As a further improvement on the present invention, the back side of described semiconductor device have successively layers of copper, silicon layer and
Chip-stack, wherein said drain end probe contact chip lamination.
The invention has the beneficial effects as follows: by the back side of semiconductor device carries out copper removal, silicon layer is thinning and loses
Effect point location, has saved the time, has improve efficiency and success rate.
Accompanying drawing explanation
Fig. 1 be semiconductor device of the present invention failure analysis method in semiconductor device immersed 70% nitric acid liquid
The schematic diagram of middle removing the cu layer；
Fig. 2 is the schematic diagram after semiconductor device removing the cu layer of the present invention；
Fig. 3 be semiconductor device of the present invention failure analysis method in use full-automatic sample to prepare (ASAP)
Equipment carries out thinning schematic diagram to the silicon layer of semiconductor device；
Fig. 4 be the silicon layer to semiconductor device of the present invention success the most thinning after schematic diagram；
Fig. 5 is that semiconductor device of the present invention uses (the radium-shine optical beam induced change in impedance value survey of electrical location equipment
Examination, OBIRCH) orient the schematic diagram of failpoint；
Fig. 6 is the zoomed-in view of semiconductor device failure of the present invention point.
Detailed description of the invention
Referring to Fig. 1 and Fig. 2, semiconductor device 100 of the present invention has main part 101 and main body 101
Side extends three pins 106 formed.Described main part 101 has front (non-label) and relative
The back side 102.The back side 102 has layers of copper, silicon layer 104 and chip-stack 108 successively.Quasiconductor of the present invention
The failure analysis method of device 100 comprises the following steps:
S101: remove the layers of copper at semiconductor device 100 back side 102.
The present invention uses the nitric acid liquid 200 of 70%, by semiconductor device 100 main part 101 back side 102
Layers of copper erodes.In order to avoid pin 106 is by the corrosion of nitric acid liquid 200, need three pins 106
Protect.For reducing cost, this step use the way controlling nitric acid liquid 200 liquid level protect survey
Test tube foot 106 is not corroded.
The present invention is to utilize nitric acid liquid 200 and layers of copper to react comparatively fast, the most anti-with capsulation material (epoxy resin)
The principle answered realizes.Its reaction equation is: Cu+4HNO30--＞ Cu2.Fig. 2 i.e. shows and successfully removes
The schematic diagram of the semiconductor device 100 after this layers of copper, removes the main part 101 after layers of copper and offers U-shaped window
Mouth 103.
S103: the silicon layer 104 at semiconductor device 100 back side 102 is carried out thinning.
It is right that the present invention uses full-automatic sample to prepare (Automated Sample Prep, ASAP) equipment 300
Silicon layer 104 carries out thinning.ASAP equipment 300 can select region to be ground, and so can utilize this
Equipment is ground on the silicon layer 104 at the back side 102 of the semiconductor device 100 having outputed window 103.
The ASAP equipment 300 of the present invention uses three kinds of different drill bits to carry out thinning to silicon layer, after using successively
It is formed for the photo of the semiconductor device 100 after the thinning silicon layer 104 shown in Fig. 4.
S105: with low-light microscope (Emission Microscope, EMMI) and radium-shine optical beam induced impedance
The failpoint at value change test (OBIRCH) electrically semiconductor device 100 back side 102, location equipment location.
The present invention utilizes and electrically positions equipment OBIRCH 400 to orient failpoint 109.This is electrically fixed
Position equipment 400 has directly pricks what the chip-stack 108 at semiconductor device 100 back side 102 connected
Gate end probe that Drain end probe and directly rolling tube foot 106 connect and source end probe.In Fig. 5
Showing and orient failpoint 109 after utilizing this electrical location equipment 400, Fig. 6 is this failpoint 109
The zoomed-in view divided.
The method that in figure it can be seen that the back side is analyzed can be accurately positioned out failpoint, and added voltage
Less with electric current, do not result in artificial burn, very helpful to the cause investigation of ineffective part.
Special needs to be pointed out is, only with the failure analysis of this semiconductor device in the specific embodiment of the invention
Method is as example, and the failure analysis method of the most any kind of semiconductor device is all suitable for this
The principle that invention discloses.For the person of ordinary skill of the art, made under the teachings of the present invention
For the equivalence change of the present invention, must be included in the scope that the claims in the present invention are advocated.
Claims (5)
1. the failure analysis method of the semiconductor device of a Plastic Package form, it is characterised in that: it includes step:
S101: use the salpeter solution of 70% to remove the layers of copper at the semiconductor device back side；
S103: the semiconductor device back side after removing layers of copper forms U-shaped window, uses full-automatic sample to prepare in this window
The silicon layer at the semiconductor device back side is carried out thinning by (Automated Sample Prep) equipment；And
S105: use low-light microscope (Emission Microscope, EMMI) and/or radium-shine optical beam induced change in impedance value
The failpoint at test (OBIRCH) the electrically semiconductor device back side, location equipment location.
2. the failure analysis method of the semiconductor device of Plastic Package form as claimed in claim 1, it is characterised in that described step
The salpeter solution using 70% in S101 soaks the back side of semiconductor device to remove layers of copper.
3. the failure analysis method of the semiconductor device of Plastic Package form as claimed in claim 1, it is characterised in that described step
S103 use three kinds of different drill bits silicon layer is ground thinning.
4. the failure analysis method of the semiconductor device of Plastic Package form as claimed in claim 1, it is characterised in that described OBIRCH
Electrically location equipment has drain end probe, gate end probe and source end probe, and semiconductor device includes having front
And the main part at the described back side and pin, wherein drain end probe directly contacts the back side of main part, gate end probe and source
End probe connects the pin of semiconductor device.
5. the failure analysis method of the semiconductor device of Plastic Package form as claimed in claim 4, it is characterised in that described partly lead
The back side of body device has layers of copper, silicon layer and chip-stack, wherein said drain end probe contact chip lamination successively.
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| CN201010605339.6A CN102565680B (en) | 2010-12-27 | 2010-12-27 | The failure analysis method of semiconductor device |
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| CN201010605339.6A CN102565680B (en) | 2010-12-27 | 2010-12-27 | The failure analysis method of semiconductor device |
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| CN102565680A CN102565680A (en) | 2012-07-11 |
| CN102565680B true CN102565680B (en) | 2016-09-14 |
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Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103969569B (en) * | 2013-01-25 | 2017-03-29 | 上海华虹宏力半导体制造有限公司 | The back surface optical failure localizing sample preparation method of integrated circuit and analysis method |
| CN103367191A (en) * | 2013-07-03 | 2013-10-23 | 上海华力微电子有限公司 | Failpoint locating method |
| CN104020408B (en) * | 2014-05-26 | 2016-07-06 | 武汉新芯集成电路制造有限公司 | Storage chip bit line failure analysis method |
| CN105334085B (en) * | 2014-08-12 | 2018-03-20 | 中芯国际集成电路制造(上海)有限公司 | Sample preparation methods and SIMS analysis method |
| CN107544012A (en) * | 2016-06-24 | 2018-01-05 | 上海北京大学微电子研究院 | Multichannel microscope semiconductor integrated test system |
| CN110634740B (en) * | 2019-08-29 | 2021-11-30 | 深圳赛意法微电子有限公司 | Improved back unsealing method of semiconductor device |
| CN110618004B (en) * | 2019-08-29 | 2022-04-01 | 深圳赛意法微电子有限公司 | Improved back unsealing method of semiconductor device |
| CN111370347A (en) * | 2020-03-24 | 2020-07-03 | 上海华虹宏力半导体制造有限公司 | Failure analysis method of power device |
| KR20220046732A (en) | 2020-10-07 | 2022-04-15 | 삼성전자주식회사 | Substrate testing apparatus |
| CN113406472A (en) * | 2021-05-17 | 2021-09-17 | 世强先进(深圳)科技股份有限公司 | Back analysis method for failure reasons of light-emitting chip |
| CN117080066B (en) * | 2023-10-13 | 2024-01-26 | 深圳基本半导体有限公司 | Method for removing layer on surface layer of silicon carbide chip |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1108808A (en) * | 1994-02-22 | 1995-09-20 | 国际商业机器公司 | Method for recovering bare semiconductor chips from plastic packaged moduler |
| CN1147146A (en) * | 1995-06-30 | 1997-04-09 | 现代电子产业株式会社 | Deprocessing method for analyzing failure in semiconductor device |
| US6245586B1 (en) * | 1998-10-09 | 2001-06-12 | James Barry Colvin | Wire-to-wire bonding system and method |
| CN1877292A (en) * | 2005-06-10 | 2006-12-13 | 联华电子股份有限公司 | Defect detection method |
| CN101769876A (en) * | 2008-12-29 | 2010-07-07 | 中芯国际集成电路制造(上海)有限公司 | Method for carrying out failure analysis in semiconductor device |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7098143B2 (en) * | 2003-04-25 | 2006-08-29 | Texas Instruments Incorporated | Etching method using an at least semi-solid media |
| US7786451B2 (en) * | 2003-10-16 | 2010-08-31 | Alis Corporation | Ion sources, systems and methods |
-
2010
- 2010-12-27 CN CN201010605339.6A patent/CN102565680B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1108808A (en) * | 1994-02-22 | 1995-09-20 | 国际商业机器公司 | Method for recovering bare semiconductor chips from plastic packaged moduler |
| CN1147146A (en) * | 1995-06-30 | 1997-04-09 | 现代电子产业株式会社 | Deprocessing method for analyzing failure in semiconductor device |
| US6245586B1 (en) * | 1998-10-09 | 2001-06-12 | James Barry Colvin | Wire-to-wire bonding system and method |
| CN1877292A (en) * | 2005-06-10 | 2006-12-13 | 联华电子股份有限公司 | Defect detection method |
| CN101769876A (en) * | 2008-12-29 | 2010-07-07 | 中芯国际集成电路制造(上海)有限公司 | Method for carrying out failure analysis in semiconductor device |
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Effective date of registration: 20171207 Address after: 214028 Xinzhou Road, Wuxi national hi tech Industrial Development Zone, Jiangsu, China, No. 8 Patentee after: Wuxi Huarun Shanghua Technology Co., Ltd. Address before: 214028 Wuxi provincial high tech Industrial Development Zone, Hanjiang Road, No. 5, Jiangsu, China Patentee before: Wuxi CSMC Semiconductor Co., Ltd. |