CN102544041B - Pixel cell of cmos image sensor and preparation method thereof - Google Patents
Pixel cell of cmos image sensor and preparation method thereof Download PDFInfo
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- CN102544041B CN102544041B CN201210014840.4A CN201210014840A CN102544041B CN 102544041 B CN102544041 B CN 102544041B CN 201210014840 A CN201210014840 A CN 201210014840A CN 102544041 B CN102544041 B CN 102544041B
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Abstract
The invention discloses pixel cell of a kind of cmos image sensor and preparation method thereof, this pixel cell comprises monocrystalline substrate, the shallow trench isolation region arranged in monocrystalline substrate, the transfering transistor arranged between shallow trench isolation region and bury type light sensitive diode, wherein transfering transistor comprises threshold voltage adjustments district, threshold voltage adjustments district is positioned at below transfer transistor gate and gate dielectric layer thereof, and threshold voltage adjustments district impurities is along orientation having different CONCENTRATION DISTRIBUTION, in the close threshold voltage adjustments district impurity concentration of impurity concentration higher than the side, floating diffusion region that drains at close transfering transistor of burying the threshold adjustment region of type light sensitive diode side, at transfering transistor lower channels, place forms certain impurity concentration gradient, thus define certain potential gradient.By optimizing pixel cell structure and technological parameter, can the image retention of removal of images transducer effectively according to cmos image sensor of the present invention, thus improve image quality.
Description
Technical field
The present invention relates to a kind of CMOS (Complementary Metal Oxide Semiconductor) (ComplementaryMetal-Oxide-Semiconductor is called for short CMOS) technical field, particularly relate to pixel cell of a kind of cmos image sensor and preparation method thereof.
Background technology
Imageing sensor is generally used for optical signalling to be converted to the signal of telecommunication, it is the important component part of composition digital camera, according to the difference of device, Charge-Coupled Device Array (charge CoupledDevice can be divided into, be called for short CCD) and cmos image sensor type (CMOS Image Sensor is called for short CIS) two large classes.In recent years, cmos image sensor development rapidly, compared to traditional ccd image sensor, cmos image sensor have can on sheet simultaneously integrated image sensor array and relevant numeral, analog circuit, and low-power consumption, the feature such as chip area is little, cost of manufacture is low.
The basic photosensitive unit of cmos image sensor is called as pixel, wherein, pixel for described cmos image sensor at least comprises a light sensitive diode, a transfering transistor and is positioned at floating diffusion region (the Floating Diffusion of transfering transistor drain electrode, be called for short FD), comprise other several transistors in addition, according to pixels comprise transistor size and be called as 4T type pixel, 5T type pixel, 6T type pixel and 7T type pixel etc.For 4T type cmos image sensor pixel, comprise: light sensitive diode, a transfering transistor and be positioned at transfering transistor drain electrode FD, comprise other 3 MOS transistor in addition: reset transistor, source follower transistor and select transistor.
The cmos image sensor course of work is: first incident light produces photogenerated charge in light sensitive diode district, then photogenerated charge transfers to floating diffusion region FD when transfering transistor is opened, the photogenerated charge finally transferring to FD again after other MOS transistor change into voltage signal and to go forward side by side line correlation process.In the process, what described photogenerated charge transferred to that FD relies on is electrical potential difference when transfering transistor is opened between light sensitive diode district and floating diffusion region FD.
Such problem is there is: after burying the photogenerated charge in type light sensitive diode and transferring to floating diffusion region FD in the above-mentioned cmos image sensor course of work, FD place, floating diffusion region electromotive force reduces, the electrical potential difference of burying like this between type light sensitive diode and floating diffusion region FD point reduces, like this, when transfering transistor control gate bias voltage reduces, if light sensitive diode and FD point electromotive force are relatively, average is assigned to light sensitive diode district and FD place, floating diffusion region by the electric charge in transfer transistor gate lower channels, like this, the electric charge returning to light sensitive diode district becomes residual charge, superpose with photogenerated charge next time, cause image retention, reduce image quality.
Therefore, need a kind of pixel cell of novel cmos image sensor, described pixel cell significantly can reduce the image retention of cmos image sensor, improves image quality.
Summary of the invention
(1) technical problem that will solve
In view of this, main purpose of the present invention is to provide and a kind ofly can significantly reduces pixel cell of the cmos image sensor of image retention and preparation method thereof.
(2) technical scheme
For achieving the above object, technical scheme of the present invention is achieved in that
A kind of pixel cell of cmos image sensor, comprise monocrystalline substrate, the shallow trench isolation region arranged in this monocrystalline substrate, the transfering transistor arranged between this shallow trench isolation region and bury type light sensitive diode, wherein said transfering transistor comprises threshold voltage adjustments district.
In such scheme, described monocrystalline substrate adopts silicon substrate or the P type epitaxial film silicon chip of P type; The conduction type in described threshold voltage adjustments district is P type.
In such scheme, containing impurity in the threshold voltage adjustments district of described transfering transistor, this impurity, along orientation having different CONCENTRATION DISTRIBUTION, is specially: in the close threshold voltage adjustments district impurity concentration of impurity concentration higher than the side, floating diffusion region that drains at close transfering transistor of burying the threshold adjustment region of type light sensitive diode side.
In such scheme, the threshold voltage adjustments district of described transfering transistor is positioned at below transfer transistor gate and gate dielectric layer thereof, a part is connected with the surface doping district of burying type light sensitive diode, another part be positioned at the floating diffusion region that transfering transistor drains and be connected; Wherein be positioned at the threshold voltage adjustments district of burying type light sensitive diode side overlapping with burying the type light sensitive diode buried regions district upper section that adulterates, the length of lap is 0.0 ~ 0.35 μm.
Make a method for the pixel cell of cmos image sensor, comprising: step 1: single-crystal semiconductor substrate is provided, and in this single-crystal semiconductor substrate, form transfering transistor and the shallow trench isolation region of burying type light sensitive diode; Step 2: form first time ion implanted region, threshold voltage adjustments district; Step 3: form second time ion implanted region, threshold voltage adjustments district; Step 4: form the buried implant of burying type light sensitive diode; Step 5: form transfering transistor gate dielectric layer and grid; Step 6: the light doping section and the heavily doped region that form transfering transistor drain electrode, the light doping section of described transfering transistor is connected with adjacent shallow trench isolation region and transfering transistor threshold voltage adjustments district with heavily doped region; Step 7: form the surface doping district of burying type light sensitive diode.
In such scheme, described monocrystalline substrate adopts silicon substrate or the P type epitaxial film silicon chip of P type, described in bury type light sensitive diode buried regions doped region conduction type be N-type; First time ion implanted region, described threshold voltage adjustments district and second time ion implanted region conduction type are P type; It is described that to bury type light sensitive diode surface doping district conduction type be P type.
In such scheme, first time ion implanted region, described threshold voltage adjustments district and second time ion implanted region adopt the ion implantation of identical implantation dosage and Implantation Energy, or adopt different implantation dosages and the ion implantation of Implantation Energy; The dosage range that first time ion implanted region, described threshold voltage adjustments district and second time ion implanted region p type impurity inject is 5.0E11 ~ 1.0E13, and adopting Implantation Energy to be the boron of 2 ~ 30kev or Implantation Energy is the BF of 10 ~ 55kev
2.
In such scheme, a described threshold voltage adjustments district first time ion implanted region part is positioned at the buried regions doping overlying regions of burying type light sensitive diode, and all cover, grid and the gate dielectric layer inferior portion thereof of another part and transfering transistor are overlapping, and the length of lap is 0.0 ~ 0.5 μm.
In such scheme, below the described threshold voltage adjustments district second time complete cover gate in ion implanted region and gate dielectric layer thereof, partly overlap with first time ion implanted region, threshold voltage adjustments district, length of overlapped part is 0.0 ~ 0.5 μm, due in threshold voltage adjustments district first time ion implanted region carried out twice ion implantation with second time ion implanted region lap, therefore in threshold voltage adjustments district, described lap impurity concentration is the highest.
In such scheme, described in bury the buried regions doped region of type light sensitive diode overlapping with grid and gate dielectric layer inferior portion thereof, length of overlapped part is 0.0 ~ 0.35 μm.
In such scheme, described in bury type light sensitive diode buried regions doped region adopt ion implantation technique implantation dosage to be that the N-type impurity of 5.0E11 ~ 1.0E13 is formed, adopting Implantation Energy to be the arsenic of 50 ~ 350kev or Implantation Energy is the phosphorus of 30 ~ 250kev.
In such scheme, the gate dielectric layer of described transfering transistor adopts thermal oxidation to be formed, and material is SiO
2or SiN; Adopt the method depositing polysilicon of chemical vapor deposition, finally adopt mask technique and dry etching to form the grid of transfering transistor.
In such scheme, described type of burying light sensitive diode surface doping district employing ion implantation technique implantation dosage is that the p type impurity of 5.0E12 ~ 1.0E14 is formed, and adopts the boron of 2 ~ 25kev, the BF of 10 ~ 55kev
2or the indium of 15 ~ 60kev.
In such scheme, described type of burying light sensitive diode surface doping district and first time ion implanted region, threshold voltage adjustments district use same layer mask plate to carry out ion implantation.
(3) beneficial effect
As can be seen from technique scheme, the present invention has following beneficial effect:
1, pixel cell of cmos image sensor provided by the invention and preparation method thereof, the Impurity Distribution of finite concentration gradient is formed by the threshold voltage adjustments district below transfer transistor gate, thus in photogenerated charge transfer process, along Potential Distributing transfering transistor orientation defining certain gradient, like this, when transfering transistor turns off, just no longer average the shifting to raceway groove both sides of electric charge in transfering transistor raceway groove, but the overwhelming majority flow to floating diffusion region FD, the electric charge which reduces in transfer transistor gate lower channels rebounds to burying type light sensitive diode, decrease the electric charge of burying in type light sensitive diode remaining, because this reducing image retention, improve picture quality.
2, the pixel cell and preparation method thereof of cmos image sensor provided by the invention, because the buried regions doping of burying type light sensitive diode is overlapping with transfer transistor gate inferior portion, the charge barrier between light sensitive diode and transfering transistor can be reduced, reach the object reducing image retention further.
Accompanying drawing explanation
Figure 1 shows that the structural representation of cmos image sensor pixel cell provided by the invention;
Fig. 2 schematically illustrates the CONCENTRATION DISTRIBUTION schematic diagram of the transfer transistor gate lower channels of cmos image sensor pixel cell provided by the invention;
Fig. 3 ~ Figure 14 shows that making cmos image sensor pixel cell provided by the invention process schematic representation.
Embodiment
For making the object, technical solutions and advantages of the present invention clearly understand, below in conjunction with specific embodiment, and with reference to accompanying drawing, the present invention is described in more detail.
Owing to there is such problem in the cmos image sensor course of work: after burying the photogenerated charge in type light sensitive diode and transferring to floating diffusion region FD, FD place, floating diffusion region electromotive force reduces, the electrical potential difference of burying like this between type light sensitive diode and floating diffusion region FD point reduces, like this, when transfering transistor control gate bias voltage reduces, if light sensitive diode and FD point electromotive force are relatively, average is assigned to light sensitive diode district and FD place, floating diffusion region by the electric charge in transfer transistor gate lower channels, like this, the electric charge returning to light sensitive diode district becomes residual charge, superpose with photogenerated charge next time, cause image retention, reduce image quality.Therefore, the invention provides pixel cell of a kind of novel cmos image sensor and preparation method thereof, described pixel cell significantly can reduce the image retention of cmos image sensor, improves image quality.
In embodiments of the present invention, the pixel cell of cmos image sensor provided by the invention at least comprises buries type light sensitive diode and transfering transistor, the light sensitive diode of a specific embodiment of the present invention and transfering transistor structural representation as shown in Figure 1, Figure 1 shows that the structural representation of cmos image sensor pixel cell provided by the invention.
The pixel cell of the cmos image sensor shown in Fig. 1 comprises: the lap 1034 in monocrystalline substrate 101, the isolation structure 102 being positioned at monocrystalline substrate, threshold voltage adjustments district 103 and 104 and 103 and 104, the buried regions of burying type light sensitive diode adulterate 105, grid 107 and gate dielectric layer 106, transfering transistor drain floating diffusion region 108 and bury type light sensitive diode surface doping district 109.
In embodiments of the present invention, the monocrystalline substrate 101 of the pixel of the cmos image sensor shown in Fig. 1 adopts resistivity to be the p type single crystal silicon silicon chip of 5 ~ 50ohm.cm, alternatively, also can be that electrical resistivity of epitaxy is the P type epitaxial film of 5 ~ 50ohm.cm on the p type single crystal silicon silicon chip of very low resistivity (being less than 5ohm.cm).
In embodiments of the present invention, the isolation structure 102 of the pixel of the cmos image sensor shown in Fig. 1 is positioned at P monocrystalline substrate 101 inside, adopts shallow trench isolation to use SiO from (STI) technology
2material or SiO
2isolate with the composite material of SiN.
In embodiments of the present invention, be provided with transfering transistor between the isolation structure 102 of the pixel of the cmos image sensor shown in Fig. 1 and bury type light sensitive diode, wherein, described transfering transistor comprises: grid 107 and gate dielectric layer 106, the lap 1034 in threshold voltage adjustments district 103,104,103 and 104, transfering transistor drain floating diffusion region 109; Described type light sensitive diode of burying comprises buried regions doping 105 and surface doping district 110.
In embodiments of the present invention, transfering transistor threshold voltage adjustments district shown in Fig. 1 comprises different two regions 103 and 104 of two impurity concentrations, wherein, described threshold voltage adjustments district overlaps, overlapping region is 1034, overlapping region, wherein said threshold voltage adjustments district 103 and 104 1034 is near burying type light sensitive diode side, impurity concentration is higher, described threshold voltage adjustments district 104 is near transfering transistor drain electrode FD side, floating diffusion region, impurity concentration is lower, Figure 2 shows that transfering transistor threshold voltage adjustments district is along the impurities concentration distribution in orientation.
By optimizing the Structure and energy in threshold voltage adjustments district 103 and 104, impurity in raceway groove below transfer transistor gate is defining certain concentration gradient along orientation, like this, when transfering transistor works, to form the potential gradient along orientation in described transfering transistor lower channels, the electric charge be conducive in raceway groove shifts to transfering transistor drain electrode floating diffusion region.
In embodiments of the present invention, the gate dielectric layer 106 of the transfering transistor shown in Fig. 1 adopts the method for thermal oxidation to be formed, and employing material is SiO
2or SiON; Adopt the method for chemical vapor deposition to be formed for the grid 107 above described gate dielectric layer 106, employing material is polysilicon.
In embodiments of the present invention, the drain electrode floating diffusion region 109 of the transfering transistor shown in Fig. 1 comprises drain electrode light doping section and drain electrode heavily doped region two parts, described light doping section has the effect preventing MOS transistor hot carrier's effect, described heavily doped region constitutes floating diffusion region FD, the area of heavily doped region and doping content determine the electric capacity of floating diffusion region FD, have impact to the conversion gain of imageing sensor.
In embodiments of the present invention, bury type light sensitive diode buried regions doped region 105 part shown in Fig. 1 to be positioned at and to bury below type light sensitive diode, a part is overlapping with transfer transistor gate 107 and gate dielectric layer 106 inferior portion thereof, length of overlapped part is 0.0 ~ 0.35 μm, by burying the Structure and energy of type light sensitive diode buried regions doping 105 described in optimizing, the charge barrier between light sensitive diode and transfering transistor can be reduced, reach the object reducing image retention.
In embodiments of the present invention, the length of burying type light sensitive diode surface doping district 109 shown in Fig. 1 need ensure to cover completely buries type light sensitive diode buried regions doped region 105, photogenerated charge in light sensitive diode is avoided and monocrystalline substrate 101 surface contact, there is the effect of pinning monocrystalline substrate 101 surface charge, make the electric leakage of light sensitive diode less, reduce dark current.
Based on the cmos image sensor pixel cell shown in Fig. 1 and Fig. 2, Fig. 3 ~ Figure 14 shows that making cmos image sensor pixel cell provided by the invention process schematic representation, specifically comprise step:
Step 1, as shown in Figure 3, first single-crystal semiconductor substrate is provided, described monocrystalline substrate 101 adopts resistivity to be the p type single crystal silicon silicon chip of 5 ~ 50ohm.cm, and in single-crystal semiconductor substrate, form transfering transistor and the isolation structure 102 of burying type light sensitive diode, described isolation structure 102 adopts shallow trench isolation to be formed from (STI) technology, and material is SiO
2or SiN;
Step 2, as shown in Figure 4, for the ion implanted regions of first time ion implanted region 103, described threshold voltage adjustments district when layout design, described threshold voltage adjustments district first time ion implanted region employing ion implantation technique implantation dosage is that the p type impurity of 5.0E11 ~ 1.0E13 is formed, can be the boron of 2 ~ 30kev for Implantation Energy, can be also the BF of 10 ~ 55kev for Implantation Energy
2, the first time ion implanted region 103, threshold voltage adjustments district formed after Figure 5 shows that ion implantation;
Step 3, as shown in Figure 6, for the ion implanted regions of described threshold voltage adjustments district second time ion implanted region 104 when layout design, described threshold voltage adjustments district second time ion implanted region employing ion implantation technique implantation dosage is that the p type impurity of 5.0E11 ~ 1.0E13 is formed, can be the boron of 2 ~ 30kev for Implantation Energy, can be also the BF of 10 ~ 55kev for Implantation Energy
2the second time ion implanted region 104, threshold voltage adjustments district formed after Figure 7 shows that ion implantation, wherein, when layout design, second time ion implanted region 104, described threshold voltage adjustments district is completely below cover gate and gate dielectric layer thereof, partly overlap with first time ion implanted region 103, threshold voltage adjustments district, length of overlapped part is 0.0 ~ 0.5 μm, like this due in threshold voltage adjustments district first time ion implanted region carried out twice ion implantation with second time ion implanted region lap 1034, therefore described lap has maximum impurity concentration;
Step 4, as shown in Figure 8, for burying the ion implanted regions of the buried doped layer heteroion injection region 105 of type light sensitive diode described in when layout design, described buried regions doped region 105 of burying type light sensitive diode adopt ion implantation technique implantation dosage be 5.0E11 ~ 1.0E13 N-type impurity formed, can be the arsenic of 50 ~ 350kev for Implantation Energy, also can be the phosphorus of 30 ~ 250kev for Implantation Energy, the buried regions doped region 105 of type of the burying light sensitive diode formed after Figure 9 shows that ion implantation;
Step 5, as shown in Figure 10, form transfering transistor gate dielectric layer 106 and grid 107, described gate dielectric layer 106 adopts thermal oxidation process to be formed, and material is SiO
2or SiON; Described grid 107 is above gate dielectric layer 106, employing depositing polysilicon is formed, mask plate and lithographic technique is finally adopted to form grid, when layout design, described buried regions doped region of burying type light sensitive diode is overlapping with grid and gate dielectric layer inferior portion thereof, and length of overlapped part is 0.0 ~ 0.35 μm;
Step 6, as shown in figure 11, for light doping section and the ion implanted regions, heavily doped region of transfering transistor drain electrode described when layout design, adopt and formed with the ion implantation of standard CMOS process compatibility, the light doping section of described transfering transistor is connected with adjacent shallow trench isolation region and transfering transistor threshold voltage adjustments district with heavily doped region, as shown in figure 12, the floating diffusion region 108 of transfering transistor drain electrode is formed together;
Step 7, as shown in figure 13, for burying the ion implanted regions in the surface doping district 109 of type light sensitive diode described in when layout design, described type of burying light sensitive diode surface doping district 109 adopt ion implantation technique implantation dosage be 5.0E12 ~ 1.0E14 p type impurity formed, can be the boron of 2 ~ 25kev, also can be the BF of 10 ~ 55kev
2, can also be the indium of 15 ~ 60kev.
It should be noted that, in above step, step 2 formed first time ion implanted region 103, described threshold voltage adjustments district and step 7 formed described in what bury that the surface doping district 109 of type light sensitive diode adopts is that identical one deck mask plate carries out ion implantation, thus reduce cost of manufacture.
Above-described specific embodiment; object of the present invention, technical scheme and beneficial effect are further described; be understood that; the foregoing is only specific embodiments of the invention; be not limited to the present invention; within the spirit and principles in the present invention all, any amendment made, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (8)
1. the pixel cell of a cmos image sensor, comprise monocrystalline substrate, the shallow trench isolation region arranged in this monocrystalline substrate, the transfering transistor arranged between this shallow trench isolation region and bury type light sensitive diode, it is characterized in that, described transfering transistor comprises threshold voltage adjustments district;
Containing impurity in the threshold voltage adjustments district of described transfering transistor, this impurity, along orientation having different CONCENTRATION DISTRIBUTION, is specially: in the close threshold voltage adjustments district impurity concentration of impurity concentration higher than the side, floating diffusion region that drains at close transfering transistor of burying the threshold adjustment region of type light sensitive diode side;
Wherein, the threshold voltage adjustments district of described transfering transistor is positioned at below transfer transistor gate and gate dielectric layer thereof, a part is connected with the surface doping district of burying type light sensitive diode, another part be positioned at the floating diffusion region that transfering transistor drains and be connected; Be positioned at the threshold voltage adjustments district of burying type light sensitive diode side overlapping with burying the type light sensitive diode buried regions district upper section that adulterates, the length of lap is 0.0 ~ 0.35 μm;
Described threshold voltage adjustments district comprises twice ion implanted region, an ion implanted region part is positioned at the buried regions doping overlying regions of burying type light sensitive diode for the first time, and all cover, grid and the gate dielectric layer inferior portion thereof of another part and transfering transistor are overlapping, and the length of lap is 0.0 ~ 0.5 μm;
Below the described threshold voltage adjustments district second time complete cover gate in ion implanted region and gate dielectric layer thereof, partly overlap with first time ion implanted region, threshold voltage adjustments district, length of overlapped part is less than or equal to 0.5 μm for being greater than 0, due in threshold voltage adjustments district first time ion implanted region carried out twice ion implantation with second time ion implanted region lap, therefore in threshold voltage adjustments district, described lap impurity concentration is the highest;
Described type of burying light sensitive diode surface doping district and first time ion implanted region, threshold voltage adjustments district use same layer mask plate to carry out ion implantation.
2. the pixel cell of cmos image sensor according to claim 1, is characterized in that, described monocrystalline substrate adopts silicon substrate or the P type epitaxial film silicon chip of P type; The conduction type in described threshold voltage adjustments district is P type.
3. make a method for the pixel cell of the cmos image sensor according to any one of claim 1 to 2, it is characterized in that, comprising:
Step 1: single-crystal semiconductor substrate is provided, and in this single-crystal semiconductor substrate, form transfering transistor and the shallow trench isolation region of burying type light sensitive diode;
Step 2: form first time ion implanted region, threshold voltage adjustments district;
Step 3: form second time ion implanted region, threshold voltage adjustments district;
Step 4: form the buried implant of burying type light sensitive diode;
Step 5: form transfering transistor gate dielectric layer and grid;
Step 6: the light doping section and the heavily doped region that form transfering transistor drain electrode, the light doping section of described transfering transistor is connected with adjacent shallow trench isolation region and transfering transistor threshold voltage adjustments district with heavily doped region;
Step 7: form the surface doping district of burying type light sensitive diode;
Wherein, described in bury the buried regions doped region of type light sensitive diode overlapping with grid and gate dielectric layer inferior portion thereof, length of overlapped part is 0.0 ~ 0.35 μm.
4. the method for the pixel cell of making cmos image sensor according to claim 3, it is characterized in that, described monocrystalline substrate adopts silicon substrate or the P type epitaxial film silicon chip of P type, described in bury type light sensitive diode buried regions doped region conduction type be N-type; First time ion implanted region, described threshold voltage adjustments district and second time ion implanted region conduction type are P type; It is described that to bury type light sensitive diode surface doping district conduction type be P type.
5. the method for the pixel cell of making cmos image sensor according to claim 3, it is characterized in that, first time ion implanted region, described threshold voltage adjustments district and second time ion implanted region adopt the ion implantation of identical implantation dosage and Implantation Energy, or adopt the different ion implantations entering dosage and Implantation Energy; The dosage range that first time ion implanted region, described threshold voltage adjustments district and second time ion implanted region p type impurity inject is 5.0E11 ~ 1.0E13, and adopting Implantation Energy to be the boron of 2 ~ 30kev or Implantation Energy is the BF of 10 ~ 55kev
2.
6. the method for the pixel cell of making cmos image sensor according to claim 3, it is characterized in that, described buried regions doped region of burying type light sensitive diode adopts ion implantation technique implantation dosage to be that the N-type impurity of 5.0E11 ~ 1.0E13 is formed, and adopting Implantation Energy to be the arsenic of 50 ~ 350kev or Implantation Energy is the phosphorus of 30 ~ 250kev.
7. the method for the pixel cell of making cmos image sensor according to claim 3, is characterized in that, the gate dielectric layer of described transfering transistor adopts thermal oxidation to be formed, and material is SiO
2or SiN; Adopt the method depositing polysilicon of chemical vapor deposition, finally adopt mask technique and dry etching to form the grid of transfering transistor.
8. the method for the pixel cell of making cmos image sensor according to claim 3, it is characterized in that, described type of burying light sensitive diode surface doping district employing ion implantation technique implantation dosage is that the p type impurity of 5.0E12 ~ 1.0E14 is formed, and adopts the boron of 2 ~ 25kev, the BF of 10 ~ 55kev
2or the indium of 15 ~ 60kev.
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| US8809925B2 (en) * | 2012-10-11 | 2014-08-19 | Omnivision Technologies, Inc. | Partial buried channel transfer device in image sensors |
| CN103066086B (en) * | 2012-12-18 | 2017-05-31 | 上海集成电路研发中心有限公司 | A kind of cmos image sensor pel array and its manufacture method |
| CN103915457A (en) * | 2014-03-14 | 2014-07-09 | 复旦大学 | Silicon-based CMOS image sensor and method of the silicon-based CMOS image sensor for restraining photon-generated carrier surface trap recombination |
| CN104617119B (en) * | 2014-12-10 | 2017-12-22 | 中国科学院半导体研究所 | The high-speed cmos image sensor pixel cells and preparation method of compatible ranging |
| CN104505394B (en) * | 2014-12-10 | 2019-02-01 | 中国科学院半导体研究所 | The cmos image sensor pixel unit and preparation method thereof of compatible ranging |
| CN106356382A (en) * | 2015-07-16 | 2017-01-25 | 中芯国际集成电路制造(上海)有限公司 | CMOS image sensor and manufacturing method thereof |
| CN109244094A (en) * | 2018-09-06 | 2019-01-18 | 德淮半导体有限公司 | Pixel unit and its manufacturing method, imaging sensor and imaging device |
| CN110085609A (en) * | 2019-04-08 | 2019-08-02 | 天津大学 | Image sensor pixel structure and preparation method thereof with low-light mode |
| CN113382184B (en) * | 2021-06-09 | 2023-12-01 | 上海矽印科技有限公司 | Method for automatically adjusting high dynamic range pixel by gain |
| CN115911072B (en) * | 2023-01-04 | 2023-05-26 | 湖北江城芯片中试服务有限公司 | Semiconductor device, manufacturing method thereof and CMOS image sensor |
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