CN102542094A - Nano-scale multi-fork radio frequency CMOS (Complementary Metal-Oxide-Semiconductor) model and extraction method thereof - Google Patents
Nano-scale multi-fork radio frequency CMOS (Complementary Metal-Oxide-Semiconductor) model and extraction method thereof Download PDFInfo
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Abstract
The invention provides a nano-scale multi-fork radio frequency CMOS (Complementary Metal-Oxide-Semiconductor Transistor) model. The model comprises a core MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) model and a periphery equivalent parasitic parameter sub-circuit, wherein STI (Shallow Trench Isolation) stress model parameters of the core MOS model, i.e. Kvtho, kuo and lkuo, are obtained through revising the difference between measurement data of a general NMOS (N-Channel Metal Oxide Semiconductor) direct current model and simulation characteristic of a general CMOS direct current model of a multi-fork radio frequency CMOS device. The nano-scale multi-fork radio frequency CMOS model provided by the invention can be applied in measurement of multi-fork CMOS devices and fits well with the devices and has relatively high accuracy of a precision extraction method.
Description
Technical field
The present invention relates to a kind of CMOS model, relate in particular to the how interdigital RF CMOS model of a kind of nanoscale.
Background technology
Along with the CMOS technology is increasingly extensive in the application in radio frequency (RF) field, product design becomes more and more important to the accuracy of the high frequency model of MOS device to RF.Because the ghost effect when high frequency of MOS device is complicated and bigger with the domain correlativity, present way is that the mode with macro model is that the MOS device is set up high frequency model.
At Chinese invention patent " calculation method of parameters " (application number: 200710094514.8 applyings date: 2007-12-14), a kind of RFCMOS model and calculation method of parameters are provided with RFCMOS model of extendability.
But this patent has only related to conventional single tine and has referred to MOS, and reckons without multi-interdigital CMOS and receive STI (shallow trench isolation) stress influence.Since in how interdigital cmos device, each interdigital stress influence that introduced by STI, and other polysilicons are interdigital simultaneously also exists certain stress influence to it.
Simultaneously this patent also and reckon without the RFMOS device under interdigital more situation, firing current is very big, the channel resistance very little (less than 10 ohm) of equivalence.This moment, the measurement to its DC characteristic received the dead resistance influence in probe and the measuring system easily.
And under bigger, the interdigital more situation of grid width the size variable source of the model of this patent, omit living resistance parameter computing formula and out of true.
Therefore, those skilled in the art is devoted to develop a kind of accurate, is applicable to how interdigital nanoscale RF CMOS DC SPICE model.
Summary of the invention
Technical matters to be solved by this invention provides a kind of how interdigital RF CMOS model of nanoscale with degree of precision.
For solving above-mentioned technical matters; The how interdigital RF CMOS model of a kind of nanoscale of the present invention; Comprise core MOSFET model and peripheral equivalent parasitic parameter electronic circuit; Said core MOSFET model comprises source, drain electrode and source, drain electrode dead resistance; Comprise STI stress model parameter K vtho, kuo and lkuo in the parameter of said core MOSFET model, said parameter K vtho, kuo and lkuo draw according to the measurement data of the conventional NMOS DC Model of large scale multi-interdigital CMOS device and the difference correction of conventional cmos DC Model simulated properties existence.
In a preferred embodiments of the present invention, Id-VgVds=1.2V that said STI stress model parameter K vtho, kuo and lkuo measure through the conventional NMOS DC Model of large scale multi-interdigital CMOS device and Id-VgVds=0V characteristic curve are revised and are drawn.
In another preferred embodiments of the present invention, the source of said MOSFET model, drain electrode also comprise probe dead resistance R
Probe_sourceAnd R
Probe_drainSaid R
Probe_source=R
Probe_drainThrough interdigital at most, wide and the shortest its following formula of DC measurement data substitution (1) of RFMOS device, (2), (3) simultaneous solution of raceway groove extract said R
Probe_sourceAnd R
Probe_drain
Wherein Vgs ' is virtual voltage between the MOSFET grid after the eliminating source region probe introducing dead resistance dividing potential drop effect, source; Vds ' is virtual voltage between the MOSFET leakage after the eliminating drain region probe introducing dead resistance dividing potential drop effect, source, V
DsBe drain voltage, I
DsBe leakage current, V
GsBe gate voltage, V
ThBe the fault threshold voltage.
In another preferred embodiments of the present invention, said source, drain electrode dead resistance Rd and Rs are source, the drain electrode dead resistance of size variable, and the parameter calculation formula of said Rd and Rs is:
Wherein, R
0Representative source, drain resistance initial value, W are the device channel width, and L is a channel length; NF is interdigital number; Wfactro is the index of the interdigital power function that is inversely proportional to source, drain resistance, and Lc is the coefficient of channel length continuous item in source, the drain resistance formula, and Lfactro is the continuous item index.
The present invention also provides the parameter extracting method of the how interdigital RF CMOS model of nanoscale, may further comprise the steps:
Step 1, choosing the long how interdigital MOS device of large-size of raceway groove is target, enterprising capable STI stress correlation parameter is optimized on the how interdigital MOS device of 65nm the following stated direct current measurement data basis;
Step 2, the following how interdigital MOS device of 65nm of choosing all sizes is a target, enterprising capable probe resistance extracts on the following direct current measurement data of 65nm basis;
Step 3 is chosen the raceway groove broad, and is interdigital maximum, and the MOS device is a target to receive probe resistance to influence the most significantly, omits the size variable formula of living resistance with extraction source on the following direct current measurement data of its 65nm basis;
Step 4 carries out curve fitting and final argument optimization according to the simulation curve and the measurement data of used scale device.
Model of the present invention can be good at match with device in can being applicable to that multi-interdigital CMOS device is measured, and has higher degree of accuracy.Its method for distilling is accurately quick.
Description of drawings
Fig. 1 is that the present invention is the multi-interdigital CMOS equivalent circuit macro models that embodiment adopts.
Embodiment
As shown in fig. 1; In an embodiment of the present invention; The how interdigital RF CMOS model of a kind of nanoscale; Comprise core MOSFET model 1 and peripheral equivalent parasitic parameter electronic circuit, the STI stress model parameter of said core MOSFET model is: STI stress model parameter K vtho, kuo and lkuo in the difference correction routine MOS model that exists according to the measurement data and the conventional cmos DC Model simulated properties of the conventional NMOS DC Model of large scale multi-interdigital CMOS device.
As kernel model, the form of the peripheral equivalent parasitic parameter electronic circuit of arranging in pairs or groups is that the nanoscale multi-interdigital CMOS device makes up complete S PICE simulated macro model to the present invention's employing with CMOS SPICE model.Wherein core CMOS SPICE model parameter need test and extract through conventional cmos DC Model test structure; Again STI parameter is wherein revised.
The parameter extracting method of the how interdigital RF CMOS model of nanoscale of the present invention may further comprise the steps:
Step 1, choosing the long how interdigital MOS device of large-size of raceway groove is target, enterprising capable STI stress correlation parameter is optimized on the how interdigital MOS device of 65nm the following stated direct current measurement data basis;
Step 2, the following how interdigital MOS device of 65nm of choosing all sizes is a target, enterprising capable probe resistance extracts on the following direct current measurement data of 65nm basis;
Step 3 is chosen the raceway groove broad, and is interdigital maximum, and the MOS device is a target to receive probe resistance to influence the most significantly, omits the size variable formula of living resistance with extraction source on the following direct current measurement data of its 65nm basis;
Step 4 carries out curve fitting and final argument optimization according to the simulation curve and the measurement data of used scale device.
Model of the present invention can be good at match with device in can being applicable to that multi-interdigital CMOS device is measured, and has higher degree of accuracy.Its method for distilling is accurately quick.
In one embodiment of the invention, through building RF parasitic parameter numerical value in the dc parameter and the PSP that 65nm conventional cmos DC Model test structure are tested and extracted its core CMOS PSP model according to measurement data.Carried out correlative study for the existing numerous documents of 65nm conventional cmos DC Model parameter extraction, be not described in detail in this.
Because conventional cmos DC Model test structure and multi-interdigital CMOS model measurement structure domain there are differences, the conventional cmos device polysilicon grid that single tine refers to only receive the stress influence that STI introduces; And each interdigital stress influence that introduced by STI in the how interdigital cmos device, other polysilicons are interdigital simultaneously also exists certain stress influence to it.
Therefore, the STI stress model parameter to conventional NMOS DC Model is revised in the embodiments of the invention.Target devices need be chosen and receive probe dead resistance and source to omit living resistance to influence lessly, receive the STI layout to influence bigger large scale multi-interdigital CMOS device.Difference correction STI stress model parameter K vtho, kuo and lkuo according to its measurement data and the existence of conventional cmos DC Model simulated properties.
In an embodiment of the present invention; Owing to compare with conventional MOS device with same channel width and length; The how interdigital MOS device of large scale receives probe dead resistance and source to omit living resistance to be influenced less; It is bigger influenced by the STI layout, therefore can obtain comprising the RF MOS DC Model of STI influence through the Id-VgVds=1.2V of this device and STI stress model parameter K vtho, kuo and the lkuo in the conventional MOS model of Id-VdVbs=0V family curve correction.
In an embodiment of the present invention, because RF MOS device is under interdigital more situation, firing current is very big, the channel resistance very little (less than 10 ohm) of equivalence.This moment, the measurement to its DC characteristic received the dead resistance influence in probe and the measuring system easily, so the CMOS DC SPICE model of embodiments of the invention need extract and place the multi-interdigital CMOS macro model to the equivalent dead resistance of probe.Interdigital the DC characteristic of the RF MOS that raceway groove is wide and the shortest is had the greatest impact by the probe dead resistance at most, can extract probe resistance resistance, i.e. model parameter R through the match to its DC characteristic
Probe_sourceAnd R
Probe_drainIt is that 5 μ m, channel length are that 0.06 μ m, interdigital number are 64 RF NMOS that embodiments of the invention have been chosen channel width.The probe portion that can be considered contact source, drain electrode owing to the RF probe that the RF cmos device is tested is symmetrical, i.e. R
Probe_source=R
Probe_drain, extract probe resistance resistance R through following formula (1), (2), (3) simultaneous solution
Probe_sourceAnd R
Probe_drain
MOSFET electric current and voltage formula:
The influence that the probe dead resistance produces MOSFET:
Wherein Vgs ' is virtual voltage between the MOSFET grid after the eliminating source region probe introducing dead resistance dividing potential drop effect, source; Vds ' is virtual voltage between the MOSFET leakage after the eliminating drain region probe introducing dead resistance dividing potential drop effect, source.
After the present invention's probe dead resistance influence that to be embodiment introduced when having considered the STI influence and having measured, the conventional NMOS DC Model of correction still can't with the match well of most of RF MOS device.The how interdigital MOS device of this explanation still has part source leakage resistance not characterized.Living resistance is omitted in the source that is not characterized as yet and interdigital number is inversely proportional to, and is inversely proportional to channel width, is directly proportional with channel length.This physical characteristics with device is consistent.In view of the above, proposed in the embodiments of the invention size variable the source, omit living resistance (Rd, Rs) computing formula and living resistance value is omitted in this source simulated:
Wherein, R
0Representative source, drain resistance initial value, W are the device channel width, and L is a channel length; NF is interdigital number; Wfactro is the index of the interdigital power function that is inversely proportional to source, drain resistance, and Lc is the coefficient of channel length continuous item in source, the drain resistance formula, and Lfactro is the continuous item index.
In an embodiment of the present invention, the source that can extract each device through each RFCMOS direct current characteristic is carried out curve fitting, omit living resistance.Again according to variant size RFCMOS device source, omit situation that living resistance changes along with channel width W, channel length L, interdigital quantity NF to above-mentioned source, omit living resistance calculations formula and carry out parameter extraction, obtain the parameter values of Wfactr, NFfactor, Lfactor and Lc.
Embodiments of the invention obtain R after one group of all scale device of RF NMOS having been carried out correlation parameter extraction and curve fitting
0=34, Wfactor=0.5, NFfactor=0.9, Lfactor=1.7, Lc=0.002.Fitting result is as shown in table 1.Can know by following table, above-mentioned source, omit living resistance calculations formula and extraction the source, omit living resistance value very high degree of fitting arranged.
All scale device correlation parameter curve-fitting results tables of table 1:RF NMOS
More than specific embodiment of the present invention is described in detail, but it is just as example, the present invention is not restricted to the specific embodiment of above description.To those skilled in the art, any equivalent modifications that the present invention is carried out with substitute also all among category of the present invention.Therefore, not breaking away from impartial conversion and the modification of being done under the spirit and scope of the present invention, all should contain within the scope of the invention.
Claims (5)
1. how interdigital RF CMOS model of nanoscale; Comprise core MOSFET model and peripheral equivalent parasitic parameter electronic circuit; Said core MOSFET model comprises source, drain electrode and source, drain electrode dead resistance; Comprise STI stress model parameter K vtho, kuo and lkuo in the parameter of said core MOSFET model; It is characterized in that said parameter K vtho, kuo and lkuo draw according to the measurement data of the conventional NMOS DC Model of large scale multi-interdigital CMOS device and the difference correction of conventional cmos DC Model simulated properties existence.
2. the how interdigital RF CMOS model of nanoscale as claimed in claim 1; It is characterized in that Id-VgVds=1.2V that said STI stress model parameter K vtho, kuo and lkuo measure through the conventional NMOS DC Model of large scale multi-interdigital CMOS device and Id-VgVds=0V characteristic curve are revised and drawn.
3. the how interdigital RF CMOS model of nanoscale as claimed in claim 1 is characterized in that, the source of said MOSFET model, drain electrode also comprise probe dead resistance R
Probe_sourceAnd R
Probe_drainSaid R
Probe_source=R
Probe_drainThrough interdigital at most, wide and the shortest its following formula of DC measurement data substitution (1) of RFMOS device, (2), (3) simultaneous solution of raceway groove extract said R
Probe_sourceAnd R
Probe_drain
(2)
Wherein Vgs ' is virtual voltage between the MOSFET grid after the eliminating source region probe introducing dead resistance dividing potential drop effect, source; Vds ' is virtual voltage between the MOSFET leakage after the eliminating drain region probe introducing dead resistance dividing potential drop effect, source, V
DsBe drain voltage, I
DsBe leakage current, V
GsBe gate voltage, V
ThBe the fault threshold voltage.
4. the how interdigital RF CMOS model of nanoscale as claimed in claim 1 is characterized in that, said source, drain electrode dead resistance Rd and Rs are source, the drain electrode dead resistance of size variable, and the parameter calculation formula of said Rd and Rs is:
Wherein, R
0Representative source, drain resistance initial value, W are the device channel width, and L is a channel length; NF is interdigital number; Wfactro is the index of the interdigital power function that is inversely proportional to source, drain resistance, and Lc is the coefficient of channel length continuous item in source, the drain resistance formula, and Lfactro is the continuous item index.
5. the parameter extracting method of the how interdigital RF CMOS model of nanoscale according to claim 1 is characterized in that, may further comprise the steps:
Step 1, choosing the long how interdigital MOS device of large-size of raceway groove is target, enterprising capable STI stress correlation parameter is optimized on the how interdigital MOS device of 65nm the following stated direct current measurement data basis;
Step 2, the following how interdigital MOS device of 65nm of choosing all sizes is a target, enterprising capable probe resistance extracts on the following direct current measurement data of 65nm basis;
Step 3 is chosen the raceway groove broad, and is interdigital maximum, and the MOS device is a target to receive probe resistance to influence the most significantly, omits the size variable formula of living resistance with extraction source on the following direct current measurement data of its 65nm basis;
Step 4 carries out curve fitting and final argument optimization according to the simulation curve and the measurement data of used scale device.
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| WO2015109679A1 (en) * | 2014-01-27 | 2015-07-30 | 中国科学院微电子研究所 | Sti stress effect modelling method and apparatus for mos device |
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| CN112052637A (en) * | 2020-08-31 | 2020-12-08 | 中国科学院微电子研究所 | BSIMMG-based FDSOI MOSFET model generation method and device |
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Application publication date: 20120704 |