CN102522329A - Machining method of semiconductor chip - Google Patents
Machining method of semiconductor chip Download PDFInfo
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- CN102522329A CN102522329A CN2012100042166A CN201210004216A CN102522329A CN 102522329 A CN102522329 A CN 102522329A CN 2012100042166 A CN2012100042166 A CN 2012100042166A CN 201210004216 A CN201210004216 A CN 201210004216A CN 102522329 A CN102522329 A CN 102522329A
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- wafer
- electrode layer
- processing method
- semiconductor chip
- film process
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- 238000000034 method Methods 0.000 title claims abstract description 45
- 239000004065 semiconductor Substances 0.000 title claims abstract description 17
- 238000003754 machining Methods 0.000 title abstract 5
- 239000002184 metal Substances 0.000 claims abstract description 50
- 229910052751 metal Inorganic materials 0.000 claims abstract description 50
- 239000002253 acid Substances 0.000 claims abstract description 47
- 238000005530 etching Methods 0.000 claims abstract description 34
- 238000005219 brazing Methods 0.000 claims description 17
- 238000001259 photo etching Methods 0.000 claims description 15
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 14
- 238000003672 processing method Methods 0.000 claims description 13
- 229910000679 solder Inorganic materials 0.000 claims description 9
- 230000007797 corrosion Effects 0.000 claims description 7
- 238000005260 corrosion Methods 0.000 claims description 7
- 230000015572 biosynthetic process Effects 0.000 claims description 6
- 230000003628 erosive effect Effects 0.000 claims description 6
- 239000000203 mixture Substances 0.000 claims description 5
- 238000006396 nitration reaction Methods 0.000 claims description 5
- 238000006243 chemical reaction Methods 0.000 abstract description 3
- 229910052710 silicon Inorganic materials 0.000 abstract description 3
- 239000010703 silicon Substances 0.000 abstract description 3
- QTBSBXVTEAMEQO-UHFFFAOYSA-N Acetic acid Chemical compound CC(O)=O QTBSBXVTEAMEQO-UHFFFAOYSA-N 0.000 description 4
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 4
- 238000005336 cracking Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229960000583 acetic acid Drugs 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 239000012362 glacial acetic acid Substances 0.000 description 2
- 229910017604 nitric acid Inorganic materials 0.000 description 2
- 238000005554 pickling Methods 0.000 description 2
- 238000003466 welding Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- 238000004026 adhesive bonding Methods 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000009089 cytolysis Effects 0.000 description 1
- 239000008367 deionised water Substances 0.000 description 1
- 229910021641 deionized water Inorganic materials 0.000 description 1
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910021645 metal ion Inorganic materials 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
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Abstract
The invention discloses a machining method of a semiconductor chip, relating to a splitting process without mechanical damage, and provides a machining method of the semiconductor chip, which has the advantages of high efficiency and no mechanical damage and provides a friendly linkage measure. The machining method comprises the following steps of: 1, setting an electrode layer; 2, once acid-etching; and 3, secondarily acid-etching. According to the machining method, an electrode window is firstly formed, and then a metal electrode layer is coated and planted on the electrode window on the surface of a wafer. The metal electrode does not basically react with acid in processes of two times of acid etching. A strong chemical reaction exists between strong acid and a wafer body made of silicon, the wafer body can be rapidly etched, and further the wafer is split according to a designed shape, and finally, hexagonal, circular and other-shaped chips which are difficult to obtain by adopting common means are finally machined.
Description
Technical field
The present invention relates to a kind of manufacturing method for semiconductor chips, relate in particular to a kind of cracking technology that has no mechanical damage.
Background technology
Existing OJ (the open knot of Open Juction) type diode fabricating method mainly comprises the steps: to diffuse to form the semiconductor crystal wafer of required vertical structure; Nickel plating; Cut into square or regular hexagon list chips; Use weld tabs together with copper conductor and chip metal electrode layer welding assembly; Use the nitration mixture pickling; Gluing also solidify to form the passivation protection layer; The epoxy mold pressing is also solidified; Pin is zinc-plated; Testing package.The chip that this kind method is adopted is generally square after cutting; The bight is 90 °, and electric field strength is stronger at sharp corner, is prone to puncture lost efficacy; As cut into regular hexagon and have the waste of certain area, especially this contradiction of the product of large chip area is especially outstanding.
Prior art has been seen the report relevant for the regular hexagon chip in the led chip field.But be cracked into the technological means that regular hexagon makes chip through wafer does not appear in the newspapers in the prior art always.
Summary of the invention
The present invention is directed to above problem, provide a kind of ability efficient, have no mechanical damage, and the processing method of the semiconductor chip of friendly linking measure is provided for following process.
Technical scheme of the present invention is: may further comprise the steps: wafer is spread, is provided with oxide layer and the operation of photoetching window on oxide layer; Behind the photoetching window, said oxide layer is latticed in wafer surface; Processing according to the following steps then:
1), electrode layer is set; Toward the interior wafer surface metal lining electrode layer of said window;
2), acid etching; Adopt hydrofluoric acid to remove the latticed oxide layer of wafer surface, between said metal electrode layer, form latticed groove;
3), secondary acid etching; Down inject nitration mixture along latticed groove, corrosion wafer body passes through the wafer body until erosion, makes the wafer body be split into plurality of chips; Make.
After electrode layer is set, also comprise immediately the solder layer operation is set; Prewelding brazing metal on said metal electrode layer is fixedly connected in the scope of said metal electrode layer and window sidewall formation brazing metal.
Before a said acid etching operation, also have film process, said film process is for pasting one deck bonding diaphragm in the wafer bottom surface.
After a said acid etching operation, also have film process, said film process is for pasting one deck bonding diaphragm in the wafer bottom surface.
The regular polygon that is shaped as circle or bight band circular arc chamfering of said photoetching window.
Said oxide layer is set and on oxide layer the operation of photoetching window, and the said electrode layer operation that is provided with is carried out the two-sided of said wafer.
After electrode layer is set, also comprise immediately the solder layer operation is set; Prewelding brazing metal on said metal electrode layer is fixedly connected in the scope of said metal electrode layer and window sidewall formation brazing metal.
Before a said acid etching operation, also have film process, said film process is for pasting one deck bonding diaphragm in the wafer bottom surface.
After a said acid etching operation, also have film process, said film process is for pasting one deck bonding diaphragm in the wafer bottom surface.
Said photoetching window be shaped as circle or regular polygon.
Form earlier electrode window through ray in the technology of the present invention, metal lining electrode layer on the said electrode window through ray of wafer surface.Metal electrode layer is in the twice acid corrosion process in road, back, basically with acid reactionless (strong acid can make the metal electrode laminar surface form oxide-film).Strong acid and siliceous wafer body have strong chemical reaction, and rapid " erosion is passed through " wafer body, and then make wafer according to the design shape cracking, finally make chips such as hexagon that conventional means is difficult to obtain, circle.Compare with blast technology: product does not have mechanical stress, is easy to implement.Compare with mechanical lysis technology, the advantage of this case is: the chip that can process arbitrary shape.The present invention has filled up the technological gap of special-shaped chip cracking.In addition, technology of the present invention can form circular arc chamfering in the bight of chip, can effectively avoid electric field to concentrate; Improve the electrical property of product; The solder layer of setting up is that following process provides friendly linking measure.The present invention is cut apart chip through chemical corrosion, obtains the chip of ideal form, and cracking process has no mechanical damage to chip basically, and the back road pickling time is short, and is little to the corrosion of metal amount, and metal ion stains few, has improved the product electrical reliability.
Description of drawings
Fig. 1 be the present invention oxide layer is set and on oxide layer the sketch map of photoetching window operation,
Fig. 2 is the sketch map that the present invention is provided with the electrode layer operation,
Fig. 3 is the sketch map of film process of the present invention,
Fig. 4 is the sketch map after twice acid etching operation of the present invention,
Fig. 5 is the structural representation of the chip one that makes of the present invention;
Fig. 6 is that the present invention optimizes the sketch map that the solder layer operation is set in the execution mode for first kind,
Fig. 7 is that first kind of the present invention optimizes in the execution mode sketch map that carries out film process behind acid etching again,
Fig. 8 is that first kind of the present invention optimizes the sketch map after the secondary acid etching operation in the execution mode,
Fig. 9 is the structural representation that first kind of the present invention optimizes the chip two that execution mode makes;
Figure 10 be second kind of the present invention optimize in the execution mode two-sided oxide layer is set and on oxide layer the sketch map of photoetching window operation,
Figure 11 is that the present invention optimizes the two-sided sketch map that the electrode layer operation is set in the execution mode for second kind,
Figure 12 is that the present invention optimizes the two-sided sketch map that the solder layer operation is set in the execution mode for second kind,
Figure 13 is that second kind of the present invention optimizes in the execution mode sketch map that carries out film process behind acid etching again,
Figure 14 is that second kind of the present invention optimizes in the execution mode sketch map that carries out film process before acid etching,
Figure 15 is that second kind of the present invention optimizes the sketch map after the secondary acid etching operation in the execution mode,
Figure 16 is the structural representation that second kind of the present invention optimizes the chip three that execution mode makes;
Figure 17 is first kind of flat shape of the obtained chip of the present invention,
Figure 18 is second kind of flat shape of the obtained chip of the present invention,
Figure 19 is the third flat shape of the obtained chip of the present invention,
Figure 20 is the 4th a kind of flat shape of the obtained chip of the present invention;
1 is wafer among the figure, the 2nd, and oxide layer, the 21st, window, the 3rd, metal electrode layer, the 4th, brazing metal, the 5th, blue film, the 61st, chip one, 62nd, chip two, 63rd, chip three.
Embodiment
Processing method of the present invention may further comprise the steps shown in Fig. 1-5:
Behind the photoetching window 21, said oxide layer 2 is latticed in wafer surface; Grid interior shape such as Figure 17-20, can be circular, have square, regular hexagon or the octagon of circular arc chamfering, and above-mentioned flat shape can form when film is set off in making according to the needs of concrete applied environment.
Processing according to the following steps then:
1), electrode layer is set; Like Fig. 2, toward said window 21 interior wafer surface metal lining electrode layers 3; As electrode;
2), acid etching; Adopt hydrofluoric acid to remove latticed oxide layer 2 grids on wafer 1 surface, between said metal electrode layer 3, form latticed groove; The acid solution of an acid etching is a hydrofluoric acid solution, and concentration is: 10-46%, the hydrofluoric acid ability corrosion surface oxide layer of this kind concentration facts have proved that this kind acid solution can not produce corrosiveness to metal electrode.
Before a said acid etching operation, also have film process, said film process is for pasting one deck bonding diaphragm in wafer 1 bottom surface; Adopt blue film 5 preferable as bonding diaphragm effect; Like Fig. 4.
After a said acid etching operation, also have film process, said film process is for pasting one deck bonding diaphragm in wafer 1 bottom surface; Adopt blue film 5 preferable as bonding diaphragm effect;
3), secondary acid etching; Down inject nitration mixture along latticed groove, corrosion wafer 1 body passes through the wafer body until erosion, makes the wafer body be split into plurality of chips; Make chip as shown in Figure 51.The acid solution of secondary acid etching can adopt combination allotments such as hydrofluoric acid, nitric acid, glacial acetic acid, sulfuric acid.Facts have proved that this kind acid solution is passed through under the situation of wafer body in erosion, this kind acid solution can not produce very strong corrosiveness to metal electrode, promptly can not destroy metal electrode.Ratio such as hydrofluoric acid, nitric acid, glacial acetic acid, sulfuric acid is 1:1:X:Y, the span 1-20 of X wherein, the span 1-15 of Y.
The present invention optimizes execution mode for first kind and comprises: after metal electrode layer 3 is set, also comprise the operation that solder layer is set immediately; Like Fig. 6, prewelding brazing metal 4 on said metal electrode layer 3 is fixedly connected in the scope of said metal electrode layer 3 and window sidewall formation brazing metal 4.Brazing metal 4 end faces are a little more than oxide layer 2 (upper window edge) when being provided with: avoid that the metal lead wire head is urged to the chip body in the later process, cause chip failure.And the welding processing in road, convenient back.
Optimize under the execution mode at this first kind, film process also can be taked before an acid etching or behind an acid etching, to carry out.It is as shown in Figure 7 to carry out film process behind the acid etching.Behind the secondary acid etching, as shown in Figure 8, the wafer body is passed through in final acid solution erosion, makes the wafer body be split into plurality of chips; After taking off one by one from the blue film 5, make chip as shown in Figure 92 62 (end face has brazing metal 4).
Second kind of the present invention optimizes execution mode: said oxide layer 2 is set and on oxide layer 2 operation of photoetching window 21 (like Figure 10), and said electrode layer 3 operations (like Figure 11) that are provided with are carried out the two-sided of said wafer 1.
After electrode layer 3 is set, also comprise immediately the solder layer operation is set, like Figure 12; Prewelding brazing metal 4 on said metal electrode layer 3 is fixedly connected in the scope of said metal electrode layer 3 and window 21 sidewalls formation brazing metal 4.
Optimize under the execution mode at second kind, before a said acid etching operation, also have film process, said film process is for pasting one deck bonding diaphragm in the wafer bottom surface; Adopt blue film 5 preferable as bonding diaphragm effect.Like Figure 14.
Optimize under the execution mode at second kind, after a said acid etching operation, also have film process, said film process is for pasting one deck bonding diaphragm in the wafer bottom surface; Adopt blue film 5 preferable as bonding diaphragm effect.Like Figure 13.
The secondary acid etching makes chip shown in figure 15 3 63 (end face and bottom surface are equipped with brazing metal 4) then.
Need to prove that the acid solution that is used to corrode the wafer body is basic identical to the mechanism of metal electrode layer 3, brazing metal 4, under concentrated acid reaction seldom, so the silicon layer below can sheltering is not corroded; Wafer body in the latticed groove then can be corroded until the silicon chip break-through by nitration mixture fast.
When removing blue film, need on refrigerator, to remove blue film, isolate single chips.
As required, also can clean, dry: chip put into HF acid clean, use deionized water rinsing, oven dry at last to remove the metal remained oxide to chip.
Claims (10)
1. the processing method of a semiconductor chip may further comprise the steps: wafer is spread, is provided with oxide layer and the operation of photoetching window on oxide layer; Behind the photoetching window, said oxide layer is latticed in wafer surface; It is characterized in that, then processing according to the following steps:
1), electrode layer is set; Toward the interior wafer surface metal lining electrode layer of said window;
2), acid etching; Adopt hydrofluoric acid to remove the latticed oxide layer of wafer surface, between said metal electrode layer, form latticed groove;
3), secondary acid etching; Down inject nitration mixture along latticed groove, corrosion wafer body passes through the wafer body until erosion, makes the wafer body be split into plurality of chips; Make.
2. the processing method of a kind of semiconductor chip according to claim 1 is characterized in that, after electrode layer is set, also comprises immediately the solder layer operation is set; Prewelding brazing metal on said metal electrode layer is fixedly connected in the scope of said metal electrode layer and window sidewall formation brazing metal.
3. the processing method of a kind of semiconductor chip according to claim 1 and 2 is characterized in that, before a said acid etching operation, also has film process, and said film process is for pasting one deck bonding diaphragm in the wafer bottom surface.
4. the processing method of a kind of semiconductor chip according to claim 1 and 2 is characterized in that, after a said acid etching operation, also has film process, and said film process is for pasting one deck bonding diaphragm in the wafer bottom surface.
5. the processing method of a kind of semiconductor chip according to claim 1 and 2 is characterized in that, the regular polygon that is shaped as circle or bight band circular arc chamfering of said photoetching window.
6. the processing method of a kind of semiconductor chip according to claim 1 is characterized in that, said oxide layer is set and on oxide layer the operation of photoetching window, and the said electrode layer operation that is provided with is carried out the two-sided of said wafer.
7. the processing method of a kind of semiconductor chip according to claim 6 is characterized in that, after electrode layer is set, also comprises immediately the solder layer operation is set; Prewelding brazing metal on said metal electrode layer is fixedly connected in the scope of said metal electrode layer and window sidewall formation brazing metal.
8. according to the processing method of claim 6 or 7 described a kind of semiconductor chips, it is characterized in that before a said acid etching operation, also having film process, said film process is for pasting one deck bonding diaphragm in the wafer bottom surface.
9. according to the processing method of claim 6 or 7 described a kind of semiconductor chips, it is characterized in that after a said acid etching operation, also having film process, said film process is for pasting one deck bonding diaphragm in the wafer bottom surface.
10. according to the processing method of claim 6 or 7 described a kind of semiconductor chips, it is characterized in that, said photoetching window be shaped as circle or regular polygon.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210004216.6A CN102522329B (en) | 2012-01-09 | 2012-01-09 | Machining method of semiconductor chip |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210004216.6A CN102522329B (en) | 2012-01-09 | 2012-01-09 | Machining method of semiconductor chip |
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| Publication Number | Publication Date |
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| CN102522329A true CN102522329A (en) | 2012-06-27 |
| CN102522329B CN102522329B (en) | 2014-03-12 |
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| CN201210004216.6A Expired - Fee Related CN102522329B (en) | 2012-01-09 | 2012-01-09 | Machining method of semiconductor chip |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104112661A (en) * | 2014-07-03 | 2014-10-22 | 扬州虹扬科技发展有限公司 | Cutting technology processing method |
| CN107733389A (en) * | 2017-11-01 | 2018-02-23 | 应达利电子股份有限公司 | A kind of quartz crystal is large stretch of and manufactures the method for small chips using it |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1564331A (en) * | 2004-04-05 | 2005-01-12 | 清华大学 | Method of mfg. GaN-base LED |
| CN101030616A (en) * | 2007-03-21 | 2007-09-05 | 山东华光光电子有限公司 | Production of high-brightness light-emitting diodes chip |
| US7579202B2 (en) * | 2007-12-21 | 2009-08-25 | Tekcore Co., Ltd. | Method for fabricating light emitting diode element |
| CN101859852A (en) * | 2010-05-13 | 2010-10-13 | 厦门市三安光电科技有限公司 | Manufacturing process for improving capacity of aluminum gallium indium phosphorus light-emitting diodes |
-
2012
- 2012-01-09 CN CN201210004216.6A patent/CN102522329B/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1564331A (en) * | 2004-04-05 | 2005-01-12 | 清华大学 | Method of mfg. GaN-base LED |
| CN101030616A (en) * | 2007-03-21 | 2007-09-05 | 山东华光光电子有限公司 | Production of high-brightness light-emitting diodes chip |
| US7579202B2 (en) * | 2007-12-21 | 2009-08-25 | Tekcore Co., Ltd. | Method for fabricating light emitting diode element |
| CN101859852A (en) * | 2010-05-13 | 2010-10-13 | 厦门市三安光电科技有限公司 | Manufacturing process for improving capacity of aluminum gallium indium phosphorus light-emitting diodes |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104112661A (en) * | 2014-07-03 | 2014-10-22 | 扬州虹扬科技发展有限公司 | Cutting technology processing method |
| CN107733389A (en) * | 2017-11-01 | 2018-02-23 | 应达利电子股份有限公司 | A kind of quartz crystal is large stretch of and manufactures the method for small chips using it |
| CN107733389B (en) * | 2017-11-01 | 2020-12-01 | 深圳市深汕特别合作区应达利电子科技有限公司 | Quartz crystal large wafer and method for manufacturing small wafer by using same |
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| CN102522329B (en) | 2014-03-12 |
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