CN102510452A

CN102510452A - Correlated three sampling circuits for CMOS (Complementary Metal-Oxide-Semiconductor Transistor) active pixel sensor

Info

Publication number: CN102510452A
Application number: CN2011103172082A
Authority: CN
Inventors: 邓若汉; 陈永平; 陈世军; 余金金; 王洪彬
Original assignee: Shanghai Institute of Technical Physics of CAS
Current assignee: Shanghai Institute of Technical Physics of CAS
Priority date: 2011-10-18
Filing date: 2011-10-18
Publication date: 2012-06-20

Abstract

The invention discloses correlated three sampling circuits for a CMOS (Complementary Metal-Oxide-Semiconductor Transistor) active pixel sensor, which relates to CMOS (Complementary Metal-Oxide-Semiconductor Transistor) active pixel sensor (APS) signal noise processing circuit design. Line degrees of the sensor adopt the correlated three sampling circuits, i.e. three line degree sampling hold circuits are sued for sampling and holding an output signal of a CMOS active pixel, so that two options for effectively inhibiting random noise in the pixel output signal under different working conditions, where one option is characterized in that: 'signal voltage' and 'reset voltage' of the pixel in the same frame are differentiated after being sampled and held, so that FPN (Fixed Pattern Noise) is eliminated and low frequency noise is inhibited; and the other option is characterized in that: 'signal voltage' of the pixel and 'reset voltage' of the next frame are differentiated after being sampled and held, so that FPN (Fixed Pattern Noise) is eliminated and low frequency noise is inhibited. The correlated three sampling circuits can provide different noise elimination schemes for different working conditions such as variation of integration time, and the noise can be better inhibited.

Description

A kind of relevant three sample circuits that are used for the CMOS CMOS active pixel sensor

Technical field

The present invention relates to CMOS CMOS active pixel sensor (APS) signal noise processing circuits; Be meant that specifically the ranks level circuit at CMOS-APS adopts a kind of relevant three sample circuits; Can under the different working condition, use different samplings to keep scheme, more effectively suppress the noise of CMOS-APS.

Background technology

Up to the present, the solid state image sensor that is used for visible light wave range mainly contains charge-coupled device (CCD) and complementary metal oxide semiconductors (CMOS) (CMOS) imageing sensor (CIS).Compare CCD, CIS is owing to have low cost, low-power consumption, be easy to and advantages such as other signal processing circuit is integrated, more and more widely be applied to various fields.Although the shortcoming that CIS also has himself as: compare CCD the noise and want big etc., these gaps are along with the progress of technology and upgrade also diminishing gradually of better circuit design, can estimate that following CIS will replace CCD in most of fields comprehensively.

The structure of CIS is generally formed (like Chinese patent, patent No. CN, 1835551A, on March 18th, 2005) by active pixel array, ranks signal processing circuit, chip-scale signal processing circuit and sequential drive circuit.Owing to compare CCD, noise is the main shortcoming of CIS always, so noise problem also is the problem that all CIS devices need be faced jointly always.And wherein CIS active pixel circuit is as the first order of whole C IS circuit, and its noise is the most important source of whole C IS output noise.General way is to adopt correlated-double-sampling (CDS) method that the output noise of pixel is eliminated and suppress (like Chinese patent, patent No. CN, 1835551A, on March 18th, 2005) in the ranks level.In the CDS method; Produce resetting voltage and signal voltage from a pixel of APS array; Resetting voltage that samples and signal voltage are done difference with regard to the detected light intensity of represent pixel; And do at these two signals and can eliminate fixed pattern noise (FPN) and low-frequency noise simultaneously when poor, improved the signal to noise ratio of CIS thus.Here, " resetting voltage " refers generally to APS and reads the voltage that is produced when before photogenerated charge memory node electric capacity being resetted at signal voltage, and " signal voltage " refers to the voltage that APS is produced when signal is sampled.

Yet; In CMOS-APS 3T structure; CDS can reduce with the growth of the time of integration the inhibition effect of low-frequency noise, this be because the degree of correlation of the low-frequency noise in " resetting voltage " and " signal voltage " these two voltages can be in time the interval increase and reduce.Therefore as far as the 3T structure C MOS-APS of long-time integration mode of operation, the noise suppression effect of CDS can reduce greatly.

Summary of the invention

The purpose of this invention is to provide a kind of ranks noise difference dividing circuit, the problem of noise suppression effect variation of the CDS method of the 3T structure C MOS-APS that exists in the solution prior art with the growth of the time of integration.

In order to achieve the above object, the present invention adopts a kind of noise suppressing method of relevant three samplings to replace correlated double sampling circuit.Described relevant three sample circuits comprise: sampling reset signal switch and corresponding electric capacity and the logical buffer circuits (Buffer) of column selection of keeping; Sampled light signaling switch and corresponding electric capacity and the logical buffer circuits (Buffer) of column selection of keeping, the reset signal switch of sampling next frame and corresponding electric capacity and the logical buffer circuits (Buffer) of column selection of keeping.

Concrete way is that relevant three sample circuits have adopted three sampling hold circuits, can store " signal voltage " and this frame and back " resetting voltage " of a frame after the pixel integration simultaneously.Like this noise is differed from except that the time, two kinds of selections can be arranged: the time of integration more in short-term, adopt " signal voltage " and " resetting voltage " of same frame to do difference and remove; In the time of integration when longer, adopt " resetting voltage " of " signal voltage " and next frame to do to differ from and remove.Noise suppression effect when getting well of doing like this is in long integration is better than the correlated-double-sampling method.

Great advantage of the present invention is: need not change technology and not increase basically under the prerequisite of complexity of CIS circuit system; Directly on the basis of ranks CDS, increase a sampling hold circuit and just can realize, have advantage such as need not change technology, circuit design is simple and noise suppression effect is better.

Description of drawings

Fig. 1 is the block diagram of CMOS CMOS active pixel sensor.

Fig. 2 is the circuit block diagram of the general correlated-double-sampling of prior art.

Fig. 3 is the circuit diagram of relevant three sampling (CTS) methods of proposing of the present invention.

Fig. 4 is the sequential chart that has adopted the CMOS CMOS active pixel sensor of relevant three samplings (CTS).

Embodiment

Below in conjunction with accompanying drawing, specific embodiments of the invention is done further to specify:

As shown in Figure 2, relevant three sample circuits by three separately independently sampling hold circuit constitute.Every sampling hold circuit comprises a switch, an electric capacity and an output Buffer.Switch opening and closing by periodic clock control, is controlling charging and the maintenance process of row pixel bus to electric capacity.The ON time of three switches successively differs, and the readout time of " resetting voltage " of respectively corresponding " resetting voltage ", " signal voltage " and next frame, after accomplishing capacitor charging separately, successively breaks off separately.Output Buffer also controls conducting and disconnection by cycle clock; After the sampling capacitance charging is accomplished; Buffer is by the clock control conducting in output, and these three voltage signals export back level signal processing circuit simultaneously to, accomplishes that the noise difference is removed and process such as signal amplification.

Operation principle: shown in Fig. 3 circuit sequence sketch map, after a pixel of each row resets, the switch Ф of relevant three samplings ₁At first conducting, switch Ф after the regular hour ₁Break off, at this moment capacitor C _SH1Charging is accomplished, and charge stored is Q ₁, then " resetting voltage " of storage this moment is: V _Reset=Q ₁/ C _SH1Behind integration after a while, switch Ф ₂Conducting, switch Ф after the regular hour ₂Break off, at this moment capacitor C _SH2Charging is accomplished, and charge stored is Q ₂, then " signal voltage " of storage this moment is: V _Sig=Q ₂/ C _SH2Again this pixel is resetted switch Ф subsequently ₃Conducting, switch Ф after the regular hour ₃Break off, at this moment capacitor C _SH3Charging is accomplished, and charge stored is Q ₃, then " resetting voltage " of storage this moment is: V ^* _Reset=Q ₃/ C _SH3Wherein, the equal and opposite in direction of three electric capacity has C _SH1=C _SH2=C _SH3=C _SH, then the cts signal difference is removed and can be used V _Reset-V _SigOr V ^* _Reset-V _SigExpression when short time integral, generally can be adopted V _Reset-V _Sig, and during long time integral, then should adopt V ^* _Reset-V _SigV is adopted in above-mentioned selection for noise suppression effect is carried out in addition ^* _Reset-V _SigAlso can improve frame frequency.

Claims

1. relevant three sample circuits that are used for the CMOS CMOS active pixel sensor is characterized in that this circuit has the sampling hold circuit that contains a switch, an electric capacity and an output buffer of three same structures; Described three sampling hold circuits are respectively opened and cut-off switch sample maintenance " resetting voltage " or " signal voltage " by own periodic; At the detected light intensity of remarked pixel and carry out the noise difference when removing; According to the transducer difference of the time of integration, select to carry out that the noise difference is removed or carry out the noise difference with " signal voltage " of " resetting voltage " of next frame and this frame and remove the noise that suppresses the CMOS CMOS active pixel sensor with " resetting voltage " of same frame and " signal voltage ".