CN102497163A - Field programmable gate array (FPGA)-based closed loop voltage controlled oscillator (VCO) linearity correction method - Google Patents
Field programmable gate array (FPGA)-based closed loop voltage controlled oscillator (VCO) linearity correction method Download PDFInfo
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Abstract
The invention relates to a field programmable gate array (FPGA)-based closed loop voltage controlled oscillator (VCO) linearity correction method, which comprises voltage control word output, voltage-controlled frequency generation, frequency measurement, voltage control word searching and storage. By the method, the linearity of a VCO can be effectively corrected; the method is high in real-time performance, timely, reliable, high in universality and accurate in linearity correction; and the problem of limitation of the conventional VCO linearity correction is solved.
Description
Technical field
The present invention relates to a kind of VCO linearity correction method, especially a kind of closed loop VCO linearity correction method based on FPGA belongs to signal processing and system control technology field.
Background technology
Millimetric wave voltage-controlled oscillator (VCO) is the adjustable signal source of a kind of frequency of oscillation with the control change in voltage, is widely used in the radar system, particularly linear frequency modulation continuous wave radar (LFMCW).VCO will determine the performance of whole LFMCW radar system as core parts.Yet receive electricity to transfer the influence of high steady and broadband contradiction in element variable capacitance diode intrinsic tuning non-linear and the oscillator structure; The output of the radio frequency of VCO produces the non-linear and power fluctuation of frequency sweep in the frequency sweep process, the fm linearity of himself generally can only reach 2% one 5%.In order to improve the overall performance of LFMCW radar system, must carry out the frequency sweep gamma correction to VCO.The VCO linearity correction is as one of key technology of fmcw radar; Many in the world countries are all in the research of carrying out this respect; And the exploitation, produce some practical linearity correction systems, the whole bag of tricks has been proposed, can be divided into three major types on the whole: one, reactance compensation linearity correction method; Two, open loop linearity correction method; Three, closed loop linearity correction method.It below is the comparison of several kinds of linearity correction methods
| Bearing calibration | Linearity situation | Debugging difficulty | Cost of manufacture |
| The reactance compensation method | Difference | Difficult | Low |
| The open loop correction method | Difference | Be prone to | Lower |
| The frequency discrimination comparison method | Better | Generally | Generally |
| The closed-loop simulation correction method | Good | Difficult | Generally |
| The closed-loop digital correction method | Very good | Difficult | High |
But above-mentioned bearing calibration has following defective: reliability is not high, versatility is poor, and the linearity correction precision is low, and environmental suitability is poor, and particularly when proofreading and correct the linearity of swept-frequency signal, it is low to proofread and correct efficient.
Can for this reason, design a kind of VCO linearity correction method, have the reliability height, versatility is good, the linearity correction precision be high, and characteristics such as good environmental adaptability improve the linearity correction efficient of swept-frequency signal simultaneously, are the technical barriers that this area faces.
Summary of the invention
The purpose of this invention is to provide a kind of simply, efficient, general, can be widely used in the method for VCO linearity correction, this bearing calibration comprises the steps:
NIOS among the 1FPGA sends voltage control word VCTRL through the DA interface module to digital to analog converter DAC;
2 digital to analog converter DAC convert control word VCTRL into corresponding electric current;
3 amplifying circuits are voltage with current conversion, and magnitude of voltage is amplified, and are designated as vturn;
Its output signal frequency of voltage vturn control of 4 voltage controlled oscillator VCO utilizations input;
5 voltage controlled oscillator VCO output signal frequency form fractional frequency signal FDIV through frequency division, frequency range at 100MHZ between the 200MHZ;
The frequency measurement module of 6 fractional frequency signal FDIV input FPGA, the frequency of measurement input signal;
NIOS among the 7FPGA reads the frequency values that the frequency measurement module records; Relative error between the frequency values that the NIOS judgement obtains and the frequency values of expection is in 0.1%; If relative error is greater than 0.1%, then repeat 1 to 6 step, up to relative error in 0.1%; The voltage control word of this moment is stored in the ram in slice, so far accomplish the voltage correction of a frequency of VCO.
Preferably, frequency division is 20 times a frequency division.
Preferably, the scope of voltage amplification be-10V is to+10V.
Preferably, also has filter step between step 3) and the step 4).
Preferably, use hardware language VerilogHDL in the frequency measurement module.
The invention also discloses a kind of closed loop VCO swept-frequency signal linearity correction method, concrete bearing calibration following steps based on FPGA:
1) according to the M that counts of voltage controlled oscillator VCO frequency range and needs correction, calculates preset value of frequency point array F, and this storage of array is arrived in the ROM file, supply PFGA to use;
2) FPGA reads m value F [m] in the preset value of frequency point array, carries out the trimming process of m frequency;
3) as if m=0, then FPGA sends initial D/A voltage control word V_turn [0], makes that the D/A output voltage is 0V, if m does not wait 0, then FPGA sends the correction voltage value V [m-1] that initial D/A voltage control word V_turn [0] equals m-1 preset frequency;
4) FPGA frequency measurement module is measured the frequency measurement f_check [i] of the fractional frequency signal of voltage controlled oscillator VCO feedback; If f_check [i] is less than the preset value of frequency point F [m] of m frequency; Then voltage control word V_turn adds up, i.e. V_turn [i+1]=V_turn [i]+1, and V_turn [i+1] sent to digital to analog converter DAC; FPGA surveys the frequency measurement f_check [i+1] that module is measured the fractional frequency signal of voltage controlled oscillator VCO feedback once more frequently, until f_check [i+1]＞=F [m]; If | f_check [i]-F [m] |＜| f_check [i+1]-F [m] |; The VCO output frequency of then representing magnitude of voltage V_turn [i] representative is more near preset value of frequency point F [m]; V_turn [i] is stored in the ram in slice, otherwise the VCO output frequency of magnitude of voltage V_turn [i+1] representative is more near preset value of frequency point F [m]; And V_turn [i+1] stored in the ram in slice, so far accomplish the correction of m frequency;
5) m adds up, and goes on foot from the 2nd to repeat, and the correction until accomplishing the preset value of frequency point of M point obtains M point voltage value, and is stored in the ram in slice.
In the frequency measurement module, use VerilogHDL to write the frequency measurement algorithm.
The invention has the beneficial effects as follows: through experimental verification, this method can effectively be proofreaied and correct the linearity of VCO, and real-time is high, timely reliably, versatility is high, and linearity correction is accurate, has solved many limitation problems that present VCO linearity correction exists.
Description of drawings
Fig. 1 is the flow chart that carries out the single-frequency point calibration based on the closed loop VCO linearity correction method of FPGA of the present invention;
Fig. 2 is that the closed loop VCO linearity correction method based on FPGA of invention is carried out the flow chart flow chart that multifrequency point is proofreaied and correct;
Fig. 3 is the frequency measurement schematic diagram of frequency measurement module among the present invention;
Fig. 4 is a VCO voltage-frequency performance plot.
Embodiment
Inventive principle
VCO frequency sweep gamma correction technology is one of key technology that realizes high accuracy and the linear frequency modulated continuous wave radar of high-resolution, studies more being based at present and postpones a phase demodulation method, and it is the closed-loop digital bearing calibration of core with the digital processing system.Its operation principle is: the difference frequency signal to mixing output carries out accurate Calculation by the digital signal processor by using algorithm to phase place after the A/D sampling; Thereby obtain the frequency shift (FS) function; And then can draw the control voltage of following one-period; After the D/A conversion, remove to control VCO again, constantly repeat this process and realize making the VCO output waveform near the ideal linearity FM signal the VCO linearity correction.The core of closed-loop digital corrective system is the digital processing system principle, considers from accuracy, and closed-loop digital corrective system perfect along with the raising of sample rate and algorithm in theory, the linearity can be improved greatly.But problem also produces thus, and the raising of sampling number can cause the increase of data volume, and the workload of digital signal processor strengthens, particularly if complex algorithm with the speed that influences system, adopts high speed device will make the cost of system improve simultaneously.
Inventor of the present invention is through big quantity research, and combined digital signal is handled, and has found following technical characterstic.VCO voltage-frequency performance plot is as shown in Figure 4.
Can know that by Fig. 4 the VCO voltage-frequency curve has two tangible characteristics: the one, it can change with the temperature of circuit board, and the 2nd, the low-voltage part of VCO voltage-frequency curve is linear basically, distortion has then taken place in the high voltage part.If be divided into the individual frequency F of M (m=0:M-1) [m] to whole VCO frequency range, each frequency correspondence magnitude of voltage be V [m], as long as find each frequency corresponding voltage value just can proofread and correct to the linearity of VCO.The signal of VCO output is a millimeter wave, and signal frequency is distributed in.To directly carry out very difficulty of time domain or frequency-domain analysis to this signal.If give VCO one fixed voltage V_turn, then its output signal is a single-frequency, and establishing its frequency is W.If this simple signal is carried out N times of frequency division, can obtain the lower signal of frequency.Low frequency signal can use the algorithm of Digital Signal Processing that it is carried out frequency measurement, and the frequency values that obtains is made as F, so the output frequency W=N*F of VCO.Use the method can measure the frequency of VCO easily.According to the frequency values W that obtains, adjust the frequency F [m] that V_turn makes that W equals to preset repeatedly, the VCO frequency that this voltage V_turn is corresponding so is F [m], and this voltage V_turn is stored among the V [m].With the method each frequency is proofreaied and correct, obtained M magnitude of voltage, thereby realize the linearity correction of VCO.
The present invention utilizes this technical characterstic, and a kind of new closed loop VCO linearity correction method based on FPGA is provided, and is the major control device with FPGA; Be aided with peripheral ball bearing made using; Realization is to efficient, the high-precision correction of VCO, and the method reliability is high, versatility is good, and the linearity correction precision is high; Good environmental adaptability, the efficient of swept-frequency signal linearity correction is high simultaneously.
Below in conjunction with accompanying drawing and embodiment the closed loop VCO linearity correction method of inventing is described in detail.
As shown in Figure 1, bearing calibration comprises the steps:
NIOS among the 1FPGA sends voltage control word VCTRL through the DA interface module to digital to analog converter DAC;
2 digital to analog converter DAC convert control word VCTRL into corresponding electric current;
3 amplifying circuits are voltage with current conversion, and magnitude of voltage is amplified to-10v is between+the 10V, is designated as vturn;
Its output signal frequency of voltage vturn control of 4 voltage controlled oscillator VCO utilizations input;
5 voltage controlled oscillator VCO output signal frequency form fractional frequency signal FDIV through 20 times frequency division, frequency range at 100MHZ between the 200MHZ;
The frequency measurement module of 6 fractional frequency signal FDIV input FPGA, the frequency of measurement input signal;
NIOS among the 7FPGA reads the frequency values that the frequency measurement module records; Relative error between the frequency values that the NIOS judgement obtains and the frequency values of expection is in 0.1%; If relative error is greater than 0.1%, then repeat 1 to 6 step, up to relative error in 0.1%; The voltage control word of this moment is stored in the ram in slice, so far accomplish the voltage correction of a frequency of VCO.
When proofreading and correct the whole frequency range of VCO; Only need the frequency range of VCO is divided into N frequency; Adopt above step that each frequency is proofreaied and correct, obtain the voltage control word of N some this moment, they are stored in the ram in slice; Read according to certain time sequence as required and send, be i.e. may command VCO output signal frequency.Concrete bearing calibration following steps:
1) according to the M that counts of voltage controlled oscillator VCO frequency range and needs correction, calculate M discrete value of frequency point to be corrected, form preset frequency array F, and this storage of array is arrived in the ROM file, supply PFGA to use;
2) FPGA reads m value F [m] in the preset frequency array F, and F [m] is m frequency to be corrected, carries out the trimming process of m frequency to be corrected, and m is the natural number between 1 to M;
3) carry out timing DA voltage control word initial value selected of m frequency to be corrected: if m=1, then the initial voltage control word adopts predetermined voltage control word (V_turn [0]), and this control word makes that digital to analog converter DAC output current is 0, i.e. output voltage 0V; If m is not equal to 1, then its initial voltage control word is selected the correction voltage value (V [m-1]) of m-1 preset frequency;
4) correction of m frequency of execution comprises the steps:
4.1) NIOS among the FPGA sends initial voltage control word VCTRL through the DA interface module to digital to analog converter DAC;
4.2) digital to analog converter DAC converts control word VCTRL into corresponding electric current;
4.3) amplifying circuit is voltage with current conversion, and magnitude of voltage is amplified to-10v is between+the 10V, is designated as vturn;
4.4) its output signal frequency of voltage vturn control of voltage controlled oscillator VCO utilization input;
4.5) the voltage controlled oscillator VCO output signal frequency is through 20 times frequency division, forms fractional frequency signal FDIV, frequency range at 100MHZ between the 200MHZ;
4.6) the frequency measurement module of fractional frequency signal FDIV input FPGA, measure the frequency of input signal;
4.7) the frequency measurement module measures the frequency measurement (f_check [i]) of the fractional frequency signal of voltage controlled oscillator VCO feedback; If the frequency values (f_check [i]) that records is less than the preset value of frequency point F [m] of m frequency; Then voltage control word (V_turn) adds up; Be V_turn [i+1]=V_turn [i]+1; And the voltage control word after will adding up (V_turn [i+1]) sends to digital to analog converter DAC, and the frequency measurement module is measured the frequency measurement (f_check [i+1]) of the fractional frequency signal of voltage controlled oscillator VCO feedback once more, until the preset value of frequency point (f_check [i+1]＞=F [m]) of the frequency values that records more than or equal to m frequency; Frequency values that records before and after relatively adding up this moment and the frequency-splitting between the preset value of frequency point F [m]; If | f_check [i]-F [m] |＜| f_check [i+1]-F [m] |; The VCO output frequency of voltage control word V_turn [i] representative before then expression this time adds up is more near preset value of frequency point F [m]; V_turn [i] is stored in the ram in slice, otherwise the VCO output frequency of voltage control word V_turn [i+1] representative after this adds up is more near preset value of frequency point F [m]; And V_turn [i+1] stored in the ram in slice, so far accomplish the correction of m frequency;
5) m+1 repeated from the 2nd step, preset the correction of value of frequency point until accomplishing M point, obtained M voltage control word, and was stored in the ram in slice.
In carrying out swept-frequency signal linearity correction process, the 3rd) go on foot the initial voltage control word that adopts the voltage control word after last frequency is proofreaied and correct to proofread and correct as current frequency, shortened the correction time of this frequency, improved correction efficient; In (7) step trimming process, promptly stop trimming process as long as record frequency values greater than preset value of frequency point, shortened the correction time of this frequency equally, improved correction efficient.
In the frequency measurement module, use VerilogHDL to write the frequency measurement algorithm, accomplish the frequency measurement to fractional frequency signal, the frequency measurement principle is as shown in Figure 3.
Being located at once counter among actual gate time of the t is N to the count value of measured signal
X, be N to the count value of standard signal
S, the standard signal frequency is f
s, the frequency of measured signal then
In measuring process, there are two counters respectively standard and measured signal to be counted simultaneously.At first providing gate opening signal (presetting the gate rising edge). this hour counter does not begin counting, but the rising edge of measured signal by the time is when arriving, and counter just really begins counting.Preset closing gate signal (trailing edge) then then, counter does not stop counting immediately, but the rising edge of measured signal by the time just finishes counting when arriving, and accomplishes the one-shot measurement process. can find out, actual gate time t and preset tr gate time.Not strict equating, but difference can not surpass measured signal-individual cycle.Being located at once counter among actual gate time of the t is N to the count value of measured signal
X, be N to the count value of standard signal
S, the standard signal frequency is f
s, then the frequency of measured signal does
Through verification experimental verification, the closed loop VCO linearity correction method based on the FPGA cooperative work of software and hardware of the present invention is very accurately reliable, and the linearity after the correction is 0.3%.
Above embodiment is merely the usefulness of setting forth the present invention, and it does not represent the qualification to protection range of the present invention, and any modification, improvement of doing based on inventive concept is all within protection range of the present invention.
Claims (7)
1. the closed loop VCO linearity correction method based on FPGA is characterized in that, comprises the steps:
1) NIOS among the FPGA sends voltage control word VCTRL through the DA interface module to digital to analog converter DAC;
2) digital to analog converter DAC converts control word VCTRL into corresponding electric current;
3) amplifying circuit is a voltage with current conversion, and magnitude of voltage is amplified, and is designated as vturn;
4) its output signal frequency of voltage vturn control of voltage controlled oscillator VCO utilization input;
5) the voltage controlled oscillator VCO output signal frequency forms fractional frequency signal FDIV through frequency division, frequency range at 100MHZ between the 200MHZ;
6) the frequency measurement module of fractional frequency signal FDIV input FPGA, the frequency of measurement input signal;
7) NIOS among the FPGA reads the frequency values that the frequency measurement module records; Relative error between the frequency values that the NIOS judgement obtains and the frequency values of expection is in 0.1%; If relative error is greater than 0.1%, then repeat 1 to 6 step, up to relative error in 0.1%; The voltage control word of this moment is stored in the ram in slice, so far accomplish the voltage correction of a frequency of VCO.
2. according to a kind of closed loop VCO linearity correction method of claim 1, it is characterized in that said frequency division is 20 times a frequency division based on FPGA.
3. according to a kind of closed loop VCO linearity correction method of claim 1, it is characterized in that based on FPGA, in the said step 3), the scope of voltage amplification is-10V is to+10V.
4. according to a kind of closed loop VCO linearity correction method of claim 1, it is characterized in that also having filter step between said step 3) and the step 4) based on FPGA.
5. according to a kind of closed loop VCO linearity correction method of claim 1, it is characterized in that, use hardware language VerilogHDL in the said frequency measurement module based on FPGA.
6. closed loop VCO swept-frequency signal linearity correction method based on FPGA is characterized in that following steps:
1) according to the M that counts of voltage controlled oscillator VCO frequency range and needs correction, calculate M discrete value of frequency point to be corrected, form preset frequency array F, and this storage of array is arrived in the ROM file, supply PFGA to use;
2) FPGA reads m value F [m] in the preset frequency array F, and F [m] is m frequency to be corrected, carries out the trimming process of m frequency to be corrected, and m is the natural number between 1 to M;
3) carry out timing DA voltage control word initial value selected of m frequency to be corrected:
If m=1, then the initial voltage control word adopts predetermined voltage control word (V_turn [0]), and this control word makes that digital to analog converter DAC output current is 0, i.e. output voltage 0V; If m is not equal to 1, then its initial voltage control word is selected the correction voltage value (V [m-1]) of m-1 preset frequency;
4) correction of m frequency of execution comprises the steps:
4.1) NIOS among the FPGA sends initial voltage control word VCTRL through the DA interface module to digital to analog converter DAC;
4.2) digital to analog converter DAC converts control word VCTRL into corresponding electric current;
4.3) amplifying circuit is voltage with current conversion, and magnitude of voltage is amplified to-10v is between+the 10V, is designated as vturn;
4.4) its output signal frequency of voltage vturn control of voltage controlled oscillator VCO utilization input;
4.5) the voltage controlled oscillator VCO output signal frequency is through 20 times frequency division, forms fractional frequency signal FDIV, frequency range at 100MHZ between the 200MHZ;
4.6) the frequency measurement module of fractional frequency signal FDIV input FPGA, measure the frequency of input signal;
4.7) the frequency measurement module measures the frequency measurement (f_check [i]) of the fractional frequency signal of voltage controlled oscillator VCO feedback; If the frequency values (f_check [i]) that records is less than the preset value of frequency point F [m] of m frequency; Then voltage control word (V_turn) adds up; Be V_turn [i+1]=V_turn [i]+1; And the voltage control word after will adding up (V_turn [i+1]) sends to digital to analog converter DAC, and the frequency measurement module is measured the frequency measurement (f_check [i+1]) of the fractional frequency signal of voltage controlled oscillator VCO feedback once more, until the preset value of frequency point (f_check [i+1]＞=F [m]) of the frequency values that records more than or equal to m frequency; Frequency values that records before and after relatively adding up this moment and the frequency-splitting between the preset value of frequency point F [m]; If | f_check [i]-F [m] |＜| f_check [i+1]-F [m] |; The VCO output frequency of voltage control word V_turn [i] representative before then expression this time adds up is more near preset value of frequency point F [m]; V_turn [i] is stored in the ram in slice, otherwise the VCO output frequency of voltage control word V_turn [i+1] representative after this adds up is more near preset value of frequency point F [m]; And V_turn [i+1] stored in the ram in slice, so far accomplish the correction of m frequency;
5) m+1 repeated from the 2nd step, preset the correction of value of frequency point until accomplishing M point, obtained M voltage control word, and was stored in the ram in slice.
7. according to a kind of closed loop VCO swept-frequency signal linearity correction method of claim 6, it is characterized in that, use hardware language VerilogHDL in the said frequency measurement module based on FPGA.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104601903A (en) * | 2014-12-23 | 2015-05-06 | 深圳市思乐数据技术有限公司 | Video signal converting method and circuit |
| CN109581376A (en) * | 2018-12-26 | 2019-04-05 | 北京遥测技术研究所 | A kind of VCO frequency sweep non-linear correction method for safety check imaging |
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| US20080061891A1 (en) * | 2006-09-12 | 2008-03-13 | Fujitsu Limited | Phase-locked oscillator and multi-radar system using same |
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| CN104601903A (en) * | 2014-12-23 | 2015-05-06 | 深圳市思乐数据技术有限公司 | Video signal converting method and circuit |
| CN104601903B (en) * | 2014-12-23 | 2018-03-06 | 深圳市思乐数据技术有限公司 | A kind of video signal conversion method and circuit |
| CN109581376A (en) * | 2018-12-26 | 2019-04-05 | 北京遥测技术研究所 | A kind of VCO frequency sweep non-linear correction method for safety check imaging |
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Effective date of registration: 20190903 Address after: 100013 Beijing City, Dongcheng District Hepingli No. 3 South Street Patentee after: Beijing Huahang Haiying New Technology Development Co.,Ltd. Address before: 100013 Beijing City, Dongcheng District Hepingli No. 3 South Street Patentee before: Beijing Huahang Radio Measurement Research Institute |