CN102496603A - Chip level packaging structure - Google Patents
Chip level packaging structure Download PDFInfo
- Publication number
- CN102496603A CN102496603A CN2011104283805A CN201110428380A CN102496603A CN 102496603 A CN102496603 A CN 102496603A CN 2011104283805 A CN2011104283805 A CN 2011104283805A CN 201110428380 A CN201110428380 A CN 201110428380A CN 102496603 A CN102496603 A CN 102496603A
- Authority
- CN
- China
- Prior art keywords
- layer
- chip
- packaging structure
- metal
- grade packaging
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/1147—Manufacturing methods using a lift-off mask
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/118—Post-treatment of the bump connector
- H01L2224/11848—Thermal treatments, e.g. annealing, controlled cooling
- H01L2224/11849—Reflowing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/119—Methods of manufacturing bump connectors involving a specific sequence of method steps
- H01L2224/11912—Methods of manufacturing bump connectors involving a specific sequence of method steps the bump being used as a mask for patterning other parts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
The invention discloses a chip level packaging structure which comprises a chip, a bump lower metal layer and a solder bump, wherein a bonding pad and a passivation layer are arranged on the chip; the passivation layer surrounds the periphery of the bonding pad; the bump lower metal layer is positioned on the bonding pad; the solder bump is positioned on the bump lower metal layer; and the bump lower metal layer comprises a heat-resistant metal layer, a metal infiltration layer, a blocking layer and a solder protection layer which are positioned on the chip bonding pad in turn from bottom to top. According to the invention, the electrical performance and reliability of a product are improved.
Description
Technical field
The present invention relates to the semiconductor packages field, relate in particular to ubm layer, chip-scale encapsulation (Wafer Level chip Scale Package, encapsulating structure WLCSP).
Background technology
In recent years, because the microcircuit of chip is made towards the high integration development, therefore, its Chip Packaging also needs to develop to high power, high density, direction frivolous and microminiaturization.Chip Packaging is exactly after chip manufacturing is accomplished, with materials such as plastic cement or Tao Ci, chip to be wrapped in wherein, to reach the protection chip, makes chip not damaged by extraneous steam and mechanicalness.The main function of Chip Packaging has electric energy to transmit (Power Distribution) respectively, signal transmits (Signal Distribution), heat abstraction (Heat Dissipation) and protection support (Protection and Support).
Because the requirement of electronic product now is compact and high integration, therefore can makes and the production of integrated circuits miniaturization cause the logic that comprises in the chip to increase; And further make chip I/O (input/output) pin number increase; And be to cooperate these demands, produced many different packaged types, for example; BGA Package (Ball grid array; BGA), chip size packages (Chip Scale Package, CSP), multi-chip module encapsulation (Multi Chip Module package, MCM package), flip-over type encapsulation (Flip Chip Package), coil type encapsulation (Tape Carrier Package; TCP) and wafer-level packaging (Wafer Level Package, WLP) etc.
No matter with the method for packing of which kind of form, most method for packing all is wafer separate to be become independently accomplish the program that encapsulates again behind the chip.And wafer-level packaging is a trend in the method for packaging semiconductor; Wafer-level packaging is an encapsulated object with the full wafer wafer; Thereby packaging and testing all need in the not preceding completion of cutting crystal wafer as yet; Be the encapsulation technology that a kind of height is integrated, so can save making such as filler, assembling, glutinous crystalline substance and routing, therefore can reduce cost of labor in a large number and shorten manufacturing time.
Application number is that 200410049093.3 Chinese patent has been introduced a kind of chip grade packaging structure.Figure 1A to Fig. 1 F is existing solder bump forming process sketch map.Shown in Figure 1A, form one deck passivation layer 106 on the substrate 102 of pad 104.Then, deposit one deck heat resistant metal layer 108 (being generally chromium Cr or titanium Ti) and metal infiltrating layer 110 (being generally copper Cu) in succession on pad 104 and passivation layer 106 surfaces are shown in Figure 1B.Be coated with photoresist 112 and patterning photoresist then forming groove 114, shown in Fig. 1 C with the pad relevant position.Then, shown in Fig. 1 D, packing material is the scolder of tin (Sn) or tin silver (SnAg) in groove 114, just formed the mushroom-shaped solder bump 120 shown in Fig. 1 E after removing photoresist 112.Etching heat resistant metal layer 108 and metal infiltrating layer 110 melt the spherical solder salient point 120 shown in Fig. 1 F through the termination electrode reflux technique with solder bump at last afterwards.
Prior art forms in the wafer-level package process, because the solder bump material directly contacts with metal infiltrating layer, the copper-base of metal infiltrating layer is prone to be diffused in the tin of solder bump and forms signal bronze, influences welding quality.In addition, before forming scolder on the metal infiltrating layer, the exposed easy oxidation of soakage layer and the solder bump performance of follow-up formation and reliability are reduced.
Summary of the invention
The problem that the present invention solves provides a kind of chip grade packaging structure, prevents that chip electrical property and reliability from reducing.
For addressing the above problem; The present invention provides a kind of chip grade packaging structure; Comprise: chip, ubm layer and solder bump, said chip is provided with pad and passivation layer, said passivation layer be centered around said pad around; Said ubm layer is positioned on the said pad, and said solder bump is positioned on the said ubm layer; Said ubm layer comprises heat resistant metal layer, metal infiltrating layer, barrier layer and the scolder protective layer that from bottom to top is positioned at the chip bonding pad top successively.
Alternatively, the material of said heat resistant metal layer is a titanium.
Alternatively, the material of said heat resistant metal layer is titanium, chromium, tantalum or their combination.
Alternatively, the material of said metal infiltrating layer is a copper.
Alternatively, the material of said metal infiltrating layer is copper, aluminium, nickel or their combination.
Alternatively, the material on said barrier layer is a nickel.
Alternatively, the thickness on said nickel barrier layer is 1.5～3 μ m.
Alternatively, said scolder protective layer is pure tin or ashbury metal.
Alternatively, the thickness of said scolder protective layer is 1～2 μ m.
Alternatively, the material of said solder cream is consistent with the material of scolder protective layer.
Compared with prior art; In the ubm layer that the present invention forms; Can avoid self disappearing because of diffusion effect on the one hand in the suitable barrier layer (Ni) of thickness, and then the hole that stops between scolder and the metal infiltrating layer formation because of intermetallic compound to produce effectively; Be unlikely to simultaneously to cause resistivity to rise again and influence the electric heating property of product because of the nickel barrier layer is blocked up.
In addition, the scolder protective layer in the ubm layer not only can protect the barrier layer not oxidized; Also improved the adhesive force between barrier layer and solder bump; And in reflux course, the scolder protective layer has good humidifying effect, has improved the formation quality of solder bump.
Description of drawings
Figure 1A to Fig. 1 F is existing solder bump forming process sketch map;
Fig. 2 is the sketch map of chip grade packaging structure of the present invention;
Fig. 3 is the embodiment flow chart that the present invention forms chip grade packaging structure
Fig. 4 A to Fig. 4 G is the process schematic representation that the present invention forms the embodiment of chip grade packaging structure.
Embodiment
Do detailed explanation below in conjunction with the accompanying drawing specific embodiments of the invention.
Fig. 2 is the sketch map of chip grade packaging structure of the present invention; Said encapsulating structure comprises: chip 300, ubm layer and solder bump 309; Said chip 300 is provided with pad 301 and passivation layer 302; Said passivation layer 302 be centered around said pad 301 around; Said ubm layer is positioned on the said pad 301, and said solder bump 309 is positioned on the said ubm layer, it is characterized in that: said ubm layer comprises heat resistant metal layer 303, metal infiltrating layer 304, barrier layer 306 and the scolder protective layer 307 that from bottom to top is positioned at chip 300 pads 301 tops successively; The material of said heat resistant metal layer 303 is titanium, chromium, tantalum or their combination; The material of said metal infiltrating layer 304 is copper, aluminium, nickel or their combination; The material on said barrier layer 306 is the nickel metal of thickness 1.5 μ m～3 μ m; The material of said scolder protective layer 307 is pure tin or the ashbury metal of thickness 1 μ m～2 μ m, like sn-ag alloy, gun-metal or SAC alloy etc.
In the above-mentioned encapsulating structure, can avoid self disappearing because of diffusion effect in the suitable barrier layer (Ni) of thickness, and then the hole that stops between scolder and the metal infiltrating layer formation because of intermetallic compound to produce effectively; Be unlikely to simultaneously to cause resistivity to rise again and influence the electric heating property of product because of the nickel barrier layer is blocked up.The scolder protective layer that is positioned at the top, barrier layer then not only can protect the barrier layer not oxidized; Also improved the adhesive force between barrier layer and solder bump; And in reflux course, the scolder protective layer has good humidifying effect, has improved the formation quality of solder bump.
For further specifying the advantage of encapsulating structure of the present invention, encapsulating structure of the present invention is done further to introduce below in conjunction with a concrete method for packing embodiment.
As shown in Figure 3, in one embodiment of the invention, a kind of chip-scale packaging method is provided, comprise step:
S101 forms heat resistant metal layer and metal infiltrating layer successively on bonding pads and passivation layer;
S102 forms photoresist on metal infiltrating layer, said photoresist is provided with the metal infiltrating layer that opening exposes the chip bonding pad top;
S103 forms barrier layer and scolder protective layer successively on the metal infiltrating layer in above-mentioned opening;
S104 forms solder cream on the scolder protective layer;
S105 removes photoresist;
S106, heat resistant metal layer on the etch passivation layer and metal infiltrating layer to passivation layer is exposed;
S107, reflux solder cream forms solder bump.
In the present embodiment, at first execution in step S101 forms heat resistant metal layer and metal infiltrating layer successively on bonding pads and passivation layer, forms the structure shown in Fig. 4 A.
In this step, chip 300 is provided with pad 301 and passivation layer 302, and pad 301 is function lead-out terminals of chip 300, and finally realizes the conduction transition of electrical functionality through the solder bump 309 of follow-up formation; The material of passivation layer 302 comprises dielectric material or their mixtures such as silica, silicon nitride, silicon oxynitride, polyimides, benzene three polybutene, is used for protecting the circuit of chip 300.
In the present embodiment, the material of said heat resistant metal layer 303 can be constituting of titanium Ti, chromium Cr, tantalum Ta or they, and the present invention is preferably Ti.The material of said metal infiltrating layer 304 can be constituting of a kind of in copper Cu, aluminium Al, the nickel or they, and wherein more excellent metal infiltrating layer 304 is Cu.The method that forms said heat resistant metal layer 303 and metal infiltrating layer 304 can adopt the method for existing evaporation or sputter or physical vapour deposition (PVD) equally, and wherein more excellent method is sputter.Certainly; Common practise according to those skilled in the art; The method that forms is not limited only to sputtering method, and other methods that are suitable for all can be applicable to the present invention, and the thickness of heat resistant metal layer 303 that forms and metal infiltrating layer 304 also is to decide according to the process requirements of reality.
Implementation step S102 forms photoresist on metal infiltrating layer then, and said photoresist is provided with the metal infiltrating layer that opening exposes the chip bonding pad top, forms the structure shown in Fig. 4 B.
In the present embodiment, the method that forms photoresist 305 can be a rotary coating, and the concrete steps of these methods are well known to those skilled in the art, repeat no more at this.After forming photoresist 305, specifically can define the shape of pad 301, make to form opening in the photoresist 305 to expose the metal infiltrating layer 304 on the pad 301 through existing photoetching development technology.
Implementation step S103 forms barrier layer and scolder protective layer successively on the metal infiltrating layer in above-mentioned opening then, forms the structure shown in Fig. 4 C.
In this step; With remaining photoresist 305 on the chip 300 is mask; In the opening of the photoresist 305 that in last step, formed, metal infiltrating layer 304 above, form barrier layer 306, scolder protective layer 307 successively, concrete technology can be through with the mode of electroplating.Certainly, according to those skilled in the art's common practise, the method for formation is not limited only to electroplate, and other methods that are suitable for all can be applicable to the present invention.The material on said barrier layer 306 is a nickel, and the material of said scolder protective layer 307 is consistent with follow-up formation solder bump 309, is pure tin or ashbury metal, like sn-ag alloy, gun-metal, SAC alloy etc.
In the present embodiment, the thickness of barrier layer 306 nickel is 1.5 μ m～3 μ m, and concrete thickness is 1.5 μ m, 2 μ m, 2.5 μ m or 3 μ m etc.Acting as in diffuse to the metal infiltrating layer 304 that prevents follow-up formation salient point of barrier layer 306; When Ni layer thickness during less than 1.5 μ m; Ni finally can disappear because of the diffusion effect between adjacent metal, and then can't stop effectively that follow-up salient point is diffused in the metal infiltrating layer 304; When Ni layer thickness during, can cause the resistivity rising because of the electric heating property of Ni metal itself is relatively poor, and then influence the electric heating property of final products greater than 3 μ m.
In the present embodiment, the thickness of scolder protective layer 307 is 1 μ m～2 μ m, and concrete thickness is 1 μ m, 1.5 μ m or 2 μ m etc. for example.The effect of scolder protective layer 307 is to make the barrier layer 306 of its below not oxidized, has improved the electrical property and the reliability on barrier layer 306, and simultaneously, scolder protective layer 307 also has good humidifying effect, can effectively improve the formation quality of solder bump 309.
So far; That is to say; On pad 301, form the multiple layer metal layer; Comprise successively up that from the bottom heat resistant metal layer 303, metal infiltrating layer 304, barrier layer 306, scolder protective layer 307, these multiple layer metal layers have promptly constituted ubm layer UBM (the Under Bump Metallurgy) layer of being used to claim in the present technique field.
Implementation step S104 forms solder cream on the scolder protective layer then, forms the structure shown in Fig. 4 D.
In this step; Be mask with photoresist 305 still, on scolder protective layer 307, form solder cream 308, it is consistent with the material that forms scolder protective layer 307 to form said solder cream 308; Be pure tin or ashbury metal, like sn-ag alloy, gun-metal, SAC alloy etc.The method that forms solder cream 308 can be metallide, screen painting or directly implant prefabricated modes such as solder ball that the concrete steps of these methods are well known to those skilled in the art, repeat no more at this.
Then implementation step S105 removes photoresist, forms the structure shown in Fig. 4 E.
After accomplishing above-mentioned operation, photoresist 305 can have been removed, and can use wet method or the mode peeled off is removed, and the concrete steps of these methods are well known to those skilled in the art, repeat no more at this.
Implementation step S106 then, heat resistant metal layer on the etch passivation layer and metal infiltrating layer to passivation layer is exposed, forms the structure shown in Fig. 4 F.
In the present embodiment, specifically can remove the metal infiltrating layer 304 and heat resistant metal layer 303 on chip 300 surfaces beyond the solder cream 308, thereby expose passivation layer 302 through the method for spraying acid solution or wafer is soaked in the acid solution.
At last, implementation step S107, reflux solder cream forms salient point, promptly forms the chip grade packaging structure shown in Fig. 4 G.
In the present embodiment; Form solder bump 309 through backflow heat fused solder cream 308; Said solder cream 308 is the different shape of material of the same race with solder bump 309, has finally realized the function pads 301 of chip 300 is drawn out to the encapsulation transition on the solder bump 309.
Though the present invention discloses as above with preferred embodiment, the present invention is defined in this.Any those skilled in the art are not breaking away from the spirit and scope of the present invention, all can do various changes and modification, so protection scope of the present invention should be as the criterion with claim institute restricted portion.
Claims (10)
1. chip grade packaging structure; Comprise chip, ubm layer and solder bump; Said chip is provided with pad and passivation layer, said passivation layer be centered around said pad around, said ubm layer is positioned on the said pad; Said solder bump is positioned on the said ubm layer, it is characterized in that: said ubm layer comprises heat resistant metal layer, metal infiltrating layer, barrier layer and the scolder protective layer that from bottom to top is positioned at the chip bonding pad top successively.
2. a kind of chip grade packaging structure according to claim 1 is characterized in that the material of said heat resistant metal layer is a titanium.
3. a kind of chip grade packaging structure according to claim 1 is characterized in that, the material of said heat resistant metal layer is titanium, chromium, tantalum or their combination.
4. a kind of chip grade packaging structure according to claim 1 is characterized in that the material of said metal infiltrating layer is a copper.
5. a kind of chip grade packaging structure according to claim 1 is characterized in that, the material of said metal infiltrating layer is copper, aluminium, nickel or their combination.
6. a kind of chip grade packaging structure according to claim 1 is characterized in that the material on said barrier layer is a nickel.
7. a kind of chip grade packaging structure according to claim 6 is characterized in that, the thickness on said nickel barrier layer is 1.5～3 μ m.
8. a kind of chip grade packaging structure according to claim 1 is characterized in that, said scolder protective layer is pure tin or ashbury metal.
9. a kind of chip grade packaging structure according to claim 8 is characterized in that, the thickness of said scolder protective layer is 1～2 μ m.
10. according to claim 1 or 8 described a kind of chip grade packaging structures, it is characterized in that the material of said solder cream is consistent with the material of scolder protective layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011104283805A CN102496603A (en) | 2011-12-19 | 2011-12-19 | Chip level packaging structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011104283805A CN102496603A (en) | 2011-12-19 | 2011-12-19 | Chip level packaging structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN102496603A true CN102496603A (en) | 2012-06-13 |
Family
ID=46188409
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2011104283805A Pending CN102496603A (en) | 2011-12-19 | 2011-12-19 | Chip level packaging structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102496603A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103258805A (en) * | 2013-04-17 | 2013-08-21 | 南通富士通微电子股份有限公司 | Semiconductor device chip scale package structure |
| CN103681558A (en) * | 2012-09-03 | 2014-03-26 | 矽品精密工业股份有限公司 | Connection structure in semiconductor package |
| CN107195605A (en) * | 2017-05-18 | 2017-09-22 | 上海交通大学 | Cuprum-nickel-stannum micro bump using thin nickel dam as barrier layer and preparation method thereof |
| CN108517520A (en) * | 2018-06-15 | 2018-09-11 | 北京铂阳顶荣光伏科技有限公司 | A kind of diamond laminated film and its preparation method and application |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101241889A (en) * | 2007-01-12 | 2008-08-13 | 硅存储技术公司 | Under bump metallurgy structure of a package and method of making same |
| CN100517671C (en) * | 2006-06-12 | 2009-07-22 | 中芯国际集成电路制造(上海)有限公司 | Solder lug and manufacturing method thereof |
-
2011
- 2011-12-19 CN CN2011104283805A patent/CN102496603A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100517671C (en) * | 2006-06-12 | 2009-07-22 | 中芯国际集成电路制造(上海)有限公司 | Solder lug and manufacturing method thereof |
| CN101241889A (en) * | 2007-01-12 | 2008-08-13 | 硅存储技术公司 | Under bump metallurgy structure of a package and method of making same |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103681558A (en) * | 2012-09-03 | 2014-03-26 | 矽品精密工业股份有限公司 | Connection structure in semiconductor package |
| CN103258805A (en) * | 2013-04-17 | 2013-08-21 | 南通富士通微电子股份有限公司 | Semiconductor device chip scale package structure |
| CN103258805B (en) * | 2013-04-17 | 2015-11-25 | 南通富士通微电子股份有限公司 | semiconductor device chip scale package structure |
| CN107195605A (en) * | 2017-05-18 | 2017-09-22 | 上海交通大学 | Cuprum-nickel-stannum micro bump using thin nickel dam as barrier layer and preparation method thereof |
| CN108517520A (en) * | 2018-06-15 | 2018-09-11 | 北京铂阳顶荣光伏科技有限公司 | A kind of diamond laminated film and its preparation method and application |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102956590B (en) | For reducing the pseudo-inversed-chip lug of stress | |
| CN102201351B (en) | Semiconductor device and the method forming the double UBM structures connected for unleaded projection | |
| CN102130101B (en) | Form district around projection and form semiconductor device and the method for the projection cube structure with multilamellar UBM | |
| CN102163561B (en) | Semiconducter device and use same vehicle form the method for TMV and TSV in WLCSP | |
| CN102496580B (en) | A kind of formation method of solder bump | |
| US10043768B2 (en) | Semiconductor device and method of manufacture thereof | |
| TWI508202B (en) | Semiconductor device and method of dual-molding die formed on opposite sides of build-up interconnect structure | |
| CN103915353B (en) | Semiconductor devices and the method for forming embedded wafer-level chip scale package using standard carriers | |
| CN107039337A (en) | With the method and semiconductor devices of the semiconductor element formation DCALGA encapsulation for having microtrabeculae | |
| CN102496606B (en) | High-reliability wafer level cylindrical bump packaging structure | |
| CN102543766A (en) | Columnar bump packaging process | |
| CN102437066A (en) | High-reliability wafer-level columnar bump packaging method | |
| CN104425437A (en) | Three-dimensional chip stack and method of forming the same | |
| CN103715108A (en) | Semiconductor device and method of depositing encapsulant in embedded WLCSP | |
| CN102496604A (en) | High-reliability chip-scale packaging structure | |
| US20090200675A1 (en) | Passivated Copper Chip Pads | |
| CN102437065A (en) | High-reliability chip scale packaging method | |
| TW201209977A (en) | Semiconductor device and method of forming RDL wider than contact pad along first axis and narrower than contact pad along second axis | |
| CN102446780A (en) | Wafer-level packaging method | |
| CN103426850A (en) | Wafer-level chip size packaging structure | |
| CN101645407A (en) | Under bump metal layer, wafer level chip scale package structure and forming method thereof | |
| US7518211B2 (en) | Chip and package structure | |
| CN102543898A (en) | Cylindrical bump packaging structure | |
| CN202502990U (en) | Highly reliable chip-level package structure | |
| CN102437135A (en) | Wafer-level columnar bump packaging structure |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C12 | Rejection of a patent application after its publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20120613 |