CN102495352B - Multifunctional test circuit of integrated circuit stress degradation and test method thereof - Google Patents
Multifunctional test circuit of integrated circuit stress degradation and test method thereof Download PDFInfo
- Publication number
- CN102495352B CN102495352B CN201110443476.9A CN201110443476A CN102495352B CN 102495352 B CN102495352 B CN 102495352B CN 201110443476 A CN201110443476 A CN 201110443476A CN 102495352 B CN102495352 B CN 102495352B
- Authority
- CN
- China
- Prior art keywords
- stress
- circuit
- core circuit
- vdd
- switching transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000012360 testing method Methods 0.000 title claims abstract description 46
- 230000015556 catabolic process Effects 0.000 title abstract description 16
- 238000006731 degradation reaction Methods 0.000 title abstract description 16
- 238000010998 test method Methods 0.000 title abstract description 5
- 239000013256 coordination polymer Substances 0.000 claims abstract description 52
- 230000010355 oscillation Effects 0.000 claims abstract description 42
- 238000000034 method Methods 0.000 claims abstract description 15
- 238000005259 measurement Methods 0.000 claims description 44
- 230000007850 degeneration Effects 0.000 claims description 24
- 230000003534 oscillatory effect Effects 0.000 claims description 20
- 239000000758 substrate Substances 0.000 claims description 8
- 230000005540 biological transmission Effects 0.000 claims description 2
- 238000005516 engineering process Methods 0.000 abstract description 2
- 238000002347 injection Methods 0.000 abstract 2
- 239000007924 injection Substances 0.000 abstract 2
- 239000002784 hot electron Substances 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 6
- 230000000295 complement effect Effects 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- 238000001228 spectrum Methods 0.000 description 3
- 230000003068 static effect Effects 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 239000000523 sample Substances 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005284 excitation Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 238000005086 pumping Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
Images
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
The invention belongs to a integrated circuit reliability test technology field and especially relates to a multifunctional test circuit of integrated circuit stress degradation and a test method thereof. A core part of the test circuit takes an annular oscillator as a basis. Several auxiliary transistors, switch transistors and control terminals are added. By using the circuit and the method of the invention, a negative bias temperature instability, a positive bias temperature instability, hot hole injection or hot electron injection stress can be applied to pMOSFETs or nMOSFETs in a ring vibration inverter respectively; a ring oscillator is in a normal oscillation and stress oscillation state; the pMOSFETs or nMOSFETs of the inverter in the ring oscillator is in a measuring state of a charge pump. The degradation of the MOSFETs in the ring vibration inverter can be shown through changes of a ring oscillator oscillation frequency after the stress and can be shown through the changes of a CP current (Icpp or Icpn) of the pMOSFETs or nMOSFETs in the ring oscillator.
Description
Technical field
The invention belongs to IC reliability technical field of measurement and test, be specifically related to test circuit and method of testing that a kind of integrated circuit stress is degenerated.
Background technology
It is two basic problems that affect complementary metal oxide semiconductor (CMOS) field effect transistor (CMOSFET) reliability that bias voltage temperature instability (BTI) and hot carrier are injected (HCI).For the nanoscale CMOSFETs being made up of SiO2 or SiON gate medium, the Negative Bias Temperature Instability (NBTI) of pMOSFET is the main cause that affects device lifetime.But for the CMOSFETs being made up of high-k gate dielectric, the positive bias temperature instability (PBTI) of nMOSFET and the HCI of p and nMOSFET have material impact to device reliability.
BTI and HCI degenerate and cause the drive current of MOSFETs to reduce, or the increase of device delay.On the level of cmos circuit, above-mentioned degeneration can utilize the frequency change of ring oscillator (ring shakes or RO) after stress to characterize.Wherein the simplest a kind of metering circuit is take single RO as core, by the change in voltage of control end (OE) and power end, make RO be in respectively static stress, dynamic stress or normal oscillatory regime [V. Reddy et al., Impact of NBTI on Digital Circuit Reliability, IRPS, 2002, p.248].Although the circuit that single RO forms is simple in structure, the measuring accuracy of frequency change is not high.Improving improving one's methods of measuring accuracy is in circuit, to use two RO, one of them RO is as reference, do not add stress, another RO stress application, (Δ f) to measure the difference on the frequency of two RO by phase comparator, thereby [the T. H. Kim of the degradation characteristics of RO after acquisition stress, R. Persaud, and C. H. Kim, Silicon Odometer:An On-Chip Reliability Monitor for Measuring Frequency Degradation of Digital Circuits, IEEE JSSC vol.43, p.874,2008].
In measuring method as above, can degenerate in conjunction with dynamic stress (comprising BTI and HCI) and static stress degeneration (only comprising BTI) measurement result simultaneously, distinguish the BTI of CMOSFETs and the degeneration of HCI contribution in RO, but cannot distinguish the NBTI of pMOSFETs and the PBTI of nMOSFETs degeneration in CMOSFETs, also cannot distinguish HCI degeneration [the J. Keane et al. of pMOSFETs and nMOSFETs, On-chip reliability monitors for measuring circuit degradation, Microelectronics Reliability, vol. 50, p.1039, 2010].Because the PBTI of nMOSFETs degenerates and the NBTI degeneration of pMOSFETs has different mechanism, degeneration to circuit or life model have different contributions, therefore the PBTI that, distinguishes nMOSFETs in the degeneration of circuit is measured degenerates and the NBTI of pMOSFETs degenerates needs the mission life of predicting integrated circuit.Similarly, in circuit, pMOSFETs and nMOSFETs are applied to HCI stress independently, after measurement stress, HCI degenerates and also needs.
The physical cause that the BTI of MOSFET and HCI degenerate is the generation of boundary defect between stress lower channel/medium (interface state) and the generation of medium inherent vice or electric charge.Interface state, media defect and the iunjected charge (Oxide trapped charge) that produce due to stress have different impacts to the electrology characteristic of device, development can be distinguished the measuring method of the interface state, media defect and the iunjected charge that produce under stress, for the degradation model of setting up MOS device and circuit, there is using value in the life-span of characterizing device and circuit.
The method of traditional measurement MOSFET interface state density is the method for charge pump (CP).This is a kind of externally measured method, and pumping signal is provided by applying pulse generator, links drawing on pad (Pad) of MOSFET to be measured by cable and probe.This method runs into very large difficulty when measuring the MOSFET of nanoscale.Because device area (W × L) is too little, under conventional driving pulse frequency (￡ MHz), cp is too little for CP electric current I, cannot measure.If improve driving pulse frequency, due to the ghost effect of the measuring system such as cable, probe, the Icp of MOSFET can be covered by spur signal.For the CP that solves nanoscale MOSFET measures, propose in the world to measure on sheet method [the R. Fernandez et al. of CP, AC NBTI studied in the 1Hz-2GHz range on dedicated on-chip CMOS circuits, IEDM 2006, p.1039], the circuit of measured device and generation driving pulse is integrated, make the excitation frequency of CP can reach 2GHz.But the measured device in above-mentioned measuring method or discrete (individual devices), measured device does not form any type of circuit.The stress of device is degenerated and can only, by static characteristics as IdVg and Icp reflect, cannot be reflected as postponed by the dynamic perfromance of device, together with therefore cannot contacting directly with the application of circuit.
Summary of the invention
The multifunctional testing circuit and the method for testing that the object of the present invention is to provide a kind of integrated circuit stress to degenerate.Utilize test circuit of the present invention and method of testing, can apply NBTI, PBTI, HCI and dynamic stress to the crucial CMOSFETs in test circuit respectively, then utilize the degradation characteristics of the crucial CMOSFETs of the frequency of annular oscillation circuit or the measure of the change of CP electric current I cp under various stress.
The multifunctional testing circuit that integrated circuit stress provided by the invention is degenerated, its core (core circuit) is take a ring oscillator (RO_CP) as basis, between every two-stage phase inverter of RO_CP, access one group of auxiliary pMOSFET and nMOSFET, wherein the source of auxiliary pMOSFET and nMOSFET meets respectively noble potential Vdd1 and the electronegative potential Vss of RO_CP.The leakage of every group of pMOSFET and nMOSFET connects together, and is connected respectively with another switching transistor S2 by a switching transistor S1 with the output of prime phase inverter with the input of rear class phase inverter.The grid of all auxiliary pMOSFETs connects together, and receives first control end Vp; The grid of all auxiliary nMOSFETs connects together, and receives second control end Vn.The grid of all switching transistor S1 connects together, and receives the 3rd control end VS1; The grid of all switching transistor S2 connects together, and receives the 4th control end VS2.The substrate of pMOSFETs in all phase inverters of RO_CP connects together, and receives an outside link Icpp; The substrate of nMOSFETs in all phase inverters of RO_CP connects together, and receives another outside link Icpn.Switching transistor can be by single nMOSFET(switching transistor) form, the complementary switch circuit that also can be made up of two CMOSFETs forms.All switching transistors are I/O device, have thicker gate medium, and operating voltage is higher than the operating voltage of core circuit, to avoid the high level threshold value loss in when transmission.
The output of core circuit is connected to the input of the first frequency divider, and the input of the first impact damper is received in the output of the first frequency divider, and the first external measuring junction OUT1 of test circuit is linked in the output of the first impact damper.The hot end of the first frequency divider and the first impact damper is linked another high power end Vdd2 of circuit, and isolates with the high power end Vdd1 of core circuit.If the normal oscillation frequency of core circuit is f, the dynamic range of surveying instrument (as oscillograph or spectrum analyzer) is fd, the Frequency Dividing Factor N>f/fd of frequency divider.
Except core circuit, test circuit also comprise one identical with core circuit structure with reference to circuit RO_ref.Be connected to the input of the second frequency divider with reference to the output of circuit, the input of the second impact damper is received in the output of the second frequency divider, and the second external measuring junction OUT2 of test circuit is linked in the output of the second impact damper.The noble potential of the noble potential of the second frequency divider and the second impact damper and the first frequency divider and the first impact damper connects together, and receives another high power end Vdd2 of test circuit.If the normal oscillation frequency with reference to circuit is fref, the dynamic range of surveying instrument (as oscillograph or spectrum analyzer) is fd, the Frequency Dividing Factor N>fref/fd of frequency divider.
Test circuit also comprises a phase comparator.Core circuit and two inputs of linking phase comparator with reference to the output of circuit, the output of phase comparator is connected to the input of the 3rd impact damper, and the 3rd external measuring junction OUT3 of test circuit linked in the output of the 3rd impact damper.The hot end of phase comparator and the 3rd impact damper and the hot end of other frequency divider and impact damper connect together, and receive another high power end Vdd2 of test circuit.Except core circuit (RO_CP), in test circuit, the cold end of every other circuit connects together, and receives another cold end GND of test circuit, and isolates with the cold end Vss of core circuit.
Also link the input end of all phase inverters in core circuit RO_CP by some switching transistor S with reference to the output of circuit RO_ref.The grid of all switching transistor S connects together, and receives an external control end VS.Switch S can be by single nMOSFET(switching transistor) form, the complementary switch circuit that also can be made up of two CMOSFETs forms.All switching transistors in RO_ref, all the time in conducting state, therefore connect together the grid of all switching transistors in RO_ref, receive another high power end Vdd3 of test circuit, and isolate with other two high power end Vdd1 and Vdd2.
Whole circuit has 15 external contact discs (Pad), a high power end Vdd1 that core circuit uses, the low power end Vss of a core circuit, one with reference to circuit, frequency divider, the common high power end Vdd2 using of impact damper and phase comparator, one with reference to circuit, frequency divider, the common low power end GND using of phase buffer and phase comparator, a control end Vdd3 with reference to all switches in circuit, three switch S, S1, the control end VS of S2, VS1, VS2, control end Vp and the Vn of two pMOSFETs and nMOSFETs auxiliary transistor, the voltage of two CP is executed sum current (Icpp and Icpn) measuring junction, the output terminal OUT1 of three circuit, OUT2, OUT3.
In sum, the present invention proposes multifunctional testing circuit and the method for testing that a kind of integrated circuit stress is degenerated.The core (core circuit) of test circuit, take ring oscillator (ring shakes or RO) as basis, adds auxiliary transistor, switching transistor and Circumscribing port.By the conduction and cut-off state of control end control auxiliary transistor and the on off state of switching transistor, can make respectively core circuit in normal vibration, stress oscillation, positive bias temperature instability (PBTI) stress that applies Negative Bias Temperature Instability (NBTI) stress, nMOSFETs of pMOSFETs, the hot hole of pMOSFETs or nMOSFETs injects (HHI or pHCI) or thermoelectron injects (HEI or nHCI) stress, and the charge pump of pMOSFETs or nMOSFETs (CP) measuring state.Except core circuit, test circuit also comprises that one with reference to auxiliary circuits such as circuit, a phase comparator, two frequency dividers and three impact dampers.Structure with reference to circuit is identical with core circuit, but CMOSFETs in circuit is not subject to any stress, identical with the output frequency of core circuit under normal oscillatory regime all the time with reference to the output frequency of circuit.In the stress degradation testing of core circuit, can be used to frequency reference with reference to circuit, also can be used to pulse generation source, measure with the CP that carries out CMOSFETs in core circuit phase inverter.Therefore, the frequency change that circuit of the present invention both can shake by ring, also can pass through the CP curent change of CMOSFETs, measure the stress degradation characteristics of CMOSFETs device and circuit, comprise dynamic stress degradation characteristics, the NBTI stress degradation characteristics of pMOSFETs, the PBTI stress degradation characteristics of nMOSFETs, the thermoelectron that the hot hole of pMOSFETs injects degradation characteristics and nMOSFETs injects degradation characteristics.
Accompanying drawing explanation
Fig. 1 is the structural drawing of reliability testing circuit of the present invention.
Fig. 2 is test circuit core: core circuit figure.
Fig. 3 be test circuit with reference to part: with reference to circuit diagram.
Fig. 4 is a kind of replacement circuit figure of switch.
Fig. 5 is a kind of circuit structure diagram of frequency divider.
Fig. 6 is a kind of circuit structure diagram of impact damper;
Fig. 7 is a kind of structural drawing of phase comparator.
Fig. 8 is a kind of domain framework of test circuit.
Fig. 9 is that test circuit is connected and arrangement plan with the one of peripheral instrument.
Figure 10 is the bias arrangement figure of core circuit RO_CP in the time of normal oscillatory regime.
Figure 11 is pMOSFETs in the core circuit RO_CP phase inverter bias arrangement figure in the time of NBTI stress.
Figure 12 is nMOSFETs in the core circuit RO_CP phase inverter bias arrangement figure in the time of PBTI stress.
Figure 13 is pMOSFETs in the core circuit RO_CP phase inverter bias arrangement figure in the time of HCI stress.
Figure 14 is nMOSFETs in the core circuit RO_CP phase inverter bias arrangement figure in the time of HCI stress.
Figure 15 is CMOSFETs in the core circuit RO_CP phase inverter bias arrangement figure in the time of dynamic stress.
Figure 16 is pMOSFETs in the core circuit RO_CP phase inverter bias arrangement figure in the time that Icpp measures.
Figure 17 is nMOSFETs in the core circuit RO_CP phase inverter bias arrangement figure in the time that Icpn measures.
Number in the figure: 1 is ring oscillator RO_CP, 3 is the first frequency dividing circuit, and 4 is the first buffer circuit, and 5 is with reference to circuit RO_ref, and 6 is the second frequency dividing circuit, 7 is the second buffer circuit; 8 is phase comparator, and 9 is the 3rd buffer circuit; 11 is auxiliary pMOSFET, and 12 is auxiliary nMOSFET, and 13 is switching transistor S1, and 14 is switching transistor S2, and 51 is switching transistor S; 201 is the noble potential of ring oscillator RO_CP, the 202 electronegative potential Vss that are RO_CP, and 203 is the first control end Vp, 204 is the second control end Vn; 205 is the 3rd control end VS1, and 206 is the 4th control end VS2; 207 is outside link Icpp; 208 is outside link Icpn; 209 is externally measured end OUT1, and 210 is externally measured end OUT2; 211 is the 3rd externally measured end OUT3, and 212 is external control end VS.
Embodiment
Circuit of the present invention and method are for IC reliability test, the particularly degradation testing under NBTI, PBTI, HCI and dynamic stress for CMOSFETs in integrated circuit.Test parameter comprises the ring CMOSFETs stress frequency change causing of degenerating of shaking in phase inverter, also comprises the CP electric current that CMOSFETs produces under stress.Integrated circuit as shown in Figure 1, have 15 external contact dishes (Pad), be respectively the high power end Vdd1 of core circuit, the low power end Vss of core circuit, with reference to circuit, frequency divider, the common high power end Vdd2 using of impact damper and phase comparator, with reference to circuit, frequency divider, the common low power end GND using of impact damper and phase comparator, with reference to the control end Vdd3 of all switches in circuit, switch S, S1, the control end VS of S2, VS1, VS2, control end Vp and the Vn of pMOSFETs and nMOSFETs auxiliary transistor, voltage (Vcpp and Vcpn) when CP measures is executed sum current (Icpp and Icpn) test lead, the output terminal OUT1 of circuit, OUT2, OUT3.
Fig. 2 is by ring shakes, auxiliary transistor nMOSFETs and pMOSFETs, switching transistor S1 and S2 form core circuit RO_CP.Fig. 3 is identical with core circuit structure with reference to circuit RO_ref.Fig. 4 is a kind of replacement circuit of switch.Fig. 5 is a kind of circuit structure diagram of frequency divider.Fig. 6 is a kind of circuit structure diagram of impact damper.Fig. 7 is a kind of circuit diagram of phase comparator.Fig. 8 is a kind of layout design framework of test circuit.
When measurement, the peripheral instrument configuration of circuit connects as shown in Figure 9.Wherein Vdd1, Vdd2, Vdd3, Vss, GND, VS, VS1, VS2, Vp, Vn connect external voltage source, can apply different voltage (or ground connection) according to different stress and measurement pattern.Icpp and Icpn connect the source measuring unit (SMU) in analyzing parameters of semiconductor instrument, are executing the alive electric current of simultaneously measuring.OUT1, OUT2, optional oscillograph or the spectrum analyzer of connecing of OUT3.
Figure 10 is the bias arrangement of core circuit under normal oscillatory regime, for encircling the measurement of the oscillation frequency of shaking: the operating voltage Vdd0 that adds integrated circuit on Vdd1, Vp, Icpp, Vn, Icpn, Vss ground connection, VS1=VS2=VddI/O > Vdd0+Vthn, and make the switching transistor S cut-off in Fig. 1, i.e. VS ground connection.In this configuration, switching transistor S1, S2 in core circuit Fig. 2 are conductings, auxiliary transistor pMOSFETs and nMOSFETs end, therefore core circuit is in normal oscillatory regime, can measure the oscillator signal OUT1 after frequency division by oscillograph, therefrom can read output frequency fout, obtain thus the normal oscillation frequency f=N*fout of core circuit, wherein N is the divide ratio of frequency divider.
Figure 11 is pMOSFETs in the core circuit phase inverter bias arrangement under NBTI stress: on Vdd1, Icpp, Vp and Vn, add Vstress, VS1, Icpn, Vss ground connection, VS2=VddI/O > Vstress+Vthn, and make the switching transistor S cut-off in Fig. 1, i.e. VS ground connection.In this configuration, the switching transistor S1 cut-off in core circuit Fig. 2, S2 conducting, auxiliary transistor pMOSFETs is in cut-off state, and nMOSFETs is in conducting state.Therefore, in RO_CP, the input of every grade of phase inverter is in electronegative potential 0, and the output of phase inverter is in noble potential Vstress, and the pMOSFETs in RO_CP phase inverter is in NBTI stress state, and nMOSFETs in RO_CP phase inverter is not subject to stress.
Figure 12 is the bias arrangement of nMOSFETs under PBTI stress in core circuit phase inverter: on Vdd1 and Icpp, add Vstress, VS1, Icpn, Vp, Vn and Vss ground connection, VS2=VddI/O > Vstress+Vthn, and make the switching transistor S cut-off in Fig. 1, i.e. VS ground connection.In this configuration, the switching transistor S1 cut-off in core circuit Fig. 2, switching transistor S2 conducting, auxiliary transistor pMOSFETs is in conducting state, and nMOSFETs is in cut-off state.Therefore, in RO_CP, the input of every grade of phase inverter is in noble potential Vstress, and the output of phase inverter is in electronegative potential 0, and the nMOSFETs in RO_CP phase inverter is in PBTI stress state, and pMOSFETs in RO_CP phase inverter is not subject to stress.
Figure 13 is the bias arrangement of pMOSFETs under HCI stress in core circuit phase inverter: on Vdd1, Icpp, Vp and Vn, add Vstress, Icpn and Vss ground connection, VS1=VS2=VddI/O > Vstress+Vthn, and make the switch S cut-off in Fig. 1, i.e. VS ground connection.In this configuration, the switching transistor S1 in core circuit Fig. 2, switching transistor S2 conducting, auxiliary transistor pMOSFETs is in cut-off state, and nMOSFETs is in conducting state.Therefore, in RO_CP the input and output of every grade of phase inverter all in 0 and Vthn between current potential, the pMOSFETs in RO_CP phase inverter is in HCI stress state, and nMOSFETs in RO_CP phase inverter is not subject to stress.
Figure 14 is the bias arrangement of nMOSFETs under HCI stress in core circuit phase inverter: on Vdd1 and Icpp, add Vstress, Vp, Vn, Icpn and Vss ground connection, VS1=VS2=VddI/O > Vstress+Vthn, and make the switch S cut-off in Fig. 1, i.e. VS ground connection.In this configuration, the switching transistor S1 in core circuit Fig. 2, switching transistor S2 conducting, auxiliary transistor pMOSFETs is in conducting state, and nMOSFETs is in cut-off state.Therefore, all current potentials between (Vstress+Vthp) and Vstress of the input and output of every grade of phase inverter in RO_CP, the nMOSFETs in RO_CP phase inverter is in HCI stress state, and pMOSFETs in RO_CP phase inverter is not subject to stress.
Figure 15 is the bias arrangement of core circuit under stress oscillation state or dynamic stress: on Vdd1, Icpp and Vp, add Vstress, Vn, Icpn and Vss ground connection, VS1=VS2=VddI/O > Vstress+Vthn, and make the switch S cut-off in Fig. 1, i.e. VS ground connection.In this configuration, switching transistor S1, switching transistor S2 in core circuit Fig. 2 are conductings, and auxiliary transistor pMOSFETs and nMOSFETs end, and therefore core circuit is in stress oscillation state, i.e. dynamic stress state.
Figure 16 is pMOSFETs in the core circuit phase inverter bias arrangement in the time that CP measures: the operating voltage Vdd0 that adds integrated circuit on Vdd2, the upper making alive Vdd ≈ Vdd0/2 of Vdd1 and Vss, Vp, Vn, VS2 and Icpn ground connection, VS1=Vdd3=VddI/O > Vdd0+Vthn, and make the switch S conducting in Fig. 1, i.e. VS=VddI/O > Vdd0+Vthn.In this configuration, switching transistor S1 conducting in core circuit Fig. 2, switching transistor S2 cut-off, auxiliary transistor pMOSFETs conducting, nMOSFETs cut-off, in phase inverter, the grid of pMOSFETs provide driving pulse by RO_ref, and source and drain voltage be all Vdd ≈ Vdd0/2, and substrate making alive Vcpp=Vdd ≈ can measure CP electric current I cpp when Vdd0/2.
Figure 17 is nMOSFETs in the core circuit phase inverter bias arrangement in the time that CP measures: the operating voltage Vdd0 that adds integrated circuit on Vdd2, Vp, Vn and Icpp, the upper making alive Vdd ≈ Vdd0/2 of Vdd1 and Vss, VS2 ground connection, VS1=Vdd3=VddI/O > Vdd0+Vthn, and make the switch S conducting in Fig. 1, i.e. VS=VddI/O > Vdd0+Vthn.In this configuration, switching transistor S1 conducting in core circuit Fig. 2, switching transistor S2 cut-off, auxiliary transistor pMOSFETs cut-off, nMOSFETs conducting, in phase inverter, the grid of nMOSFETs provide driving pulse by RO_ref, and source and drain voltage be all Vdd ≈ Vdd0/2, and substrate making alive Vcpn=Vdd ≈ can measure CP electric current I cpn when Vdd0/2.
utilize the NBTI stress degeneration step of pMOSFETs in circuit measuring core circuit phase inverter of the present invention as follows:
(1) as shown in Figure 9 and Figure 10, measure the output frequency fout of the novel circuit (Fresh circuit) that does not add stress by output terminal OUT1, calculated the normal oscillation frequency f0 of core circuit by the divide ratio N of output frequency fout and frequency divider.
(2) on core circuit, apply as shown in figure 11, the NBTI stress of Vstress.
(3) after stress time tstress1, Circnit Layout returns to the normal oscillatory regime shown in Figure 10, oscillation frequency f1(NBTI, the tstress1 of measurement core circuit).
(4) repeating step (2) and (3), measurement core circuit time under NBTI stress is respectively oscillation frequency f2(NBTI, the tstress2 of tstress2, tstress3 etc.), f3(NBTI, tstress3) etc.
(5) calculate the frequency change Δ f1(NBTI of core circuit under NBTI stress)=f1(NBTI, tstress1)-f0, Δ f2(NBTI)=f2(NBTI, tstress2)-f0, Δ f3(NBTI)=f3(NBTI, tstress3)-f0 etc.
utilize the PBTI stress degeneration step of nMOSFETs in circuit measuring core circuit phase inverter of the present invention as follows:
(1) as shown in Figure 9 and Figure 10, measure the output frequency fout of the novel circuit (Fresh circuit) that does not add stress by output terminal OUT1, calculated the normal oscillation frequency f0 of core circuit by the divide ratio N of output frequency fout and frequency divider.
(2) on core circuit, apply as shown in figure 12, the PBTI stress of Vstress.
(3) after stress time tstress1, Circnit Layout returns to the normal oscillatory regime shown in Figure 10, oscillation frequency f1(PBTI, the tstress1 of measurement core circuit).
(4) repeating step (2) and (3), measurement core circuit time under PBTI stress is respectively oscillation frequency f2(PBTI, the tstress2 of tstress2, tstress3 etc.), f3(PBTI, tstress3) etc.
(5) calculate the frequency change Δ f1(PBTI of core circuit under PBTI stress)=f1(PBTI, tstress1)-f0, Δ f2(PBTI)=f2(PBTI, tstress2)-f0, Δ f3(PBTI)=f3(PBTI, tstress3)-f0 etc.
utilize the HCI(HHI of pMOSFETs in circuit measuring core circuit phase inverter of the present invention) stress degeneration step is as follows:
(1) as shown in Figure 9 and Figure 10, measure the output frequency fout of the novel circuit (Fresh circuit) that does not add stress by output terminal OUT1, calculated the normal oscillation frequency f0 of core circuit by the divide ratio N of output frequency fout and frequency divider.
(2) on core circuit, apply as shown in figure 13, the HCI stress of Vstress.
(3) after stress time tstress1, Circnit Layout returns to the normal oscillatory regime shown in Figure 10, oscillation frequency f1(HHI, the tstress1 of measurement core circuit).
(4) repeating step (2) and (3), measurement core circuit time under HHI stress is respectively oscillation frequency f2(HHI, the tstress2 of tstress2, tstress3 etc.), f3(HHI, tstress3) etc.
(5) calculate the frequency change Δ f1(HHI of core circuit under HHI stress)=f1(HHI, tstress1)-f0, Δ f2(HHI)=f2(HHI, tstress2)-f0, Δ f3(HHI)=f3(HHI, tstress3)-f0 etc.
utilize the HCI(HEI of nMOSFETs in circuit measuring core circuit phase inverter of the present invention) stress degeneration step is as follows:
(1) as shown in Figure 9 and Figure 10, measure the output frequency fout of the novel circuit (Fresh circuit) that does not add stress by output terminal OUT1, calculated the normal oscillation frequency f0 of core circuit by the divide ratio N of output frequency fout and frequency divider.
(2) on core circuit, apply as shown in figure 14, the HCI stress of Vstress.
(3) after stress time tstress1, Circnit Layout returns to the normal oscillatory regime shown in Figure 10, oscillation frequency f1(HEI, the tstress1 of measurement core circuit).
(4) repeating step (2) and (3), measurement core circuit time under HEI stress is respectively oscillation frequency f2(HEI, the tstress2 of tstress2, tstress3 etc.), f3(HEI, tstress3) etc.
(5) calculate the frequency change Δ f1(HEI of core circuit under HEI stress)=f1(HEI, tstress1)-f0, Δ f2(HEI)=f2(HEI, tstress2)-f0, Δ f3(HEI)=f3(HEI, tstress3)-f0 etc.
utilize in circuit measuring core circuit phase inverter of the present invention dynamic (Dynamic) stress degeneration step of CMOSFETs as follows:
(1) as shown in Figure 9 and Figure 10, measure the output frequency fout of the novel circuit (Fresh circuit) that does not add stress by output terminal OUT1, calculated the normal oscillation frequency f0 of core circuit by the divide ratio N of output frequency fout and frequency divider.
(2) on core circuit, apply as shown in figure 15, the dynamic stress of Vstress.
(3) after stress time tstress1, Circnit Layout returns to the normal oscillatory regime shown in Figure 10, oscillation frequency f1(Dynamic, the tstress1 of measurement core circuit).
(4) repeating step (2) and (3), measurement core circuit time under dynamic stress is respectively oscillation frequency f2(Dynamic, the tstress2 of tstress2, tstress3 etc.), f3(Dynamic, tstress3) etc.
(5) calculate the frequency change Δ f1(Dynamic of core circuit under dynamic stress)=f1(Dynamic, tstress1)-f0, Δ f2(Dynamic)=f2(Dynamic, tstress2)-f0, Δ f3(Dynamic)=f3(Dynamic, tstress3)-f0 etc.
utilize the stress degeneration step of MOSFETs in the phase comparator measurement core circuit inverter in circuit of the present invention as follows:
(1), as shown in Figure 11,12,13,14 and 15, on core circuit, apply respectively NBTI, PBTI, HHI, HEI or the dynamic stress of Vstress.
(2), after stress time tstress1, Circnit Layout returns to the normal oscillatory regime shown in Figure 10, by OUT3 measurement core circuit with reference to difference on the frequency Δ f1(Stress, the tstress1 of circuit RO_ref)=fOUT3.
(3) repeating step (1) and (2), by OUT3 measurement core circuit time under various stress be respectively tstress2, tstress3 etc. rear with reference to the difference on the frequency Δ f2(Stress of circuit RO_ref, tstress2), Δ f3(Stress, tstress3) etc.
It should be noted that, domain mismatch or the impact of the factor such as process deviation while manufacturing while design due to circuit, with reference to circuit RO_ref and the output frequency of the novel circuit RO_CP that does not add stress under normal oscillatory regime may and unequal, but there is certain deviation, now can measure this deviation f0 by output terminal OUT1, OUT2, OUT3, and deduct (or adding) f0 on the difference on the frequency recording in step (2).
utilize the stress degeneration step of the CP electric current I cpp of pMOSFETs in circuit measuring core circuit phase inverter of the present invention as follows:
(1), as shown in Fig. 9 and Figure 16, hold the CP electric current I cpp0 that measures the novel circuit (Fresh circuit) that does not add stress by Icpp.
(2), as shown in Figure 11,12,13,14 and 15, on core circuit, apply respectively NBTI, PBTI, HHI, HEI or the dynamic stress of Vstress.
(3) after stress time tstress1, Circnit Layout returns shown in Figure 16 and configures, and is held and is measured CP electric current I cpp1(Stress, tstress1 by Icpp).
(4) repeating step (2) and (3), are respectively CP electric current I cpp2(Stress, the tstress2 after tstress2, tstress3 etc. by Icpp measurement core circuit time under various stress), Icpp3(Stress, tstress3) etc.
(5) calculate the CP curent change Δ Icpp1(Stress of core circuit under various stress)=Icpp1(Stress, tstress1)-Icpp0, Δ Icpp2(Stress)=Icpp2(Stress, tstress2)-Icpp0, Δ Icpp3(Stress)=Icpp3(Stress, tstress3)-Icpp0 etc.
utilize the stress degeneration step of the CP electric current I cpn of nMOSFETs in circuit measuring core circuit phase inverter of the present invention as follows:
(1), as shown in Fig. 9 and Figure 17, hold the CP electric current I cpn0 that measures the novel circuit (Fresh circuit) that does not add stress by Icpn.
(2), as shown in Figure 11,12,13,14 and 15, on core circuit, apply respectively NBTI, PBTI, HHI, HEI or the dynamic stress of Vstress.
(3) after stress time tstress1, Circnit Layout returns shown in Figure 17 and configures, and is held and is measured CP electric current I cpn1(Stress, tstress1 by Icpn).
(4) repeating step (2) and (3), are respectively CP electric current I cpn2(Stress, the tstress2 after tstress2, tstress3 etc. by Icpn measurement core circuit time under various stress), Icpn3(Stress, tstress3) etc.
(5) calculate the CP curent change Δ Icpn1(Stress of core circuit under various stress)=Icpn1(Stress, tstress1)-Icpn0, Δ Icpn2(Stress)=Icpn2(Stress, tstress2)-Icpn0, Δ Icpn3(Stress)=Icpn3(Stress, tstress3)-Icpn0 etc.
Claims (4)
1. the multifunctional testing circuit that integrated circuit stress is degenerated, is characterized in that comprising a core circuit, and this core circuit comprises a ring oscillator RO_CP(1); At ring oscillator RO_CP(1) every two-stage phase inverter between, access one group of auxiliary pMOSFET(11) and nMOSFET(12), wherein the source electrode of auxiliary pMOSFETs and nMOSFETs meets respectively the noble potential Vdd1(201 of ring oscillator RO_CP) and electronegative potential Vss(202), the drain electrode of every group of pMOSFET and nMOSFET connects together, by switching transistor S1(13) with switching transistor S2(14) be connected with the input of rear class phase inverter with the output of prime phase inverter respectively; The grid of all auxiliary pMOSFETs connects together, and receives the first control end Vp(203), the grid of all auxiliary nMOSFETs connects together, and receives the second control end Vn(204); The grid of all switching transistor S1 connects together, and receives the 3rd control end VS1(205), the grid of all switching transistor S2 connects together, and receives the 4th control end VS2(206); The substrate of pMOSFETs in all phase inverters of ring oscillator RO_CP connects together, and receives separately an outside link Icpp(207); The substrate of nMOSFETs in all phase inverters of ring oscillator RO_CP connects together, and receives separately an outside link Icpn(208); All switching transistors are I/O device, and its operating voltage is higher than the operating voltage of core circuit, the threshold value loss when avoiding high level transmission;
Described test circuit, also comprises the first frequency dividing circuit (3) and the first buffer circuit (4) that a divide ratio is N; The input of the first frequency dividing circuit (3) is linked in the output of core circuit (1), and the input of the first buffer circuit (4) is linked in the output of the first frequency dividing circuit (3), and an externally measured end OUT1(209 is linked in the output of the first buffer circuit (4)).
2. the multifunctional testing circuit that integrated circuit stress as claimed in claim 1 is degenerated, it is characterized in that test circuit also comprise one identical with core circuit structure with reference to circuit RO_ref(5), second buffer circuit (7) that second frequency dividing circuit (6) identical with the first frequency dividing circuit is identical with the first buffer circuit with; Link the input of the second frequency dividing circuit (6) with reference to the output of circuit RO_ref, the input of the second buffer circuit (7) is linked in the output of the second frequency dividing circuit (6), and another externally measured end OUT2(210 is linked in the output of the second buffer circuit (7)); In addition, test circuit also comprises a phase comparator (8) and the 3rd buffer circuit (9); An input of phase comparator (8) is also linked in the output of core circuit (1), with reference to circuit RO_ref(5) output another input of also linking phase comparator (8), the input of the 3rd buffer circuit (9) is linked in the output of phase comparator (8), and the 3rd externally measured end OUT3(211 linked in the output of the 3rd buffer circuit (9)); With reference to circuit RO_ref(5) output also by some switching transistor S(51) link ring oscillator RO_CP(1) and in the input of every one-level phase inverter, the grid of all switching transistor S connects together, and receives external control end VS(212).
3. the multifunctional testing circuit that integrated circuit stress as claimed in claim 2 is degenerated, is characterized in that:
In described core circuit, as the control end voltage VS=0V of switching transistor S, and work as the threshold voltage vt hn of the control end voltage VS1=VS2=VddI/O > Vdd+ switching transistor of switching transistor S1 and S2, control voltage Vp=Vdd and the Vn=Vss of p and n auxiliary transistor, the transistorized charge pump control end of p and n voltage Vcpp=Vdd and Vcpn=Vss, the high power end voltage of core circuit Vdd1=Vdd, when Vdd=Vdd0, Vdd0 is the operating voltage of integrated circuit, switching transistor S cut-off, switching transistor S1 and switching transistor S2 conducting, all p and the cut-off of n auxiliary transistor, ring oscillator RO_CP is in normal oscillatory regime,
Described with reference to circuit RO_ref(5) in, as the high power end voltage Vdd2=Vdd with reference to circuit, with reference to the switch control end voltage Vdd3=VddI/O > Vdd+Vthn in circuit, when Vdd=Vdd0 is the operating voltage of integrated circuit, be not subject to stress with reference to all MOSFETs in circuit RO_ref, and RO_ref is all the time in normal oscillatory regime, and the output frequency of RO_ref is identical with the output frequency of core circuit all the time;
In described core circuit, as switch control end VS=0V, and work as VS1=0V, VS2=VddI/O > Vdd+Vthn, Vp=Vn=Vdd, Vcpp=Vdd, Vcpn=Vss, Vdd1=Vdd, when wherein Vdd=Vstress > Vdd0 is stress voltage, switching transistor S and switching transistor S1 cut-off, switching transistor S2 conducting, the cut-off of p auxiliary transistor, the conducting of n auxiliary transistor, in all phase inverters of RO_CP, grid, source electrode and the drain electrode of pMOSFETs are respectively in Vss, Vdd and Vdd; The grid of corresponding nMOSFETs and source electrode be all in Vss, i.e. the stress state of pMOSFETs in all phase inverters of RO_CP in Negative Bias Temperature Instability (NBTI), and corresponding nMOSFETs is in unstressed condition;
In described core circuit, as switch control end VS=0V, and work as VS1=0V, VS2=VddI/O > Vdd+Vthn, Vp=Vn=Vss, Vcpp=Vdd, Vcpn=Vss, Vdd1=Vdd, when Vdd=Vstress > Vdd0 is stress voltage, switching transistor S and switching transistor S1 cut-off, switching transistor S2 conducting, the conducting of p auxiliary transistor, the cut-off of n auxiliary transistor, in all phase inverters of RO_CP, the grid of pMOSFETs and source electrode are all in Vdd, the grid of corresponding nMOSFETs, source electrode and drain electrode are respectively in Vdd, Vss and Vss, it is the nMOSFETs of all phase inverters in the RO_CP stress state in positive bias temperature instability (PBTI), and corresponding pMOSFETs is in unstressed condition,
In described core circuit, as switch control end VS=0V, and as VS1=VS2=VddI/O > Vdd+Vthn, Vp=Vn=Vdd, Vcpp=Vdd, Vcpn=Vss, Vdd1=Vdd, when Vdd=Vstress > Vdd0 is stress voltage, switching transistor S cut-off, switching transistor S1 and switching transistor S2 conducting, the cut-off of p auxiliary transistor, the conducting of n auxiliary transistor, in RO_CP, the pMOSFETs of all phase inverters is in conducting state, and grid and drain electrode are in identical current potential, but corresponding nMOSFETs is in cut-off state, the pMOSFETs that is all phase inverters in RO_CP injects the stress state of (pHCI) in hot carrier, and corresponding nMOSFETs is in unstressed condition,
In described core circuit, as switch control end VS=0V, and as VS1=VS2=VddI/O > Vdd+Vthn, Vp=Vn=Vss, Vcpp=Vdd, Vcpn=Vss, Vdd1=Vdd, when Vdd=Vstress > Vdd0 is stress voltage, switching transistor S cut-off, switching transistor S1 and switching transistor S2 conducting, the conducting of p auxiliary transistor, the cut-off of n auxiliary transistor, in RO_CP, the pMOSFETs of all phase inverters is in cut-off state, but corresponding nMOSFETs is in conducting state, and grid and drain electrode are in identical current potential, the nMOSFETs that is all phase inverters in RO_CP injects the stress state of (nHCI) in hot carrier, and corresponding pMOSFETs is in unstressed condition,
In described core circuit, as switch control end VS=0V, and as VS1=VS2=VddI/O > Vdd+Vthn, Vp=Vdd, Vn=Vss, Vcpp=Vdd, Vcpn=Vss, Vdd1=Vdd, when Vdd=Vstress > Vdd0 is stress voltage, switching transistor S cut-off, switching transistor S1 and switching transistor S2 conducting, p and n auxiliary transistor all end, and RO_CP is in stress oscillation state, or CMOSFETs in RO_CP is in dynamic stress state;
In described core circuit, as switch control end VS=VddI/O > Vdd0+Vthn, and as VS1=VddI/O > Vdd0+Vthn, VS2=0V, Vp=Vn=0V, Vcpp=Vdd, Vcpn=0V, Vdd1=Vss=Vdd, when Vdd ≈ Vdd0/2, switching transistor S and switching transistor S1 conducting, switching transistor S2 cut-off, the conducting of p auxiliary transistor, the cut-off of n auxiliary transistor, in RO_CP, the pMOSFETs of all phase inverters is in charge pump (CP) test mode, the grid that is pMOSFETs provides driving pulse by RO_ref, source electrode and drain voltage are all Vdd ≈ Vdd0/2, substrate making alive Vcpp=Vdd ≈ can measure CP electric current I cpp when Vdd0/2,
In described core circuit, as switch control end VS=VddI/O > Vdd0+Vthn, and as VS1=VddI/O > Vdd0+Vthn, VS2=0V, Vp=Vn=Vdd0, Vcpp=Vdd0, Vcpn=Vdd, Vdd1=Vss=Vdd, when Vdd ≈ Vdd0/2, switching transistor S and switching transistor S1 conducting, switching transistor S2 cut-off, the cut-off of p auxiliary transistor, the conducting of n auxiliary transistor, in RO_CP, the nMOSFETs of all phase inverters is in CP test mode, the grid that is nMOSFETs provides driving pulse by RO_ref, source electrode and drain voltage are all Vdd ≈ Vdd0/2, substrate making alive Vcpn=Vdd ≈ can measure CP electric current I cpn when Vdd0/2.
4. utilize test circuit as claimed in claim 3 to measure the method that integrated circuit stress is degenerated, it is characterized in that:
one, in measurement core circuit inverter, the NBTI stress degeneration step of pMOSFETs is as follows:
(1) measuring by output terminal OUT1 the novel circuit that does not add stress is the output frequency fout of Fresh circuit, is calculated the normal oscillation frequency f0 of core circuit by the divide ratio N of output frequency fout and frequency divider;
(2) on core circuit, apply the NBTI stress of Vstress;
(3) after stress time tstress1, Circnit Layout returns to normal oscillatory regime, oscillation frequency f1(NBTI, the tstress1 of measurement core circuit);
(4) repeating step (2) and (3), measurement core circuit time under NBTI stress is respectively oscillation frequency f2(NBTI, the tstress2 of tstress2, tstress3), f3(NBTI, tstress3);
(5) calculate the frequency change Δ f1(NBTI of core circuit under NBTI stress)=f1(NBTI, tstress1)-f0, Δ f2(NBTI)=f2(NBTI, tstress2)-f0, Δ f3(NBTI)=f3(NBTI, tstress3)-f0;
two, in measurement core circuit inverter, the PBTI stress degeneration step of nMOSFETs is as follows:
(1) measure by output terminal OUT1 the output frequency fout of novel circuit that does not add stress, calculated the normal oscillation frequency f0 of core circuit by the divide ratio N of output frequency fout and frequency divider;
(2) on core circuit, apply the PBTI stress of Vstress;
(3) after stress time tstress1, Circnit Layout returns to normal oscillatory regime, oscillation frequency f1(PBTI, the tstress1 of measurement core circuit);
(4) repeating step (2) and (3), measurement core circuit time under PBTI stress is respectively oscillation frequency f2(PBTI, the tstress2 of tstress2, tstress3), f3(PBTI, tstress3);
(5) calculate the frequency change Δ f1(PBTI of core circuit under PBTI stress)=f1(PBTI, tstress1)-f0, Δ f2(PBTI)=f2(PBTI, tstress2)-f0, Δ f3(PBTI)=f3(PBTI, tstress3)-f0;
three, in measurement core circuit inverter, the HCI stress degeneration step of pMOSFETs is as follows:
(1), measure the output frequency fout of the novel circuit that does not add stress by output terminal OUT1, calculated the normal oscillation frequency f0 of core circuit by the divide ratio N of output frequency fout and frequency divider;
(2) on core circuit, apply the HCI stress of Vstress;
(3) after stress time tstress1, Circnit Layout returns to normal oscillatory regime, oscillation frequency f1(HHI, the tstress1 of measurement core circuit);
(4) repeating step (2) and (3), measurement core circuit time under HHI stress is respectively oscillation frequency f2(HHI, the tstress2 of tstress2, tstress3), f3(HHI, tstress3);
(5) calculate the frequency change Δ f1(HHI of core circuit under HHI stress)=f1(HHI, tstress1)-f0, Δ f2(HHI)=f2(HHI, tstress2)-f0, Δ f3(HHI)=f3(HHI, tstress3)-f0;
four, in measurement core circuit inverter, the HCI stress degeneration step of nMOSFETs is as follows:
(1) measure by output terminal OUT1 the output frequency fout of novel circuit that does not add stress, calculated the normal oscillation frequency f0 of core circuit by the divide ratio N of output frequency fout and frequency divider;
(2) on core circuit, apply the HCI stress of Vstress;
(3) after stress time tstress1, Circnit Layout returns to normal oscillatory regime, oscillation frequency f1(HEI, the tstress1 of measurement core circuit);
(4) repeating step (2) and (3), measurement core circuit time under HEI stress is respectively oscillation frequency f2(HEI, the tstress2 of tstress2, tstress3), f3(HEI, tstress3);
(5) calculate the frequency change Δ f1(HEI of core circuit under HEI stress)=f1(HEI, tstress1)-f0, Δ f2(HEI)=f2(HEI, tstress2)-f0, Δ f3(HEI)=f3(HEI, tstress3)-f0;
five, in measurement core circuit inverter, the dynamic stress degeneration step of CMOSFETs is as follows:
(1) measure by output terminal OUT1 the output frequency fout of novel circuit that does not add stress, calculated the normal oscillation frequency f0 of core circuit by the divide ratio N of output frequency fout and frequency divider;
(2) on core circuit, apply the dynamic stress of Vstress;
(3) after stress time tstress1, Circnit Layout returns to normal oscillatory regime, oscillation frequency f1(Dynamic, the tstress1 of measurement core circuit);
(4) repeating step (2) and (3), measurement core circuit time under dynamic stress is respectively oscillation frequency f2(Dynamic, the tstress2 of tstress2, tstress3), f3(Dynamic, tstress3);
(5) calculate the frequency change Δ f1(Dynamic of core circuit under dynamic stress)=f1(Dynamic, tstress1)-f0, Δ f2(Dynamic)=f2(Dynamic, tstress2)-f0, Δ f3(Dynamic)=f3(Dynamic, tstress3)-f0;
six, in another kind of measurement core circuit inverter, the stress degeneration step of MOSFETs is as follows:
(1) on core circuit, apply respectively NBTI, PBTI, HHI, HEI or the dynamic stress of Vstress;
(2) after stress time tstress1, Circnit Layout returns to normal oscillatory regime, by OUT3 measurement core circuit with reference to difference on the frequency Δ f1(Stress, the tstress1 of circuit RO_ref)=fOUT3;
(3) repeating step (1) and (2), be respectively after tstress2, tstress3 and difference on the frequency Δ f2(Stress with reference to circuit RO_ref by OUT3 measurement core circuit time under various stress, tstress2), Δ f3(Stress, tstress3);
seven, in measurement core circuit inverter, the stress degeneration step of the CP electric current I cpp of pMOSFETs is as follows:
(1) hold by Icpp the CP electric current I cpp0 that measures the novel circuit that does not add stress;
(2) on core circuit, apply respectively NBTI, PBTI, HHI, HEI or the dynamic stress of Vstress;
(3) after stress time tstress1, Circnit Layout returns to the configuration of step (1), is held and is measured CP electric current I cpp1(Stress, tstress1 by Icpp);
(4) repeating step (2) and (3), are respectively CP electric current I cpp2(Stress, the tstress2 after tstress2, tstress3 by Icpp measurement core circuit time under various stress), Icpp3(Stress, tstress3);
(5) calculate the CP curent change Δ Icpp1(Stress of core circuit under various stress)=Icpp1(Stress, tstress1)-Icpp0, Δ Icpp2(Stress)=Icpp2(Stress, tstress2)-Icpp0, Δ Icpp3(Stress)=Icpp3(Stress, tstress3)-Icpp0;
eight, in measurement core circuit inverter, the stress degeneration step of the CP electric current I cpn of nMOSFETs is as follows:
(1) hold by Icpn the CP electric current I cpn0 that measures the novel circuit that does not add stress;
(2) on core circuit, apply respectively NBTI, PBTI, HHI, HEI or the dynamic stress of Vstress;
(3) after stress time tstress1, Circnit Layout returns to the configuration of step (1), is held and is measured CP electric current I cpn1(Stress, tstress1 by Icpn);
(4) repeating step (2) and (3), are respectively CP electric current I cpn2(Stress, the tstress2 after tstress2, tstress3 by Icpn measurement core circuit time under various stress), Icpn3(Stress, tstress3);
(5) calculate the CP curent change Δ Icpn1(Stress of core circuit under various stress)=Icpn1(Stress, tstress1)-Icpn0, Δ Icpn2(Stress)=Icpn2(Stress, tstress2)-Icpn0, Δ Icpn3(Stress)=Icpn3(Stress, tstress3)-Icpn0.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110443476.9A CN102495352B (en) | 2011-12-27 | 2011-12-27 | Multifunctional test circuit of integrated circuit stress degradation and test method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110443476.9A CN102495352B (en) | 2011-12-27 | 2011-12-27 | Multifunctional test circuit of integrated circuit stress degradation and test method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102495352A CN102495352A (en) | 2012-06-13 |
| CN102495352B true CN102495352B (en) | 2014-06-11 |
Family
ID=46187193
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201110443476.9A Expired - Fee Related CN102495352B (en) | 2011-12-27 | 2011-12-27 | Multifunctional test circuit of integrated circuit stress degradation and test method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102495352B (en) |
Families Citing this family (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102590735B (en) * | 2012-02-16 | 2014-10-29 | 复旦大学 | Circuit and method for testing reliability of integrated circuit |
| CN103513173B (en) * | 2012-06-29 | 2016-04-20 | 复旦大学 | Based on BTI proving installation and the method for testing thereof of voltage controlled oscillator |
| CN103576065B (en) * | 2012-07-24 | 2017-05-03 | 中芯国际集成电路制造(上海)有限公司 | Test circuit of transistor threshold voltage |
| CN103576067A (en) * | 2012-07-27 | 2014-02-12 | 中芯国际集成电路制造(上海)有限公司 | Bias voltage temperature instability testing circuit and testing method thereof |
| CN104124230B (en) * | 2013-04-27 | 2017-08-01 | 中芯国际集成电路制造(上海)有限公司 | A kind of test structure and method of testing |
| CN103439644B (en) * | 2013-08-13 | 2015-09-23 | 哈尔滨工业大学 | A kind of SRAM-based FPGA degradation testing system |
| CN104483611B (en) * | 2014-11-24 | 2017-05-24 | 华东师范大学 | Device and method thereof for testing bias temperature instability degrading of MOS (metal oxide semiconductor) device |
| CN104655956B (en) * | 2014-12-08 | 2017-10-24 | 上海大学 | A kind of test device based on multi-functional matrix plate |
| CN107306130B (en) * | 2016-04-18 | 2020-10-09 | 中芯国际集成电路制造(上海)有限公司 | IO receiver |
| CN106597246A (en) * | 2016-11-30 | 2017-04-26 | 上海华力微电子有限公司 | Bias temperature instability testing structure and bias temperature instability testing method |
| CN107202951B (en) * | 2017-06-05 | 2019-08-06 | 中国电子产品可靠性与环境试验研究所 | SoC on piece NBTI degeneration detection system |
| CN108318796B (en) * | 2017-12-12 | 2020-04-10 | 东南大学 | Three-port silicon carbide-based power device interface state testing method |
| CN109975679B (en) * | 2017-12-14 | 2021-06-08 | 中芯国际集成电路制造(上海)有限公司 | BTI performance test circuit of MOSFET and test method based on BTI performance test circuit |
| CN108363861B (en) * | 2018-02-07 | 2021-05-25 | 华东师范大学 | Analysis method and analysis system for NBTI degradation prediction in low-frequency alternating-current stress mode |
| WO2020125506A1 (en) * | 2018-12-21 | 2020-06-25 | Huawei Technologies Co., Ltd. | Complementary ring oscillators to monitor in-situ stress within integrated circuits |
| CN111812485A (en) * | 2020-06-10 | 2020-10-23 | 西安电子科技大学 | Early warning method and circuit for aging failure of integrated circuit |
| CN112834890B (en) * | 2020-12-29 | 2021-11-30 | 北京智芯微电子科技有限公司 | Circuit for detecting NBTI (negative bias temperature instability) degradation of PMOS (P-channel metal oxide semiconductor) device |
| CN112885387A (en) * | 2021-01-19 | 2021-06-01 | 长鑫存储技术有限公司 | Protection circuit and memory |
| US11935579B2 (en) | 2021-01-19 | 2024-03-19 | Changxin Memory Technologies, Inc. | Protection circuit and memory |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6815971B2 (en) * | 2002-11-06 | 2004-11-09 | Taiwan Semiconductor Manufacturing Co., Ltd | Method and apparatus for stress testing integrated circuits using an adjustable AC hot carrier injection source |
| CN101706551A (en) * | 2009-10-30 | 2010-05-12 | 西安电子科技大学 | Testing circuit for forecasting failure of back bias voltage unstability of integrated circuit |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7126365B2 (en) * | 2002-04-16 | 2006-10-24 | Transmeta Corporation | System and method for measuring negative bias thermal instability with a ring oscillator |
-
2011
- 2011-12-27 CN CN201110443476.9A patent/CN102495352B/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6815971B2 (en) * | 2002-11-06 | 2004-11-09 | Taiwan Semiconductor Manufacturing Co., Ltd | Method and apparatus for stress testing integrated circuits using an adjustable AC hot carrier injection source |
| CN101706551A (en) * | 2009-10-30 | 2010-05-12 | 西安电子科技大学 | Testing circuit for forecasting failure of back bias voltage unstability of integrated circuit |
Non-Patent Citations (2)
| Title |
|---|
| J.Keane et al.On-chip reliability monitors for measuring circuit degradation.《Microelectronics Reliablity》.2010,第50卷 |
| On-chip reliability monitors for measuring circuit degradation;J.Keane et al;《Microelectronics Reliablity》;20100831;第50卷;1039－1053 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102495352A (en) | 2012-06-13 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102495352B (en) | Multifunctional test circuit of integrated circuit stress degradation and test method thereof | |
| CN102590735B (en) | Circuit and method for testing reliability of integrated circuit | |
| Keane et al. | An all-in-one silicon odometer for separately monitoring HCI, BTI, and TDDB | |
| US7642864B2 (en) | Circuits and design structures for monitoring NBTI (negative bias temperature instability) effect and/or PBTI (positive bias temperature instability) effect | |
| US8692571B2 (en) | Apparatus and method for measuring degradation of CMOS VLSI elements | |
| US7103861B2 (en) | Test structure for automatic dynamic negative-bias temperature instability testing | |
| US8456247B2 (en) | Monitoring negative bias temperature instability (NBTI) and/or positive bias temperature instability (PBTI) | |
| US7265639B2 (en) | Methods and apparatus for ring oscillator based MOSFET gate capacitance measurements | |
| US7183791B2 (en) | Reliability circuit for applying an AC stress signal or DC measurement to a transistor device | |
| Kim et al. | PBTI/NBTI monitoring ring oscillator circuits with on-chip Vt characterization and high frequency AC stress capability | |
| Karmani et al. | Design and test challenges in Nano-scale analog and mixed CMOS technology | |
| CN110707014A (en) | Method for testing chip process angle offset | |
| US7679394B2 (en) | Power supply noise resistance testing circuit and power supply noise resistance testing method | |
| CN112444732A (en) | Chip aging state monitoring circuit and method, chip and server | |
| US10782330B2 (en) | Semiconductor integrated circuit and signal processing method | |
| Iizuka et al. | All-digital PMOS and NMOS process variability monitor utilizing shared buffer ring and ring oscillator | |
| Arbet et al. | Oscillation-based Built-In Self Test of integrated active analog filters | |
| Núñez et al. | Experimental Characterization of Time-Dependent Variability in Ring Oscillators | |
| US20100174503A1 (en) | Monitoring NFET/PFET Skew in Complementary Metal Oxide Semiconductor Devices | |
| Linder et al. | Separating NBTI and PBTI effects on the degradation of ring oscillator frequency | |
| Bach et al. | Improvements to CBCM (charge-based capacitance measurement) for deep submicron CMOS technology | |
| CN210090563U (en) | Circuit unit for testing grid dynamic capacitance of inverter and test circuit | |
| US12044723B2 (en) | Circuit for temperature stress test for memory chips | |
| Keane et al. | On-chip silicon odometers and their potential use in medical electronics | |
| Olmos et al. | Test mode method and strategy for RF-based fault injection analysis for on-chip relaxation oscillators under EMC standard tests or RFI susceptibility characterization |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20140611 |