CN102487039A - Preparation method of semiconductor device - Google Patents
Preparation method of semiconductor device Download PDFInfo
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- CN102487039A CN102487039A CN2010105736259A CN201010573625A CN102487039A CN 102487039 A CN102487039 A CN 102487039A CN 2010105736259 A CN2010105736259 A CN 2010105736259A CN 201010573625 A CN201010573625 A CN 201010573625A CN 102487039 A CN102487039 A CN 102487039A
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Abstract
The invention discloses a preparation method of a semiconductor device. The preparation method comprises the following steps of: providing a semiconductor substrate on which a metal interconnecting wire is formed; forming a dielectric layer on the surface of the semiconductor substrate; forming a nitrogen doped silicon carbide layer, an oxide layer and a hard mask layer on the surface of the dielectric layer in sequence; carrying out dry etching on the hard mask layer, the oxide layer, the nitrogen doped silicon carbide layer and the dielectric layer so as to form an opening at the position corresponding to the metal interconnecting wire; carrying out wet cleaning on the semiconductor substrate. According to the preparation method, the nitrogen doped silicon carbide layer is used for replacing the traditional Octamethyl cyclotetrasiloxane layer so that the nitrogen doped silicon carbide layer is prevented from being corroded excessively, thereby improving the reliability of the semiconductor device.
Description
Technical field
The present invention relates to integrated circuit and make the field, particularly relate to a kind of manufacturing approach of semiconductor device.
Background technology
Along with the characteristic size of semiconductor device is further dwindled, the RC of interconnection line postpones to become the principal contradiction that influences circuit speed gradually, for improving this point, begins to adopt the process of being made metal interconnected line structure by metallic copper.Compare with traditional aluminium technology, the advantage of process for copper is that its resistivity is lower, and conductivity is better, by its connecting lead wire of processing can keep on an equal basis in addition more do forr a short time under the situation of heavy current bearing capacity, more intensive.In addition, it also has bigger advantage than aluminium technology at aspects such as electromigration, RC delay, reliability and life-spans.
Specifically please refer to Figure 1A～1E, it is the generalized section of each step corresponding construction of the manufacturing approach of existing semiconductor device, and the manufacturing approach of this semiconductor device adopts metallic copper to make metal interconnected line structure usually.
Shown in Figure 1A, at first, the Semiconductor substrate 100 that is formed with metal interconnecting wires 101 is provided.
Shown in Figure 1B, then, form dielectric layer 120 on said Semiconductor substrate 100 surfaces, before forming dielectric layer 120, also can form diffusion impervious layer 110 on Semiconductor substrate 100 surfaces earlier.
Shown in figure 1C, thereafter, form prestox tetrasilane layer (HMBD) 130, oxide layer 140 and hard mask layer 150 successively on said dielectric layer 120 surfaces.Said prestox tetrasilane layer 130 is better with the adhesiveness of dielectric layer 120; But the adhesiveness of itself and hard mask layer 150 is relatively poor; For this reason; Between prestox tetrasilane layer 130 and hard mask layer 150, added oxide layer 140; Said oxide layer 140 all has preferable adhesiveness with prestox tetrasilane layer 130 and hard mask layer 150, and the thickness of said oxide layer 140 is usually between
to
.
Shown in figure 1D; Then; On said hard mask layer 150, form patterning photoresist layer (not shown); And be mask with said patterning photoresist layer, the said hard mask layer of dry etching 150, oxide layer 140, prestox tetrasilane layer 130 are to form patterning hard mask layer 150 ', patterning oxide layer 140 ' and patterning prestox tetrasilane layer 130 '.
Shown in figure 1E; Next; Do mask with patterning hard mask layer 150 ', patterning oxide layer 140 ' jointly with patterning prestox tetrasilane layer 130 ' again; The said dielectric layer 120 of etching is until the surface that exposes diffusion impervious layer 110, to form opening 121 with said metal interconnecting wires 101 corresponding positions.Inevitably; After carrying out dry etch process, with residual polymer arranged on the sidewall of said patterning hard mask layer 150 ' surface and opening 121, this polymer is not expected to form; For this reason; Need the said Semiconductor substrate of wet-cleaned, with residual polymer on the sidewall of removing patterning hard mask layer 150 ' surface and opening 121, the cleaning liquid that said wet clean process is used is generally diluent hydrofluoric acid solution.
Yet; In actual production, find, because said prestox tetrasilane layer 130 is more loose, therefore; Said cleaning liquid is slower to the etch rate of patterning hard mask layer 150 ' and dielectric layer 120; And very fast to the etch rate of patterning prestox tetrasilane layer 130 ', make patterning prestox tetrasilane layer 130 ' by excessive corrosion, cause the sidewall of opening 121 depression (shown in dotted line among Fig. 1 E) to occur.This will cause in the follow-up copper plating process that carries out, and metal is difficult to be filled in this depression, and then cause electro-migration testing to lose efficacy, and influence the reliability of semiconductor device.
Summary of the invention
The present invention provides a kind of manufacturing approach of semiconductor device, avoids depression occurring at wet clean process after-opening sidewall, to improve the reliability of semiconductor device.
For solving the problems of the technologies described above, the present invention provides a kind of manufacturing approach of semiconductor device, comprising: the Semiconductor substrate that is formed with metal interconnecting wires is provided; Form dielectric layer at said semiconductor substrate surface; Form silicon carbide layer, oxide layer and hard mask layer that nitrogen mixes successively on said dielectric layer surface; Silicon carbide layer and dielectric layer that the said hard mask layer of dry etching, oxide layer, nitrogen mix form opening in the position corresponding with said metal interconnecting wires; The said Semiconductor substrate of wet-cleaned.
Optional, in the manufacturing approach of said semiconductor device, the silicon carbide layer that said nitrogen mixes is to utilize the mode of chemical vapour deposition (CVD) to form.The thickness of the silicon carbide layer that said nitrogen mixes is
Optional; In the manufacturing approach of said semiconductor device, said thickness of oxide layer is to utilize the mode of in-situ deposition to form for
said oxide layer.
Optional, in the manufacturing approach of said semiconductor device, the material of said hard mask layer is a titanium nitride, the material of said dielectric layer is to mix the silica of fluorine or the silica of carbon dope.
Optional, in the manufacturing approach of said semiconductor device, before said semiconductor substrate surface forms dielectric layer, also comprise: form diffusion impervious layer at said semiconductor substrate surface.
Optional, in the manufacturing approach of said semiconductor device, after the said Semiconductor substrate of wet-cleaned, also comprise: the said diffusion impervious layer of etching is to expose said semiconductor substrate surface.
Optional, in the manufacturing approach of said semiconductor device, the cleaning liquid that adopts during the said Semiconductor substrate of wet-cleaned is the hydrofluoric acid of dilution.
The silicon carbide layer (NDC layer) that the present invention utilizes nitrogen to mix substitutes traditional prestox tetrasilane layer; Silicon carbide layer and dielectric layer that this nitrogen mixes have good adhesive force property; And the silicon carbide layer that this nitrogen mixes is comparatively fine and close; Its etch rate is slower when carrying out wet clean process, and the silicon carbide layer that can avoid the nitrogen doping has been improved the reliability of semiconductor device by excessive corrosion.
Description of drawings
Figure 1A～1E is the generalized section of each step corresponding construction of the manufacturing approach of existing semiconductor device;
Fig. 2 is the flow chart of the manufacturing approach of the semiconductor device that the embodiment of the invention provided;
Fig. 3 A～3E is the generalized section of each step corresponding construction of the manufacturing approach of the semiconductor device that the embodiment of the invention provided.
Embodiment
Core concept of the present invention is; A kind of manufacturing approach of semiconductor device is provided, and the silicon carbide layer that the manufacturing approach of this semiconductor device utilizes nitrogen to mix substitutes existing prestox tetrasilane layer, and silicon carbide layer and dielectric layer that this nitrogen mixes have good adhesive force property; And the silicon carbide layer that this nitrogen mixes is comparatively fine and close; Its etch rate is slower when carrying out wet clean process, and the silicon carbide layer that can avoid the nitrogen doping has been improved the reliability of semiconductor device by excessive corrosion.
Please refer to Fig. 2, it is the flow chart of the manufacturing approach of the semiconductor device that the embodiment of the invention provided, and the method for this semiconductor device may further comprise the steps:
Step S200 provides the Semiconductor substrate that is formed with metal interconnecting wires;
Step S210 forms dielectric layer at said semiconductor substrate surface;
Step S220 forms silicon carbide layer, oxide layer and hard mask layer that nitrogen mixes successively on the dielectric layer surface;
Step S230, silicon carbide layer and dielectric layer that the said hard mask layer of dry etching, oxide layer, nitrogen mix form opening in the position corresponding with said metal interconnecting wires;
Step S240, the said Semiconductor substrate of wet-cleaned.
To combine generalized section that the manufacturing approach of semiconductor device of the present invention is described in more detail below; The preferred embodiments of the present invention have wherein been represented; Should be appreciated that those skilled in the art can revise the present invention described here, and still realize advantageous effects of the present invention.Therefore, following description is appreciated that extensively knowing to those skilled in the art, and not as limitation of the present invention.
Shown in figure 3A, at first, execution in step S200 provides the Semiconductor substrate 300 that is formed with metal interconnecting wires 301.Said Semiconductor substrate 300 can be the substrate (part that comprises integrated circuit and other elements) of multi layer substrate (silicon substrate that for example, has covering dielectric and metal film), classification substrate, silicon-on-insulator substrate (SOI), epitaxial silicon substrate, section processes.Can be in aluminium, silver, chromium, molybdenum, nickel, palladium, platinum, titanium, tantalum, the copper one or several at the material of said metal interconnecting wires 301, the material of said metal interconnecting wires 301 is preferably used copper.
Shown in figure 3B, then, execution in step S210; Form dielectric layer 320 on said Semiconductor substrate 300 surfaces; Said dielectric layer 320 preferred with dielectric constant less than 2.5 ultra-low dielectric constant material, reducing the parasitic capacitance of metal interconnecting wires, thereby reduce the RC delay; And the interference between the alleviation metal interconnecting wires, and then improve the speed of the operation of device.For example, the material of said dielectric layer 320 is a kind of or its combination of mixing in the silica of silica or carbon dope of fluorine, and it can form through modes such as chemical vapour deposition (CVD)s.
Preferable, before execution in step S210, promptly before forming dielectric layer 320, also can form diffusion impervious layer 310 on Semiconductor substrate 300 surfaces, said dielectric layer 320 covers the surface of diffusion impervious layer 310.Said diffusion impervious layer 310 can be used for preventing metal diffusing in the metal interconnecting wires 301 in dielectric layer 320, and diffusion impervious layer 310 also can prevent in follow-up etching process of carrying out simultaneously, and the metal interconnecting wires 301 in the Semiconductor substrate 300 are etched.The material of said diffusion impervious layer 310 is preferably the carborundum that nitrogen mixes, and the dielectric layer 320 of itself and follow-up formation has good adhesive force property.Certainly, the material of diffusion impervious layer 310 can also be other can barrier metal the material of diffusion, for example, silicon oxynitride.Said diffusion impervious layer 310 can form through modes such as chemical vapour deposition (CVD)s.
Shown in figure 3C, thereafter, execution in step S220 forms silicon carbide layer 330, oxide layer 340 and hard mask layer 350 that nitrogen mixes successively on said dielectric layer 320 surfaces.The silicon carbide layer 330 that said nitrogen mixes is better with the adhesiveness of dielectric layer 320; And the silicon carbide layer 330 that this nitrogen mixes is comparatively fine and close; Its etch rate is slower when carrying out wet clean process, and the silicon carbide layer 330 that can avoid the nitrogen doping is avoided opening sidewalls depression to occur by excessive corrosion.Wherein, The silicon carbide layer 330 that said nitrogen mixes is to utilize the mode of chemical vapour deposition (CVD) to form, and the thickness of the silicon carbide layer that said nitrogen mixes for example is
Wherein, The material of said hard mask layer 350 for example is a titanium nitride; Because the silicon carbide layer 330 that said nitrogen mixes is relatively poor with the adhesiveness of hard mask layer 150; For this reason, between silicon carbide layer 330 that nitrogen mixes and hard mask layer 350, added oxide layer 340, said oxide layer 340 all has preferable adhesiving effect with silicon carbide layer 330 and hard mask layer 350 that nitrogen mixes.
Preferably; The thickness of said oxide layer 340 also has comparatively faster corrosion rate owing to the employed cleaning liquid of follow-up wet clean process to oxide layer for
; Therefore; Compared with prior art; The embodiment of the invention reduces the thickness of oxide layer 340 as much as possible; Thereby avoid it in wet clean process, to be corroded,, farthest reduce the probability that depression appears in oxide layer 340 sidewalls to have under the prerequisite of preferable adhesiving effect at silicon carbide layer that nitrogen is mixed 330 and hard mask layer 350.
In the present embodiment, said oxide layer 340 is to utilize the mode of original position (in suit) deposition to form, and promptly after the silicon carbide layer 330 that deposition nitrogen mixes, directly utilizes this chamber to deposit and oxide layer 340.Utilize the mode of in-situ deposition to form the oxide layer that oxide layer 340 helps forming thinner thickness, reduce the complexity of technology, and can practice thrift the production time, enhance productivity.
Shown in figure 3D; Then; On said hard mask layer 350, form patterning photoresist layer (not shown); And be mask with said patterning photoresist layer, the silicon carbide layer 330 that the said hard mask layer of dry etching 350, oxide layer 340, nitrogen mix forms the silicon carbide layer 330 ' that patterning hard mask layer 350 ', patterning oxide layer 340 ' and patterning nitrogen mix.
Shown in figure 3E; Next; Do mask jointly with patterning hard mask layer 350 ', patterning oxide layer 340 ' and the silicon carbide layer 330 ' that patterning nitrogen mixes again; The said dielectric layer 320 of etching is until the surface that exposes said diffusion impervious layer 310, to form opening 321 with said metal interconnecting wires 301 corresponding positions.
For residual polymer on the sidewall of removing patterning hard mask layer 350 ' surface and opening 321, next, execution in step S240, the said Semiconductor substrate of wet-cleaned.In the present embodiment, the cleaning liquid that uses of said wet clean process is diluent hydrofluoric acid solution.Because the silicon carbide layer 330 that the embodiment of the invention utilizes nitrogen to mix has substituted prestox tetrasilane layer; The silicon carbide layer 330 that this nitrogen mixes is comparatively fine and close; Its etch rate is slower when carrying out wet clean process; The silicon carbide layer that can avoid the nitrogen doping has been improved the reliability of semiconductor device by excessive corrosion.
Optional, after the said Semiconductor substrate of wet-cleaned, the said diffusion impervious layer 310 of etching is to expose said Semiconductor substrate 300 surfaces; Then in opening 321, fill metal (for example copper), to be formed at another metal interconnecting wires that metal interconnecting wires 301 is electrically connected.
Obviously, those skilled in the art can carry out various changes and modification to the present invention and not break away from the spirit and scope of the present invention.Like this, belong within the scope of claim of the present invention and equivalent technologies thereof if of the present invention these are revised with modification, then the present invention also is intended to comprise these changes and modification interior.
Claims (10)
1. the manufacturing approach of a semiconductor device comprises:
The Semiconductor substrate that is formed with metal interconnecting wires is provided;
Form dielectric layer at said semiconductor substrate surface;
Form silicon carbide layer, oxide layer and hard mask layer that nitrogen mixes successively on said dielectric layer surface;
Silicon carbide layer and dielectric layer that the said hard mask layer of dry etching, oxide layer, nitrogen mix form opening in the position corresponding with said metal interconnecting wires;
The said Semiconductor substrate of wet-cleaned.
2. the manufacturing approach of semiconductor device as claimed in claim 1 is characterized in that, the silicon carbide layer that said nitrogen mixes is to utilize the mode of chemical vapour deposition (CVD) to form.
3. the manufacturing approach of semiconductor device as claimed in claim 1; It is characterized in that the thickness of the silicon carbide layer that said nitrogen mixes is
4. according to claim 1 or claim 2 the manufacturing approach of semiconductor device; It is characterized in that said thickness of oxide layer is
5. the manufacturing approach of semiconductor device as claimed in claim 4 is characterized in that, said oxide layer is to utilize the mode of in-situ deposition to form.
6. the manufacturing approach of semiconductor device as claimed in claim 1 is characterized in that, the material of said hard mask layer is a titanium nitride.
7. the manufacturing approach of semiconductor device as claimed in claim 1 is characterized in that, the material of said dielectric layer is to mix the silica of fluorine or the silica of carbon dope.
8. the manufacturing approach of semiconductor device as claimed in claim 1 is characterized in that, before said semiconductor substrate surface forms dielectric layer, also comprises: form diffusion impervious layer at said semiconductor substrate surface.
9. the manufacturing approach of semiconductor device as claimed in claim 8 is characterized in that, after the said Semiconductor substrate of wet-cleaned, also comprises: the said diffusion impervious layer of etching is to expose said semiconductor substrate surface.
10. the manufacturing approach of semiconductor device as claimed in claim 1 is characterized in that, the cleaning liquid that adopts during the said Semiconductor substrate of wet-cleaned is the hydrofluoric acid of dilution.
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| CN2010105736259A CN102487039A (en) | 2010-12-03 | 2010-12-03 | Preparation method of semiconductor device |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103531525A (en) * | 2012-07-02 | 2014-01-22 | 中芯国际集成电路制造(上海)有限公司 | Metal interconnection structure and manufacturing method thereof |
| CN103545196A (en) * | 2012-07-13 | 2014-01-29 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of metal interconnecting wires |
| CN103943551A (en) * | 2013-01-22 | 2014-07-23 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor device |
| CN105405749A (en) * | 2015-11-02 | 2016-03-16 | 株洲南车时代电气股份有限公司 | Method for etching silicon carbide |
| CN109427777A (en) * | 2017-08-30 | 2019-03-05 | 台湾积体电路制造股份有限公司 | Cutting metal gates with sloped sidewall |
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| US20060219660A1 (en) * | 2005-03-31 | 2006-10-05 | Tokyo Electron Limited | Etching method |
| CN101064295A (en) * | 2006-04-30 | 2007-10-31 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and its making method |
| CN101431019A (en) * | 2007-11-08 | 2009-05-13 | 中芯国际集成电路制造(上海)有限公司 | Production method of metal silicide |
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| US20040157453A1 (en) * | 2002-12-31 | 2004-08-12 | Applied Materials, Inc. | Method of forming a low-K dual damascene interconnect structure |
| US20060219660A1 (en) * | 2005-03-31 | 2006-10-05 | Tokyo Electron Limited | Etching method |
| CN101064295A (en) * | 2006-04-30 | 2007-10-31 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and its making method |
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Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103531525A (en) * | 2012-07-02 | 2014-01-22 | 中芯国际集成电路制造(上海)有限公司 | Metal interconnection structure and manufacturing method thereof |
| CN103531525B (en) * | 2012-07-02 | 2016-01-06 | 中芯国际集成电路制造(上海)有限公司 | The manufacture method of metal interconnect structure |
| CN103545196A (en) * | 2012-07-13 | 2014-01-29 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of metal interconnecting wires |
| CN103943551A (en) * | 2013-01-22 | 2014-07-23 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor device |
| CN103943551B (en) * | 2013-01-22 | 2016-12-28 | 中芯国际集成电路制造(上海)有限公司 | A kind of manufacture method of semiconductor device |
| CN105405749A (en) * | 2015-11-02 | 2016-03-16 | 株洲南车时代电气股份有限公司 | Method for etching silicon carbide |
| CN105405749B (en) * | 2015-11-02 | 2019-05-10 | 株洲南车时代电气股份有限公司 | A kind of method of etching silicon carbide |
| CN109427777A (en) * | 2017-08-30 | 2019-03-05 | 台湾积体电路制造股份有限公司 | Cutting metal gates with sloped sidewall |
| CN109427777B (en) * | 2017-08-30 | 2021-08-24 | 台湾积体电路制造股份有限公司 | Cut metal gate with sloped sidewalls |
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