CN102487014B - Semiconductor structure and manufacture method thereof - Google Patents

Semiconductor structure and manufacture method thereof Download PDF

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CN102487014B
CN102487014B CN201010572608.3A CN201010572608A CN102487014B CN 102487014 B CN102487014 B CN 102487014B CN 201010572608 A CN201010572608 A CN 201010572608A CN 102487014 B CN102487014 B CN 102487014B
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layer
drain region
source
contact
grid
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CN102487014A (en
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尹海洲
罗军
朱慧珑
骆志炯
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Institute of Microelectronics of CAS
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Institute of Microelectronics of CAS
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Priority to CN201010572608.3A priority Critical patent/CN102487014B/en
Priority to PCT/CN2011/071350 priority patent/WO2012071813A1/en
Priority to US13/379,658 priority patent/US8642471B2/en
Priority to CN201190000060.3U priority patent/CN202651088U/en
Publication of CN102487014A publication Critical patent/CN102487014A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28185—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66492—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a pocket or a lightly doped drain selectively formed at the side of the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's

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Abstract

The invention provides a manufacture method of a semiconductor structure. The method comprises the following steps: providing a substrate, and forming dummy grid stack, a spacer attached to a sidewall of the dummy grid stack, and a source/drain area at two sides of the dummy grid stack on the substrate, wherein, the dummy grid stack comprises a dummy grid; forming a first contact layer at a surface of the source/drain area; forming an interlayer dielectric layer which covers the first contact layer; removing the dummy grid or the dummy grid stack to form an opening, and filling first conductive material or filling a grid medium layer and the first conductive material in the opening to form a grid stack structure; forming a contact hole in the interlayer dielectric layer, wherein, the contact hole exposes the first contact layer or the first contact layer and partial area of the source/drain area; forming a second contact layer at a surface of the partial area; filling second conductive material in the contact hole to form a contact plug. And the invention provides a semiconductor device. Reducing contact resistance is facilitated.

Description

A kind of semiconductor structure and manufacture method thereof
Technical field
The present invention relates to semiconductor fabrication, relate in particular to a kind of semiconductor structure and manufacture method thereof.
Background technology
Mos field effect transistor (Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET) is a kind of transistor that can be widely used in digital circuit and analog circuit.When the gate dielectric layer of MOSFET consists of high K dielectric material, can effectively reduce grid leakage current, but when initial formation high-K gate dielectric layer, the molecular structure of high-K gate dielectric layer is defect slightly.In order to repair this defect, need at higher temperature (600 ℃-800 ℃), to it, anneal.In addition, high-K gate dielectric layer is annealed and can also be improved transistorized reliability.But, metal silicide layer in transistor can not bear the high K dielectric layer required high temperature of annealing, and wherein, metal silicide layer at high temperature its structure can change, thereby cause the increase of resistance of metal silicide layer rate, and then reduce transistorized performance.
In prior art U.S. Patent application US2007/0141798A1, propose a kind ofly can anneal to high-K gate dielectric layer but do not destroy the method for metal silicide layer, the method step is as follows:
On substrate, form and there is the transistor of sacrificing grid; On substrate, deposit the first interlayer dielectric layer; Remove described sacrifice grid and form gate groove; In described gate groove, deposition forms high k dielectric layer; Described high k dielectric layer is annealed; In described gate groove, deposit the first metal layer; On described the first interlayer dielectric layer and described transistor, deposit the second interlayer dielectric layer; Described in etching, the first interlayer dielectric layer and described the second interlayer dielectric layer to source electrode and drain electrode forms respectively the first contact trench and the second contact trench; In described the first contact trench and described the second contact trench, deposit the second metal level; Described the second metal level is annealed, at described source electrode and drain electrode, form metal silicide layer; And deposit the 3rd metal level and fill described the first contact trench and described the second contact trench.
Owing to forming contact layer (as metal silicide layer) after high K dielectric layer is annealed, so avoided metal silicide layer at high temperature destroyed.
But, although said method can not destroy metal silicide layer when high-K gate dielectric layer is annealed, but the restriction of the method is between contact trench and source/drain region, to form metal silicide layer, region area at source/drain region surface coverage metal silicide is limited, can not reduce fully the contact resistance between this transistorized source/drain region and metal silicide layer thus.Therefore, how to reduce the contact resistance between source/drain region and contact layer (as metal silicide layer), just become problem demanding prompt solution.
Summary of the invention
The object of this invention is to provide a kind of semiconductor structure and manufacture method thereof, be beneficial to the contact resistance reducing between source/drain region and contact layer (as metal silicide layer).
According to an aspect of the present invention, provide a kind of manufacture method of semiconductor structure, the method comprises the following steps:
A) provide substrate, and on described substrate, form pseudo-grid stacking, be attached to the side wall of the stacking sidewall of described pseudo-grid and the source/drain region that is positioned at the stacking both sides of described pseudo-grid, the stacking dummy grid that comprises of wherein said pseudo-grid;
B) in described source/drain region surface forms the first contact layer;
C) form the interlayer dielectric layer that covers described the first contact layer;
D) remove described dummy grid or described pseudo-grid stacking to form opening, in described opening, fill the first electric conducting material or fill gate dielectric layer and described the first electric conducting material, to form grid stacked structure;
E) in described interlayer dielectric layer, form contact hole, the subregion in the first contact layer or described the first contact layer and described source/drain region described in described contact holes exposing;
F) on surface, described subregion, form the second contact layer;
G) in described contact hole, fill the second electric conducting material, form contact plug.
The present invention also proposes a kind of semiconductor structure on the other hand, and this semiconductor structure comprises substrate, source/drain region, grid stacked structure, interlayer dielectric layer, contact plug,
Described grid stacked structure is formed on described substrate, comprises gate dielectric layer and grid;
Described source/drain region is formed among described substrate, and is positioned at described grid stacked structure both sides;
Described interlayer dielectric layer covers described source/drain region;
Described contact plug comprises and is embedded in described interlayer dielectric layer and the second electric conducting material being electrically connected to described source/drain region, wherein:
Between described interlayer dielectric layer and described source/drain region, there is the first contact layer; And
Between described contact plug and described source/drain region, there is the second contact layer.
Compared with prior art, the present invention has the following advantages:
1) in source/drain region surface forms the first contact layer, and form the second contact layer at the first contact layer of contact holes exposing or surface, the subregion in the first contact layer and source/drain region, can be increased in the region area of source/drain region surface coverage contact layer, be beneficial to the contact resistance reducing between source/drain region and contact layer (as metal silicide layer);
2) described the first contact layer has thermal stability under required annealing temperature when forming described grid stacked structure, can under higher annealing temperature (as 850 ℃), still can keep lower resistance, so can adopt high-temperature process in subsequent technique, and be difficult for reducing the performance of semiconductor structure;
3) formation of described the first contact layer, is beneficial to the generation that reduces tubulose defect (piping defect), and then is beneficial to the short circuit that reduces semiconductor structure.
Accompanying drawing explanation
By reading the detailed description that non-limiting example is done of doing with reference to the following drawings, it is more obvious that other features, objects and advantages of the present invention will become:
Fig. 1 is the flow chart of semiconductor structure, in accordance with the present invention manufacture method;
Fig. 2 to Figure 14 is according to a preferred embodiment of the present invention according to the generalized section in each stage of the semiconductor structure of flow manufacturing shown in Fig. 1;
The resistance of the formed nickel-silicide of Ni layer that Figure 15 is deposition different-thickness under different temperatures; And
The resistance of the formed nickel platinum-silicide of NiPt layer that Figure 16 is deposition different-thickness under different temperatures.
In accompanying drawing, same or analogous Reference numeral represents same or analogous parts.
Embodiment
Describe embodiments of the invention below in detail, the example of described embodiment is shown in the drawings.Below by the embodiment being described with reference to the drawings, be exemplary, only for explaining the present invention, and can not be interpreted as limitation of the present invention.
Disclosing below provides many different embodiment or example to be used for realizing different structure of the present invention.Of the present invention open in order to simplify, hereinafter the parts of specific examples and setting are described.Certainly, they are only example, and object does not lie in restriction the present invention.In addition, the present invention can be in different examples repeat reference numerals and/or letter.This repetition is in order to simplify and object clearly, itself do not indicate the relation between discussed various embodiment and/or setting.In addition, the invention provides the example of various specific technique and material, but those skilled in the art can recognize the use of applicability and/or the other materials of other techniques.It should be noted that illustrated parts are not necessarily drawn in proportion in the accompanying drawings.The present invention has omitted the description of known assemblies and treatment technology and technique to avoid unnecessarily limiting the present invention.
Below, in connection with Fig. 2 to Figure 14, to forming the method for semiconductor structure in Fig. 1, describe particularly.
With reference to figure 1 and Fig. 2, in step S101, substrate 100 is provided, and on substrate 100, form pseudo-grid source/drain region 110 stacking, that form side wall 240 and be positioned at the stacking both sides of described pseudo-grid at the stacking sidewall of described pseudo-grid, stacking first grid dielectric layer 210, dummy grid 220 and the cover layer 230 of comprising of wherein said pseudo-grid.
In the present embodiment, substrate 100 comprises silicon substrate (for example silicon wafer).For example, according to the known designing requirement of prior art (P type substrate or N-type substrate), substrate 100 can comprise various doping configurations.In other embodiment, substrate 100 can also comprise other basic semiconductor, for example germanium.For example, or substrate 100 can comprise compound semiconductor (as III-V family material), carborundum, GaAs, indium arsenide.Typically, substrate 100 can have but be not limited to the thickness of about hundreds of micron, for example can be in the thickness range of 400um-800um.
Especially, can in substrate 100, form isolated area, for example shallow trench isolation is from (STI) structure 120, so that the continuous FET device of electricity isolation.
When the pseudo-grid of formation are stacking, first on substrate 100, form first grid dielectric layer 210, in the present embodiment, the material of described first grid dielectric layer 210 can be silica, silicon nitride and be combined to form, and in other embodiments, can be also high K dielectric, for example, HfO 2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al 2o 3, La 2o 3, ZrO 2, a kind of or its combination in LaAlO, its thickness can be 2-10nm; Then, on described first grid dielectric layer 210 by depositing for example Poly-Si, Poly-SiGe, amorphous silicon, and/or, doping or unadulterated silica and silicon nitride, silicon oxynitride, carborundum, even metal forms dummy grid 220, and its thickness can be 10-80nm; Finally; on dummy grid 220, form cover layer 230; for example, by deposited silicon nitride, silica, silicon oxynitride, carborundum and be combined to form; in order to protect the top area of dummy grid 220, prevent that the top area of dummy grid 220 from reacting with the metal level of deposition in the technique of follow-up formation contact layer.By composition, after the sandwich construction of the above-mentioned deposition of etching, form pseudo-grid stacking.In another embodiment, pseudo-grid are stacking can not have first grid dielectric layer 210 yet, but remove pseudo-grid heap poststack in follow-up replacement gate process, forms gate dielectric layer.
Form described pseudo-grid heap poststack, on the stacking sidewall of described pseudo-grid, form side wall 240, for grid is separated.Side wall 240 can be by silicon nitride, silica, silicon oxynitride, carborundum and combination thereof, and/or other suitable materials form.Side wall 240 can have sandwich construction, and for adjacent two-layer, its material can be different.Side wall 240 can be by comprising that deposition-etch technique forms, and its thickness range can be 10nm-100nm, as 30nm, 50nm or 80nm.
Source/drain region 110 is positioned at the stacking both sides of pseudo-grid, can form by inject P type or N-type alloy or impurity in substrate 100, and for example, for PMOS, source/drain region 110 can be the SiGe of P type doping; For NMOS, source/drain region 110 can be the Si of N-type doping.Source/drain region 110 can be formed by the method that comprises photoetching, Implantation, diffusion and/or other appropriate process, utilize common semiconducter process and step, described semiconductor structure is annealed, with the doping in activation of source/drain region 110, annealing can adopt and comprise that other suitable methods such as short annealing, spike annealing form.In the present embodiment, source/drain region 110 is in substrate 100 inside, in some other embodiment, source/drain region 110 can be the source-drain electrode structure by the formed lifting of selective epitaxial growth, and the top of its epitaxial part is higher than the stacking bottom of pseudo-grid (in this specification, the stacking bottom of pseudo-grid of indication means the stacking boundary line with substrate 100 of pseudo-grid).
With reference to figure 1, Fig. 3 and Fig. 4, in step S102, in described source/drain region, 110 upper surfaces form the first contact layer 111, wherein, for silicon-containing substrate, are to form metal silicide layer.Take silicon-containing substrate hereinafter as example is described, contact layer is called to metal silicide layer.Particularly, as shown in Figure 3, substrate 100 described in thin the first metal layer 250 uniform folds of deposition one deck, pseudo-grid are stacking and side wall 240, after annealing, because the first metal layer 250 and the silicon on substrate react, as shown in Figure 4, at described source/drain region 110 upper surfaces, form described the first metal silicide layer 111.Thickness and the material of the first metal layer 250 depositing by selection, can so that formed described the first metal silicide layer 111 under higher temperature (as 850 ℃), still there is thermal stability, can keep lower resistivity, be beneficial to the reduction that reduces the first metal silicide layer 111 resistivity that high annealing causes in follow-up semiconductor structure manufacture process.Wherein, the material of described the first metal layer 250 can comprise the one or any combination in Co, Ni, NiPt.
The CoSi that reacts and form due to Co and Si 2when contact layer is thicker, still have high-temperature stability, if the material that therefore described the first metal layer 250 is selected is Co, the thickness by the formed the first metal layer 250 of Co can be less than 7nm.
With reference to Figure 15, the resistance of the formed nickel-silicide of Ni layer that Figure 15 is deposition different-thickness under different temperatures, its abscissa represents to carry out quick thermal treatment process (rapid thermal processing, RTP) temperature, ordinate represents the resistivity of nickel-silicide, the Ni layer of the different-thickness that different curves deposits while representing to form nickel-silicide.As can be seen from Figure 15, when the temperature of quick thermal treatment process reaches more than 700 ℃, the thickness of plated metal Ni layer is that the resistivity of the formed nickel-silicide of 2-3nm is relatively low.If during the material selection Ni of described the first metal layer 250, the thickness by the formed the first metal layer 250 of Ni is less than 4nm, be preferably 2-3nm, at this moment form the thickness of described the first metal silicide layer 111 the chances are 2 times of described the first metal layer, for example, when the thickness of deposition Ni layer is 4nm, the thickness of the NiSi of formation is probably 8nm.
With reference to Figure 16, the resistance of the formed nickel platinum-silicide of NiPt layer that Figure 16 is deposition different-thickness under different temperatures, Figure 16 consists of three of upper, middle and lower figure, its abscissa all represents to carry out the temperature of quick thermal treatment process, ordinate represents the resistance of nickel platinum-silicide, different curves in upper figure represent that content that described the first metal layer 250 is NiPt and Ni is 86%, the content of Pt is when being 14%, the resistivity of the formed nickel platinum-silicide of NiPt layer of different-thickness; Different curves in middle figure represent that content that described the first metal layer 250 is NiPt and Ni is 92%, the content of Pt is when being 8%, the resistivity of the formed nickel platinum-silicide of NiPt layer of different-thickness; Different curves in figure below represent that content that described the first metal layer 250 is NiPt and Ni is 96%, the content of Pt is when being 4%, the resistivity of the formed nickel platinum-silicide of NiPt layer of different-thickness.As can be seen from Figure 16, when the temperature of quick thermal treatment process reaches more than 700 ℃, in the NiPt layer of deposition Pt content be 4% and the NiPt layer thickness situation that is 2nm under, the resistance of formed nickel platinum-silicide is relatively low.Therefore, if during the material selection NiPt of described the first metal layer 250, the thickness by the formed the first metal layer 250 of NiPt is less than 3nm, and preferably, in NiPt, the content of Pt is less than 5%.
Show after deliberation, select after a kind of or its combined deposition the first metal layer 250 in Co, Ni or NiPt, this semiconductor structure is annealed, form the first metal silicide layer 111 after annealing on source/drain region 110, described the first metal silicide layer 111 comprises CoSi 2, NiSi or Ni (Pt) Si 2-y(wherein, 0 < y < 1) a kind of or its combination in, when its thickness is less than 15nm, preferably be less than 6nm, the first metal silicide layer 111 obtaining has high-temperature stability, can bear the high-temperature thermal annealing up to 850 ℃, that is, pseudo-grid are stacking and to form grid be heat-staple under required annealing temperature (as 700 ℃-800 ℃) when stacking removing for the first metal silicide layer 111 obtaining.Finally by the mode of selective etch, remove and do not participate in the first metal layer 250 that reaction forms the first metal silicide layer 111.
Need emphasize, now, before forming the first contact layer 111, can also be removed to side wall 240 described in small part; Especially at described the first contact layer 111, be under annealing temperature required while forming described grid stacked structure during heat-staple metal silicide layer, due to described the first contact layer 111 by extend further to the leakage zones of extensibility, source of originally carrying described side wall 240 (be LDD, lightly doped drain; In presents, be also considered as the part in source/drain region 110), further expanded the contact area between source/drain region 110 and the first contact layer 111, be beneficial to and further reduce contact resistance.
It should be noted that, when removing whole side wall 240, dummy grid 220 is preferably the material except metal, is beneficial to separated the first metal and the dummy grid that forms the first metal silicide layer 111, keeps as much as possible grid size.
With reference to figure 1 and Fig. 5, in step S103, on described substrate 100, deposit interlayer dielectric layer 300.Described interlayer dielectric layer 300 can pass through the methods such as chemical gaseous phase deposition (CVD), high-density plasma CVD, spin coating and/or other suitable technique and form.The material of described interlayer dielectric layer 300 can comprise silica (USG), the silica (as fluorine silex glass, Pyrex, phosphorosilicate glass, boron-phosphorosilicate glass) of doping, a kind of or its combination in low K dielectrics material (as black diamond, coral etc.).The thickness range of described interlayer dielectric layer 300 can be 40nm-150nm, as 80nm, 100nm or 120nm, and can have sandwich construction (between adjacent two layers, material can be different).
With reference to figure 1, Fig. 6 to Figure 10, in step S104, remove described dummy grid 220 to form opening 260, at interior filling the first electric conducting material of described opening 260, be preferably metal material, form grid stacked structure.
In the present embodiment, carry out replacement gate process.First, with reference to figure 6, to interlayer dielectric layer 300 and the stacking planarization of carrying out of pseudo-grid to expose the upper surface of dummy grid 220, for example, can remove interlayer dielectric layer 300 by the method for chemico-mechanical polishing (CMP), and make the upper surface flush (in presents, term " flushes " in the scope that the difference in height that means between the two allows at fabrication error) of dummy grid 220 and interlayer dielectric layer 300.
Then, remove in the lump dummy grid 220 and first grid dielectric layer 210, expose grid substrate 100 to form opening 260, with reference to figure 7 (b).Can use the mode of wet etching and/or dry etching to remove dummy grid 220 and first grid dielectric layer 210.Wet-etching technology comprises the solution of Tetramethylammonium hydroxide (TMAH), potassium hydroxide (KOH) or other suitable etchings; Dry etch process comprises sulphur hexafluoride (SF 6), hydride and the combination thereof of the carbon such as hydrogen bromide (HBr), hydrogen iodide (HI), chlorine, argon, helium, methane (and chloromethane), acetylene, ethene, and/or other suitable materials.
Deposition gate dielectric layer 270, covers the bottom of opening 260 and the inwall of side wall 240, with reference to figure 8.The material of described gate dielectric layer 270 can be high K dielectric, for example, and HfO 2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al 2o 3, La 2o 3, ZrO 2, a kind of or its combination in LaAlO, its thickness can be 2nm-10nm, as 5nm or 8nm.Described gate dielectric layer 270 can form by the technique of CVD or ald (ALD).Described gate dielectric layer 270 can also have sandwich construction, comprises the plural layer with above-mentioned material.
Form after described gate dielectric layer 270, further anneal, to improve the performance of semiconductor structure, the temperature range of annealing is 600 ℃ to 800 ℃.Because described the first metal silicide layer 111 still has thermal stability when up to 850 ℃, so described gate dielectric layer 270 is annealed and is difficult for causing the rising of described the first metal silicide layer 111 resistivity, the difficult performance that reduces this semiconductor structure.
After annealing, on described gate dielectric layer 270, by depositing the mode of the first electric conducting material, form metal gates 280, with reference to figure 9.For NMOS, described the first electric conducting material can be TaC, TiN, TaTbN, TaErN, TaYbN, TaSiN, HfSiN, MoSiN, RuTa x, NiTa xin a kind of or its combination, for PMOS, described the first electric conducting material can be MoN x, TiSiN, TiCN, TaAlC, TiAlN, TaN, PtSi x, Ni3Si, Pt, Ru, Ir, Mo, HfRu, RuO x; Its thickness can be 10nm-80nm, as 30nm or 50nm.Wherein, metal gates 280 also can have sandwich construction, comprises the plural layer with above-mentioned material.
In other embodiments, when the material of described first grid dielectric layer 210 is high K dielectric, for example, HfO 2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al 2o 3, La 2o 3, ZrO 2, a kind of or its combination in LaAlO, also can only remove described dummy grid 220 to form opening 260, with reference to figure 7 (a).Then, described first grid dielectric layer 210 is carried out to high annealing, with finishing established structure before forming the first electric conducting material, and then formation metal gates 280, wherein, high annealing is identical with the rear performed technique of the described gate dielectric layer 270 of above-mentioned formation with the technique that forms metal gates, does not repeat them here.
Finally, carry out cmp planarizationization and process, make the upper surface flush of described metal gates 280 and interlayer dielectric layer 300, form grid stacked structure, with reference to Figure 10.
With reference to figure 1 and Figure 12, in step S105, on described source/drain region 110, form contact hole 310.In the present embodiment, etching interlayer dielectric layer 300 is until source of exposure/drain region 110 forms contact hole 310, and wherein, the first metal silicide layer 111 can be used as etching barrier layer, controls the etching depth of contact hole 310.
First on interlayer dielectric layer 300 and metal gates 280, covers one deck photoresist layer before etching, to the described photoresist layer composition that exposes, form aperture, correspondence will form the position of contact hole 310.In the present embodiment, use photoetching process interlayer dielectric layer 300 is carried out to etching and stop on the first metal silicide layer 111 as etching barrier layer, to form contact hole 310.Material or polyethylene laurate material that the material of photoresist layer can be vinyl monomer material, contain nitrine quinones, can certainly need to select suitable material according to concrete manufacture.In other embodiments, can use other etching mode, for example, dry etching or wet etching, form contact hole 310.The contact hole 310 forming after etching can have up big and down small pyramidal structure.
In other embodiments, no matter be for the source/drain region of non-lifting or the source/drain region of lifting, when etching stopping is during in the first metal silicide layer 111 as etching barrier layer, can change other etching solutions etching is proceeded in source/drain region, until the bottom of contact hole 310 enters the inside in described source/drain region, thereby further increased the contact area between source/drain region and the second metal silicide layer, reduced the contact resistance between source/drain region and metal silicide layer.
Alternatively, before forming contact hole 310, deposited top layer 400 on interlayer dielectric layer 300 and metal gates 280, with reference to Figure 11.The material of described top layer 400 can be SiN, oxide and compound thereof, by CVD, high-density plasma CVD, spin coating or other suitable methods, is formed on interlayer dielectric layer 300 and metal gates 280.In the subsequent process forming at this semiconductor structure, top layer 400 can be used for protecting metal gates 280 not to be damaged.Now, described quilting material needs different from described inter-level dielectric layer material.For example, in subsequent handling, to interior deposition the second metal level of contact hole 310, form after the second metal silicide layer, while removing unreacted the second metal level by selective etch, top layer 400 can prevent that metal gates 280 is etched effectively.
Form after contact hole 310, remove unreacted photoresist layer.
With reference to figure 1 and Figure 13, in step S106, on described contact holes exposing surface, described source/drain region out, form the second metal silicide layer.Can pass through metal sputtering mode or chemical vapour deposition technique, in the bottom of contact hole 310, form the second metal level.In the present embodiment, the material of described the second metal level can be Ni or NiPt, and its thickness range can be 10nm-25nm, and after reacting with silicon, formed described the second metal silicide layer 112 is for being NiSi or Ni (Pt) Si 2-y.In other embodiments, can adopt other feasible metals as the second metal level.Then, this semiconductor structure is annealed, annealing can adopt and comprise that other suitable methods such as short annealing, spike annealing form, and makes the part that the second metal level of deposition contacts with source/drain region 110 form the second metal silicide layer 112.Because formed the second metal silicide needs not be subjected to the high-temperature process to high-K gate dielectric layer, therefore described the second metal silicide layer does not need to have high high-temp stability, can form second metal silicide layer thicker than the first metal silicide layer, further to reduce contact resistance, for example the scope of the thickness of formed the second metal silicide layer is preferably 15nm-35nm.Then, by the mode of selective etch, remove and do not participate in the second metal level that reaction forms the second metal silicide layer 112.
In other embodiments, for etching interlayer dielectric layer 300 and source/drain region 110, the contact hole 310 of 110 inside, arrival source/drain region that form to expose 110Zhong subregion, described source/drain region, formed the second metal silicide layer of post-depositional the second metal level, covers the bottom of described contact hole 310 and by the partial sidewall of the formed contact hole 310 of described source/drain region 110 expose portion.Wherein, the composition of described the second metal level is identical with thickness and previous embodiment, does not repeat them here.
With reference to figure 1 and Figure 14, last, execution step S107 fills the second electric conducting material in described contact hole 310, is preferably contacting metal, forms contact plug 320.Described contacting metal can be the metal or alloy such as W, TiAl, Al.Alternatively, fill contacting metal in described contact hole 310 before, can pass through the depositing operations such as ALD, CVD, PVD first at the whole inwall of contact hole 310 and bottom deposition one deck lining (not shown), the material of described lining can be Ti, TiN, Ta, TaN or its combination, the scope of its thickness is 5nm-20nm, as 10nm or 15nm.Fill after contacting metal, described contacting metal is carried out to cmp planarization processing, make the upper surface flush of upper surface and the interlayer dielectric layer 300 of contacting metal.
According to the step of conventional semiconductor fabrication process, complete subsequently the manufacture of this semiconductor structure.
After above-mentioned steps completes, in described semiconductor structure, form double layer of metal silicide, be respectively the first metal silicide layer 111 between interlayer dielectric layer 300 and source/drain region 110, and the second metal silicide layer 112 between contact plug 320 and source/drain region 110.Compared with prior art, owing to having increased contact layer (as the first metal silicide layer 111), thereby further reduced the contact resistance between source/drain region and metal silicide layer; In addition, described the first metal silicide layer 111 that the first metal layer 250 by deposition of thin forms, in up to 850 ℃, still there is thermal stability, thereby avoided after forming described the first metal silicide layer 111, when the first grid dielectric layer 210 consisting of high K dielectric or gate dielectric layer 270 are annealed, the increase of described the first metal silicide layer 111 resistivity that cause due to high temperature.Because the combination of the first metal silicide layer 111 and the second metal silicide layer 112 has expanded the contact area of contact plug and source-drain area, so method for making semiconductor provided by the invention, can effectively reduce the contact resistance between source/drain region and contact plug, be beneficial to the performance that improves semiconductor structure.In addition, the formation of the first metal silicide layer 111, can also reduce tubulose defect, effectively reduces semiconductor structure short circuit.
In order more clearly to understand according to the formed semiconductor structure of the manufacture method of above-mentioned semiconductor structure, according to Figure 14, described semiconductor structure is described below.
With reference to Figure 14, Figure 14 has been the profile of the final semiconductor structure forming after the step shown in Fig. 1.In the present embodiment, described semiconductor structure comprises: substrate 100, source/drain region 110, grid stacked structure, interlayer dielectric layer 300 and contact plug 320.Wherein, described source/drain region 110 is formed among described substrate 100; Described grid stacked structure is formed on described substrate 100, and between source/drain region 110, described grid stacked structure comprises gate dielectric layer 270 and metal gates 280, and described metal gates 280 is positioned on described gate dielectric layer 270; Described interlayer dielectric layer 300 covers described source/drain region 110; Described contact plug 320 comprises the contacting metal (i.e. the second electric conducting material) being filled in the contact hole 310 (with reference to Figure 13) that runs through described interlayer dielectric layer 300 and be electrically connected to source/drain region 110.Between described interlayer dielectric layer 300 and described source/drain region 110, there is the first metal silicide layer 111, and have the second metal silicide layer 112 between described contact plug bottom and sidewall and described source/drain region 110.
Described the first metal silicide layer 111 comprises CoSi 2, NiSi or Ni (Pt) Si 2-yin a kind of or its combination, its thickness can be less than 15nm, is preferably less than 6nm; Described the second metal silicide layer 112 comprises NiSi or Ni (Pt) Si 2-yin a kind of, the scope of its thickness can be between 15nm-35nm, the thickness of described the second metal silicide layer 112 is greater than the thickness of described the first metal silicide layer 111.
In another embodiment, source/drain region 110 can be the source-drain electrode structure promoting, that is, the top in source/drain region 110 is higher than the stacking bottom of grid.
In yet another embodiment, no matter for the source/drain region of non-lifting and the source/drain region of lifting, the bottom of contact plug 320 all may extend in source/drain region, thereby the contact area that further increases source/drain region and the second metal silicide layer 112, reduces the contact resistance between source/drain region and metal silicide layer.
Wherein, that in the embodiment of the method that all can form with aforesaid semiconductor structure structure composition, material and the formation method etc. of each several part in each embodiment of semiconductor structure, describes is identical, is not repeating.
Although describe in detail about example embodiment and advantage thereof, be to be understood that in the situation that do not depart from the protection range that spirit of the present invention and claims limit, can carry out various variations, substitutions and modifications to these embodiment.For other examples, when those of ordinary skill in the art should easily understand within keeping protection range of the present invention, the order of processing step can change.
In addition, range of application of the present invention is not limited to technique, mechanism, manufacture, material composition, means, method and the step of the specific embodiment of describing in specification.From disclosure of the present invention, as those of ordinary skill in the art, will easily understand, for the technique, mechanism, manufacture, material composition, means, method or the step that have existed or be about to develop at present later, wherein they carry out identical function or the identical result of acquisition cardinal principle of corresponding embodiment cardinal principle of describing with the present invention, according to the present invention, can apply them.Therefore, claims of the present invention are intended to these technique, mechanism, manufacture, material composition, means, method or step to be included in its protection range.

Claims (19)

1. a manufacture method for semiconductor structure, the method comprises the following steps:
A) provide substrate (100), and at described substrate (100), upper form that pseudo-grid are stacking, the side wall (240) that is attached to the stacking sidewall of described pseudo-grid and the source/drain region (110) that is positioned at the stacking both sides of described pseudo-grid, the stacking dummy grid (220) that comprises of wherein said pseudo-grid;
B) on described source/drain region (110) surface, form the first contact layer (111);
C) form the interlayer dielectric layer (300) that covers described the first contact layer (111);
D) remove described dummy grid (220) or described pseudo-grid stacking to form opening (260), in described opening (260), fill gate dielectric layer (270) and described the first electric conducting material (280), to form grid stacked structure, and anneal at the temperature of 600 ℃-800 ℃;
E) in described interlayer dielectric layer (300), form contact hole (310), described contact hole (310) exposes the subregion of described the first contact layer (111) or described the first contact layer (111) and described source/drain region (110);
F) on surface, described subregion, form the second contact layer (112);
G) in described contact hole (310), fill the second electric conducting material, form contact plug (320);
Wherein, described the first contact layer (111) thickness is less than 15nm, and the thickness of described the second contact layer (112) is greater than the thickness of described the first contact layer (111).
2. method according to claim 1, wherein:
At described step b) in, the step that forms the first contact layer (111) comprises,
On the surface, described source/drain region (110) exposing, form the first metal layer (250), the material of described the first metal layer (250) comprises a kind of or combination in Co, Ni, NiPt;
Carry out the first annealing operation, make described the first metal layer (250) and described source/drain region (110) surface reaction exposing;
Remove unreacted described the first metal layer (250).
3. method according to claim 2, wherein:
If the material of described the first metal layer (250) is Co, the thickness of Co is less than 7nm;
If the material of described the first metal layer (250) is Ni, the thickness of Ni is less than 4nm; And
If the material of described the first metal layer (250) is NiPt, the thickness of NiPt is less than 3nm.
4. method according to claim 2, wherein:
If the material of described the first metal layer (250) is NiPt, in NiPt, the content of Pt is less than 5%.
5. method according to claim 1, the thickness of wherein said the first contact layer (111) is less than 6nm.
6. method according to claim 1, wherein, in described steps d) and described step e) between also perform step i), this step I) comprising:
I) form the top layer (400) that covers described grid stacked structure and described interlayer dielectric layer (300), described top layer (400) material is different from described interlayer dielectric layer (300) material;
Now, at step e) in, while forming contact hole (310), on described grid stacked structure, remain with described top layer (400).
7. method according to claim 1, wherein, described the second contact layer (112) comprises NiSi or Ni (Pt) Si 2-yin a kind of.
8. method according to claim 1, wherein, described step f) comprising:
On the described subregion exposing, form the second metal level;
Carry out the second annealing operation, make described source/drain region (110) surface reaction of described the second metal level and exposure;
Remove unreacted described the second metal level.
9. method according to claim 8, wherein:
The material of described the second metal level comprises a kind of in Ni or NiPt.
10. method according to claim 8 or claim 9, wherein:
The thickness of described the second metal level is in the scope of 10nm to 25nm.
11. methods according to claim 1, wherein said source/drain region (110) are lifting source/drain region.
12. methods according to claim 1, wherein, in described steps d) in, between formation opening (260) and formation grid stacked structure, also comprise:
Carry out the 3rd annealing operation, to repair established structure before forming the first electric conducting material.
13. methods according to claim 1, wherein, are forming the first contact layer (111) before, also comprise: be removed to side wall (240) described in small part.
14. 1 kinds of semiconductor structures, this semiconductor structure comprises substrate (100), source/drain region (110), grid stacked structure, interlayer dielectric layer (300), contact plug (320), wherein:
Described grid stacked structure is formed on described substrate (100), comprises gate dielectric layer (270) and grid (280);
Described source/drain region (110) is formed among described substrate (100), and is positioned at described grid stacked structure both sides;
Described interlayer dielectric layer (300) covers described source/drain region (110);
Described contact plug (320) comprises and is embedded in described interlayer dielectric layer (300) and the second electric conducting material being electrically connected to described source/drain region (110), it is characterized in that:
Described gate dielectric layer (270) is present on the bottom and side of described grid (280);
Between described interlayer dielectric layer (300) and described source/drain region (110), have the first contact layer (111), described the first contact layer thickness is less than 15nm; And
Between described contact plug (320) and described source/drain region (110), have the second contact layer (112), the thickness of described the second contact layer (112) is greater than the thickness of described the first contact layer (111).
15. semiconductor structures according to claim 14, wherein:
Described the second contact layer (112) comprises NiSi or Ni (Pt) Si 2-yin a kind of.
16. semiconductor structures according to claim 14, wherein:
The thickness of described the first contact layer (111) is less than 6nm.
17. semiconductor structures according to claim 14, wherein:
The thickness of described the second contact layer (112) is greater than the thickness of described the first contact layer (111).
18. according to the semiconductor structure described in claim 14 or 17, wherein:
The thickness of described the second contact layer (112) is in the scope of 15nm to 35nm.
19. semiconductor structures according to claim 14, wherein: described contact plug (320) extends to inside, described source/drain region (110).
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Families Citing this family (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102487014B (en) * 2010-12-03 2014-03-05 中国科学院微电子研究所 Semiconductor structure and manufacture method thereof
US20120235244A1 (en) * 2011-03-18 2012-09-20 Institute of Microelectronics, Chinese Academy of Sciences Semiconductor Structure and Method for Manufacturing the Same
CN102842503B (en) * 2011-06-20 2015-04-01 中芯国际集成电路制造(北京)有限公司 Manufacturing method of semiconductor device
KR101952119B1 (en) 2012-05-24 2019-02-28 삼성전자 주식회사 Semiconductor device using metal silicide and fabricating method thereof
CN103515293B (en) * 2012-06-25 2016-03-30 中芯国际集成电路制造(上海)有限公司 A kind of method for the formation of contact hole
CN103545207B (en) * 2012-07-11 2017-07-11 中国科学院微电子研究所 Method, semi-conductor device manufacturing method
US20140048888A1 (en) * 2012-08-17 2014-02-20 Taiwan Semiconductor Manufacturing Company, Ltd. Strained Structure of a Semiconductor Device
US20140073106A1 (en) 2012-09-12 2014-03-13 International Business Machines Corporation Lateral bipolar transistor and cmos hybrid technology
CN103050438B (en) * 2012-12-18 2016-08-03 深圳深爱半导体股份有限公司 The lithographic method of contact hole
US20140306290A1 (en) * 2013-04-11 2014-10-16 International Business Machines Corporation Dual Silicide Process Compatible with Replacement-Metal-Gate
CN104217992B (en) * 2013-06-05 2017-03-01 中芯国际集成电路制造(上海)有限公司 Semiconductor device and forming method thereof
CN104347418B (en) * 2013-08-05 2019-11-01 中芯国际集成电路制造(上海)有限公司 The forming method of MOS transistor
US9153483B2 (en) * 2013-10-30 2015-10-06 Taiwan Semiconductor Manufacturing Company, Ltd. Method of semiconductor integrated circuit fabrication
CN104821277B (en) * 2014-01-30 2018-11-16 中芯国际集成电路制造(上海)有限公司 The forming method of transistor
US10032876B2 (en) 2014-03-13 2018-07-24 Taiwan Semiconductor Manufacturing Company, Ltd. Contact silicide having a non-angular profile
US20150372100A1 (en) * 2014-06-19 2015-12-24 GlobalFoundries, Inc. Integrated circuits having improved contacts and methods for fabricating same
CN105336600B (en) * 2014-08-14 2019-04-19 中国科学院微电子研究所 Form the method and its wet etching mixture formula of metal silicide
KR102254031B1 (en) 2014-10-10 2021-05-20 삼성전자주식회사 Semiconductor device and Method of manufacturing the same
US9496394B2 (en) 2014-10-24 2016-11-15 Globalfoundries Inc. Semiconductor structures with field effect transistor(s) having low-resistance source/drain contact(s)
KR102290538B1 (en) 2015-04-16 2021-08-19 삼성전자주식회사 Semiconductor device and method for manufacturing the same
US9484431B1 (en) * 2015-07-29 2016-11-01 International Business Machines Corporation Pure boron for silicide contact
US11049939B2 (en) 2015-08-03 2021-06-29 Semiwise Limited Reduced local threshold voltage variation MOSFET using multiple layers of epi for improved device operation
CN108028277B (en) * 2015-09-25 2021-12-21 英特尔公司 Semiconductor device contact with increased contact area
US20170194454A1 (en) * 2016-01-06 2017-07-06 International Business Machines Corporation NiPt AND Ti INTERSECTING SILICIDE PROCESS AND STRUCTURE
US20180145096A1 (en) * 2016-11-23 2018-05-24 Semiconductor Energy Laboratory Co., Ltd. Display device and electronic device
US10510851B2 (en) * 2016-11-29 2019-12-17 Taiwan Semiconductor Manufacturing Company, Ltd. Low resistance contact method and structure
US10256143B2 (en) * 2016-12-14 2019-04-09 Taiwan Semiconductor Manufacturing Co., Ltd. Replacement contacts
CN108573923B (en) * 2017-03-07 2021-08-06 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof
CN109390235B (en) * 2017-08-02 2021-11-12 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof
CN110534433B (en) * 2018-05-25 2023-09-22 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof
CN110600369A (en) * 2019-08-09 2019-12-20 长江存储科技有限责任公司 Preparation method of semiconductor device and semiconductor device
US11373696B1 (en) 2021-02-19 2022-06-28 Nif/T, Llc FFT-dram

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1411060A (en) * 2001-09-27 2003-04-16 三菱电机株式会社 Semiconductor device and mfg. method thereof
CN101536176A (en) * 2006-08-31 2009-09-16 先进微装置公司 A transistor having a locally provided metal silicide region in contact areas and a method of forming the transistor
CN202651088U (en) * 2010-12-03 2013-01-02 中国科学院微电子研究所 Semiconductor structure

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000223568A (en) * 1999-02-02 2000-08-11 Mitsubishi Electric Corp Semiconductor device and its fabrication
WO2004097943A1 (en) * 2003-04-28 2004-11-11 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method for manufacturing same
JP4247257B2 (en) * 2006-08-29 2009-04-02 株式会社東芝 Manufacturing method of semiconductor device
JP5070969B2 (en) * 2007-07-20 2012-11-14 ソニー株式会社 Manufacturing method of semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1411060A (en) * 2001-09-27 2003-04-16 三菱电机株式会社 Semiconductor device and mfg. method thereof
CN101536176A (en) * 2006-08-31 2009-09-16 先进微装置公司 A transistor having a locally provided metal silicide region in contact areas and a method of forming the transistor
CN202651088U (en) * 2010-12-03 2013-01-02 中国科学院微电子研究所 Semiconductor structure

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