CN102480225A - Direct voltage supplying device - Google Patents
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- CN102480225A CN102480225A CN2010105758830A CN201010575883A CN102480225A CN 102480225 A CN102480225 A CN 102480225A CN 2010105758830 A CN2010105758830 A CN 2010105758830A CN 201010575883 A CN201010575883 A CN 201010575883A CN 102480225 A CN102480225 A CN 102480225A
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Abstract
The invention provides a direct voltage supplying device which comprises a voltage detecting unit, an enable signal processing unit, a latch unit, a control unit and a voltage conversion unit, wherein the voltage detecting unit is used for receiving and detecting a direct-current input voltage so as to generate an input voltage status signal, the enable signal processing unit is used for receiving the input voltage status signal and an enable signal and determining the state of the enable signal according to the input voltage status signal; when the enable signal is invalid, a latch of the latch unit can enable the enable signal to be in an invalid state, and the control unit is used for receiving the enable signal so as to generate a control signal; when the control signal is valid, the voltage conversion unit is used for receiving and converting the direct-current input voltage into a direct-current output voltage and outputting the direct-current output voltage; and when the control signal is invalid, the voltage conversion unit stops receiving the direct-current input voltage. Thus, when the direct-current input voltage is unstable, a power supply provided for a main circuit of a server is stopped, thereby avoiding unstable power supply from causing the main circuit to generate misoperation, and effectively achieving the protective action.
Description
Technical field
The present invention relates to a kind of voltage protection, and be particularly related to a kind of direct voltage when unstable, can cut off the voltage supply device of supplying DC power source.
Background technology
In general, server (server) system provides operating voltage via power supply unit.And existing power supply unit all is the interchange (alternatingcurrent that receives 100V-230V earlier; AC) voltage; Convert above-mentioned alternating voltage to direct current (direct current through the inner transformer of power supply unit again; DC) voltage (for example 12V) is with the operating voltage as server system.This time, all protections of 12V all were to be made in the power supply unit the inside.
But later trend is that server system no longer provides operating voltage via alternating voltage, but direct voltage (for example 12V) electricity that is directly provided by terminal client directly provides operating voltage.At this moment, server system just can not use power supply unit, but is replaced by a direct current plate (DC board).Yet above-mentioned direct current plate must possess all defencive functions that power supply unit has, just overvoltage protection (over voltage protection, OVP) with under-voltage protection (under voltage protection, UVP).Because the overvoltage protection and the under-voltage protection that how to make the direct current plate also reach power supply unit to be possessed will be problems that the utmost point need solve.
Summary of the invention
The present invention proposes a kind of direct voltage feeding mechanism, comprises voltage detection unit, enable signal processing unit, latch lock unit, control unit and voltage conversion unit.Voltage detection unit receives and detects DC input voitage, and to produce the input voltage status signal, wherein the input voltage status signal is in order to the stable state of indication DC input voitage.The enable signal processing unit couples voltage detection unit, receives input voltage status signal and enable signal, and determines the state of enable signal according to the input voltage status signal; When wherein DC input voitage is stablized; Enable signal is effective, and DC input voitage is when unstable, and enable signal is invalid.Latch lock unit couples the enable signal processing unit, and when enable signal was invalid, latch lock unit breech lock enable signal kept disarmed state.Control unit couples enable signal processing unit and latch lock unit, receives enable signal and produces control signal according to this, and when enable signal was effective, control signal was effective, and when enable signal was invalid, control signal was invalid.Voltage conversion unit couples control unit; When control signal is effective; Voltage conversion unit receives DC input voitage and converts DC input voitage into VD output, and when control signal was invalid, voltage conversion unit was by receiving DC input voitage.
In one embodiment of this invention, above-mentioned voltage detection unit comprises bleeder circuit and comparator.Bleeder circuit receives DC input voitage, and direct voltage is carried out dividing potential drop, to produce voltage division signal.Comparator couples bleeder circuit, and reception is also compared the voltage division signal and first reference voltage signal, to produce the input voltage status signal.
In one embodiment of this invention, above-mentioned bleeder circuit comprises first resistance and second resistance.First termination of first resistance is received DC input voitage, and second end of first resistance produces voltage division signal.First end of second resistance couples second end of first resistance, and its second end couples earth terminal.
In one embodiment of this invention, the positive input terminal of above-mentioned comparator receives voltage division signal, and the negative input end of comparator receives first reference voltage signal.
In one embodiment of this invention, the positive input terminal of above-mentioned comparator receives first reference voltage signal, and the negative input end of comparator receives voltage division signal.
In one embodiment of this invention, above-mentioned enable signal processing unit comprises the first transistor and voltage pull-up circuit.The gate terminal of the first transistor receives the input voltage status signal, and the source terminal of the first transistor couples earth terminal.The voltage pull-up circuit couples the drain electrode end of the first transistor, and when wherein DC input voitage was stablized, not conducting of the first transistor made enable signal effective, and DC input voitage is when unstable, and the first transistor conducting makes enable signal invalid.
In one embodiment of this invention, above-mentioned voltage pull-up circuit comprises the 3rd resistance, first electric capacity and the 4th resistance.First end of the 3rd resistance couples DC input voitage, and second end of the 3rd resistance couples the drain electrode end of the first transistor, and receives enable signal.First end of first electric capacity couples second end of the 3rd resistance, and second end of first electric capacity couples earth terminal.First end of the 4th resistance couples second end of the 3rd resistance, and second end of the 4th resistance couples earth terminal.
In one embodiment of this invention, above-mentioned latch lock unit comprises the delay cell and first switch element.The input of delay cell receives second reference voltage signal, in order to postpone second reference voltage signal, to produce the delay voltage signal.First switch element couples delay cell; Receive and according to delay voltage signal and enable signal, and whether determine the breech lock enable signal, wherein when enable signal is invalid; First switch element starts with breech lock enable signal maintenance disarmed state; When enable signal was invalid, first switch did not start, and then latch lock unit is failure to actuate.
In one embodiment of this invention, above-mentioned delay cell comprises the 5th resistance and second electric capacity.First termination of the 5th resistance is received second reference voltage signal, and second end of the 5th resistance produces the delay voltage signal.First end of second electric capacity couples second end of the 5th resistance, and second end of second electric capacity couples earth terminal.
In one embodiment of this invention, above-mentioned first switch element comprises transistor seconds and the 3rd transistor.The drain electrode end receive delay voltage signal of transistor seconds, the source terminal of transistor seconds couples earth terminal, and the gate terminal of transistor seconds receives enable signal.The 3rd transistorized gate terminal couples the drain electrode end of transistor seconds, and the 3rd transistor drain end couples the gate terminal of transistor seconds, and the 3rd transistorized source terminal couples earth terminal.
In one embodiment of this invention, above-mentioned voltage conversion unit comprises second switch unit and voltage conversion circuit.The second switch unit couples control unit, when control signal is effective, and the second switch cell conduction; DC input voitage transmits via the second switch unit; When control signal was invalid, second switch not conducting of unit made voltage conversion unit end the reception DC input voitage.Voltage conversion circuit couples the second switch unit, when the second switch cell conduction, receives DC input voitage, and converts DC input voitage into VD output.
In one embodiment of this invention, above-mentioned second switch unit comprises the 4th transistor.The 4th transistorized gate terminal receives control signal, and the 4th transistor drain termination is received DC input voitage, and the 4th transistorized source terminal determines whether transmit DC input voitage by the 4th transistorized source terminal according to the state of control signal.
In one embodiment of this invention, above-mentioned direct voltage feeding mechanism also comprises the enable signal generation unit.The enable signal generation unit couples the enable signal processing unit, in order to produce enable signal.
The present invention detects DC input voitage by voltage detection unit, to produce the input voltage status signal, in order to the stable state of indication DC input voitage.Then, the enable signal processing unit decides the state of enable signal according to the input voltage status signal.Afterwards, utilize latch lock unit when enable signal is invalid, the breech lock enable signal to be keeping disarmed state, and makes enable signal can not changed.Then, control unit is controlled voltage conversion unit according to enable signal and produce control signal, whether receives and changes DC input voitage with decision and convert the main circuit that VD is given server to.Thus, when DC input voitage is unstable, stop to provide the power supply of the main circuit of server, cause main circuit to produce misoperation to avoid unsettled power supply, and reach the effect of protection effectively.
For letting the above-mentioned feature and advantage of the present invention can be more obviously understandable, hereinafter is special lifts embodiment, and conjunction with figs. elaborates as follows.
Description of drawings
Fig. 1 is the block diagram of voltage supply device of the direct current plate of one embodiment of the invention.
Fig. 2 is the detailed circuit diagram of voltage supply device of the direct current plate of Fig. 1.
Fig. 3 is another detailed circuit diagram of voltage supply device of another direct current plate of Fig. 1.
The main element symbol description
100: the direct voltage feeding mechanism
110: voltage detection unit
120: the enable signal processing unit
130: latch lock unit
140: control unit
150: voltage conversion unit
160: the enable signal generator
210,310: bleeder circuit
220,320: comparator
230,330: the voltage pull-up circuit
240,340: delay cell
250,260,350,360: switch element
270,370: voltage conversion circuit
R1-R6: resistance
C1-C3: electric capacity
M1-M4: transistor
VDD: DC input voitage
VD1: voltage division signal
VS1: input voltage status signal
VS2: delay voltage signal
Vref1, Vref2: reference voltage signal
GND: earth terminal
VE: enable signal
CS: control signal
V0: VD
Embodiment
Fig. 1 is the direct voltage feeding mechanism of one embodiment of the invention.The direct voltage feeding mechanism of present embodiment is applicable to server.Please with reference to Fig. 1, direct voltage feeding mechanism 100 comprises voltage detection unit 110, enable signal processing unit 120, latch lock unit 130, control unit 140 and voltage conversion unit 150.
Thus; The direct voltage feeding mechanism 100 of present embodiment can be when DC input voitage VDD plays pendulum; Stop to provide the power supply of the main circuit of server, cause main circuit to produce misoperation to avoid unsettled power supply, and reach the effect of protection effectively.
In addition, the direct voltage feeding mechanism 100 of present embodiment also comprises enable signal generator 160.Enable signal generator 160 couples enable signal processing unit 120, gives enable signal processing unit 120 in order to produce enable signal VE.Wherein, enable signal VE for example when the motherboard (not shown) is connected to direct voltage feeding mechanism 100, is produced by enable signal generator 160, or when mainboard starting, is produced according to starting-up signal and with its conversion by enable signal generator 160.
Below, will lift than detail circuits direct voltage feeding mechanism 100 will be described.
Fig. 2 is the detailed circuit diagram of the direct voltage feeding mechanism 100 of Fig. 1.Please with reference to Fig. 2, voltage detection unit 110 comprises bleeder circuit 210 and comparator 220.Bleeder circuit 210 receives DC input voitage VDD, and DC input voitage VDD is carried out dividing potential drop, to produce voltage division signal VD1.Wherein, bleeder circuit 210 comprises resistance R 1 and R2.First termination of resistance R 1 is received DC input voitage VDD, and second end of resistance R 1 produces voltage division signal VD1.First end of resistance R 2 couples second end of resistance R 1, and second end of resistance R 2 couples earth terminal GND.That is bleeder circuit 210 produces voltage division signal VD1 with DC input voitage VDD via after resistance R 1 and the R2 dividing potential drop.
Comparator 220 couples bleeder circuit 210, and reception is also compared voltage division signal VD1 and reference voltage signal Vref1, to produce input voltage status signal VS1.In the present embodiment; The first input end of comparator 220 (for example being positive input terminal) receives voltage division signal VD1; Second input of comparator 220 (for example being negative input end) receives reference voltage signal Vref1, and the output of comparator 220 produces input voltage status signal VS1.
Enable signal processing unit 120 comprises transistor M1 and voltage pull-up circuit 230.The gate terminal of transistor M1 receives input voltage status signal VS1, and the source terminal of transistor M1 couples earth terminal GND.Wherein, transistor M1 can be a nmos pass transistor.
Voltage pull-up circuit 230 couples the drain electrode end of transistor M1, receives enable signal VE, and according to transistor M1 whether conducting determine the state of enable signal VE.For instance, when DC input voitage VDD was stable state, promptly input voltage status signal VS1 was low accurate position of logic " 0 " and the gate terminal that is sent to transistor M1; Make not conducting of transistor M1; Then voltage pull-up circuit 230 can remain on the accurate position of high logic " 1 " with enable signal VE, and then enable signal VE is effectively, when DC input voitage VDD is labile state; Be that input voltage status signal VS1 is the accurate position of high logic " 1 " and is sent to transistor M1, make transistor M1 conducting.At this moment, because transistor M1 conducting makes enable signal VE be pulled low to the low accurate position of logic " 0 ", then enable signal VE is invalid.
In addition, voltage pull-up circuit 230 comprises resistance R 3 and R4 and capacitor C 1.First end of resistance R 3 couples DC input voitage VDD, and second end of resistance R 3 couples the drain electrode end of transistor M1, and receives enable signal VE.First end of capacitor C 1 couples second end of resistance R 3, and second end of capacitor C 1 couples earth terminal GND.First end of resistance R 4 couples second end of resistance R 3, and second end of resistance R 4 couples earth terminal GND.
Switch element 250 couples delay cell 240; Receive and according to delay voltage signal VS2 and enable signal VE; And whether determine breech lock enable signal VE, wherein when enable signal VE is invalid, switch element 250 starts with breech lock enable signal VE and keeps disarmed state.In addition, switch element 250 comprises transistor M2 and M3.The drain electrode end receive delay voltage signal VS2 of transistor M2, the source terminal of transistor M2 couples earth terminal GND, and the gate terminal of transistor M2 receives enable signal VE.The gate terminal of transistor M3 couples the drain electrode end of transistor M2, and the drain electrode end of transistor M3 couples the gate terminal of transistor M2, and the source terminal of transistor M3 couples earth terminal GND.
In addition, switch element 260 comprises transistor M4.The gate terminal of transistor M4 receives control signal CS, and the drain electrode end of transistor M4 receives DC input voitage VDD, and transistor M4 determines whether transmit DC input voitage VDD by the source terminal of transistor M4 according to the state of control signal CS.
In the integrated circuit action, at first, after the resistance R 1 and R2 dividing potential drop of DC input voitage VDD via bleeder circuit 210, produce voltage division signal VD1, and input to the first input end (positive input terminal) of comparator 220.Then, when the first input end (positive input terminal) of comparator 220 received voltage division signal VD1, the reference voltage signal Vref1 that can receive with second input (negative input end) of comparator 220 compared.
In general, when DC input voitage VDD was normal and stable work (that is overvoltage (over voltage) state does not take place), the voltage division signal VD1 that bleeder circuit 210 is produced can be less than reference voltage signal Vref1.Therefore, when the voltage of voltage division signal VD1 during less than reference voltage signal Vref1, the output of comparator 220 can produce the input voltage status signal VS1 of the low accurate position of logic " 0 ".Then, the input voltage status signal VS 1 that will hang down the accurate position of logic " 0 " is sent to the gate terminal of the transistor M1 of enable signal processing unit 120, makes not conducting of transistor M1.Because not conducting of transistor M1, voltage pull-up circuit 230 can be adjusted into the accurate position of high logic " 1 " with the enable signal VE that it received, and is sent to gate terminal and the control unit 140 of the transistor M2 of latch lock unit 130 respectively.
Because reference voltage signal Vref 2 postpones via delay cell 240; Therefore; The enable signal VE of the accurate position of high logic " 1 " can go on foot the gate terminal that be sent to transistor M2 than the delay voltage signal VS 2 Zao one that delay cell 240 is produced, and makes transistor M2 conducting.Because transistor M2 conducting; Therefore the gate terminal of transistor M 3 can couple earth terminal GND, makes transistor M 3 not conductings, and then latch lock unit 130 can't generation effect (being that latch lock unit 130 is failure to actuate); And making enable signal VE still be the accurate position of high logic " 1 ", VE is effective for the expression enable signal.
Then, when control unit 140 receives the enable signal VE of the accurate position of high logic " 1 ", can produce the gate terminal of the control signal CS of the accurate position of high logic " 1 " according to this, make transistor M4 conducting to transistor M4.Because transistor M4 conducting, voltage conversion circuit 270 can receive DC input voitage VDD via the source terminal of transistor M4, and converts DC input voitage VDD into VD V0, with the main circuit that offers server to operate.
In addition, in case DC input voitage VDD produces shake, make voltage division signal VD1 also shake thereupon, and produce overvoltage condition.Therefore, when the voltage of voltage division signal VD1 during greater than reference voltage signal Vref1, the output of comparator 220 can produce the input voltage status signal VS1 of the accurate position of high logic " 1 ".Then, the input voltage status signal VS1 of the accurate position of high logic " 1 " is sent to the gate terminal of the transistor M1 of enable signal processing unit 120, makes transistor M1 conducting.Because transistor M1 conducting; Earth terminal GND can be through transistor M1 output; Make voltage pull-up circuit 230 that the enable signal VE that it received is adjusted into the low accurate position of logic " 0 ", and be sent to gate terminal and the control unit 140 of the transistor M2 of latch lock unit 130 respectively.
At this moment, the gate terminal of transistor M2 can receive the enable signal VE of the accurate position of low logic " 0 ", makes not conducting of transistor M2.Because not conducting of transistor M2; The delay voltage signal VS2 that makes delay cell 240 produced can be sent to the gate terminal of transistor M3; And, make that latch lock unit 130 is that the low accurate position of logic " 0 " is to keep disarmed state with enable signal VE breech lock with transistor M3 conducting.Afterwards, control unit 140 receives the enable signal VE of the accurate position of low logic " 0 ", then produces the control signal CS of the low accurate position of logic " 0 " according to this, and control signal CS is sent to the gate terminal of transistor M4, makes not conducting of transistor M4.Because not conducting of transistor M4,270 of voltage conversion circuits can't receive DC input voitage VDD through transistor M4, and make voltage conversion unit 150 by receiving DC input voitage VDD, are supplied to the power supply of the main circuit of server with cut-out.Thus, the direct voltage feeding mechanism 100 of present embodiment can be when overvoltage condition takes place in DC input voitage VDD, and breech lock overvoltage condition, and cut-out effectively is supplied to the power supply of main circuit, and then reaches the effect of protection main circuit.
In addition, in the present embodiment, enable signal processing unit 120 also comprises filter circuit 280, in order to receive input voltage status signal VS1, with the noise among the filtering input voltage status signal VS1.And filter circuit 280 comprises resistance R 6 and capacitor C 3, and it is then as shown in Figure 2 that it couples relation, so repeat no more at this.
In addition, Fig. 3 is the detailed circuit diagram of another direct voltage feeding mechanism of Fig. 1.The execution mode of the voltage detection unit 110 of Fig. 3, enable signal processing unit 120, latch lock unit 130, control unit 140, voltage conversion unit 150, enable signal generator 160 can be with reference to the voltage detection unit 110 of Fig. 2, enable signal processing unit 120, latch lock unit 130, control unit 140, voltage conversion unit 150 execution mode with enable signal generator 160, so repeat no more at this.And Fig. 3 and Fig. 2 difference are: the first input end of the comparator 220 of Fig. 2 is a positive input terminal; Second input of comparator 220 is a negative input end; And the first input end of the comparator 320 of Fig. 3 is a negative input end, and second input of comparator 320 is a positive input terminal.
In the integrated circuit action, at first, after the resistance R 1 and R2 dividing potential drop of DC input voitage VDD via bleeder circuit 310, produce voltage division signal VD1, and input to the first input end (negative input end) of comparator 320.Then, when the first input end (negative input end) of comparator 320 received voltage division signal VD1, the reference voltage signal Vref1 that can receive with second input (positive input terminal) of comparator 320 compared.
In general, when DC input voitage VDD was normal and stable work (that is low-voltage (under voltage) state does not take place), the voltage division signal VD1 that bleeder circuit 310 is produced can be greater than reference voltage signal Vref1.Therefore, when the voltage of voltage division signal VD1 during less than reference voltage signal Vref1, the output of comparator 320 can produce the input voltage status signal VS1 of the low accurate position of logic " 0 ".Then, the input voltage status signal VS1 that will hang down the accurate position of logic " 0 " is sent to the gate terminal of the transistor M1 of enable signal processing unit 120, makes not conducting of transistor M1.Because not conducting of transistor M1, voltage pull-up circuit 230 can be adjusted into the accurate position of high logic " 1 " by the enable signal VE that it is received, and is sent to gate terminal and the control unit 140 of the transistor M2 of latch lock unit 130 respectively.
Because reference voltage signal Vref2 postpones via delay cell 340, therefore, the intelligent signal VE of the accurate position of high logic " 1 " can go on foot the gate terminal that be sent to transistor M2 than the delay voltage signal VS2 that delay cell 340 is produced Zao one, makes transistor M2 conducting.Because transistor M2 conducting, so the gate terminal of transistor M3 can couple earth terminal GND, makes not conducting of transistor M3, and latch lock unit 130 can't the generation effect, and makes enable signal VE still be the accurate position of high logic " 1 ", and VE is effective for the expression enable signal.
Then, when control unit 140 receives the enable signal VE of the accurate position of high logic " 1 ", can produce the gate terminal of the control signal CS of the accurate position of high logic " 1 " according to this, make transistor M4 conducting to transistor M4.Because transistor M4 conducting, voltage conversion circuit 370 can receive DC input voitage VDD via the source terminal of transistor M4, and converts DC input voitage VDD into VD V0, with the main circuit that offers server to operate.
In addition, in case DC input voitage VDD produces shake, make voltage division signal VD1 also shake thereupon, and produce low-voltage state.Therefore, when the voltage of voltage division signal VD1 during greater than reference voltage signal Vref1, the output of comparator 320 can produce the input voltage status signal VS1 of the accurate position of high logic " 1 ".Then, the input voltage status signal VS1 of the accurate position of high logic " 1 " is sent to the gate terminal of the transistor M1 of enable signal processing unit 120, makes transistor M1 conducting.Because transistor M1 conducting; Earth terminal GND can be through transistor M1 output; Make voltage pull-up circuit 330 that the enable signal VE that it received is adjusted into the low accurate position of logic " 0 ", and be sent to gate terminal and the control unit 140 of the transistor M2 of latch lock unit 130 respectively.
At this moment, the gate terminal of transistor M2 can receive the enable signal VE of the accurate position of low logic " 0 ", makes not conducting of transistor M2.Because not conducting of transistor M2; The delay voltage signal VS2 that makes delay cell 340 produced can be sent to the gate terminal of transistor M 3; And, make that latch lock unit 130 is that the low accurate position of logic " 0 " is to keep disarmed state with enable signal VE breech lock with transistor M3 conducting.Afterwards, control unit 140 receives the enable signal VE of the accurate position of low logic " 0 ", then produces the control signal CS of the low accurate position of logic " 0 " according to this, and control signal CS is sent to the gate terminal of transistor M4, makes not conducting of transistor M4.Because not conducting of transistor M4,370 of voltage conversion circuits can't receive DC input voitage VDD through transistor M4, and make voltage conversion unit 150 by receiving DC input voitage VDD, are supplied to the power supply of the main circuit of server with cut-out.Thus, the direct voltage feeding mechanism 100 of present embodiment can be when low-voltage state takes place in DC input voitage VDD, and breech lock low-voltage state, and cut-out effectively is supplied to the power supply of main circuit, and then reaches the effect of protection main circuit.
In sum, present embodiment detects DC input voitage by voltage detection unit, to produce the input voltage status signal, in order to the stable state of indication DC input voitage.Then, the enable signal processing unit decides the state of enable signal according to the input voltage status signal.Afterwards, utilize latch lock unit when enable signal is invalid, the breech lock enable signal to be keeping disarmed state, and makes that the accurate position of logic of enable signal can not changed.Then, control unit is controlled voltage conversion unit according to enable signal and produce control signal, whether receives and changes DC input voitage with decision and convert the main circuit that VD is given server to.Thus; Present embodiment is when DC input voitage unstable (for example overvoltage condition or low-voltage state); Stop to provide the power supply of the main circuit of server, cause main circuit to produce misoperation to avoid unsettled power supply, and reach the effect of protection effectively.
Though the present invention discloses as above with embodiment, so it is not in order to limiting the present invention, any under those of ordinary skill in the technical field, when can doing a little change and retouching, and do not break away from the spirit and scope of the present invention.
Claims (13)
1. a direct voltage feeding mechanism comprises;
One voltage detection unit receives and detects a direct current input voltage, and to produce an input voltage status signal, wherein this input voltage status signal is in order to indicate the stable state of this DC input voitage;
One activation signal processing unit; Couple this voltage detection unit, receive this an input voltage status signal and an activation signal, and determine the state of this enable signal according to this input voltage status signal; When wherein this DC input voitage is stablized; This enable signal is effective, and when this DC input voitage was unstable, this enable signal was invalid;
One latch lock unit couples this enable signal processing unit, and when this enable signal was invalid, this enable signal of this latch lock unit breech lock kept disarmed state;
One control unit couples this enable signal processing unit and this latch lock unit, receives this enable signal and produces a control signal according to this, and this control signal is effective when this enable signal is effective, and this control signal is invalid when this enable signal is invalid; And
One voltage conversion unit; Couple this control unit; When this control signal is effective; This voltage conversion unit receives this DC input voitage and converts this DC input voitage into direct current output voltage output, and when this control signal was invalid, this voltage conversion unit was by receiving this DC input voitage.
2. direct voltage feeding mechanism according to claim 1, wherein this voltage detection unit comprises:
One bleeder circuit receives this DC input voitage, and this direct voltage is carried out dividing potential drop, to produce a voltage division signal;
One comparator couples this bleeder circuit, receives and relatively this voltage division signal and one first reference voltage signal, to produce this input voltage status signal.
3. direct voltage feeding mechanism according to claim 2, wherein this bleeder circuit comprises:
One first resistance, its first termination is received this DC input voitage, and its second end produces this voltage division signal; And
One second resistance, its first end couples second end of this first resistance, and its second end couples earth terminal.
4. direct voltage feeding mechanism according to claim 2, wherein the positive input terminal of this comparator receives this voltage division signal, and the negative input end of this comparator receives this first reference voltage signal.
5. direct voltage feeding mechanism according to claim 2, wherein the positive input terminal of this comparator receives this first reference voltage signal, and the negative input end of this comparator receives this voltage division signal.
6. direct voltage feeding mechanism according to claim 1, wherein this enable signal processing unit comprises:
One the first transistor, its gate terminal receives this input voltage status signal, and its source terminal couples earth terminal; And
One voltage pull-up circuit couples the drain electrode end of this first transistor, receives this enable signal; And according to this first transistor whether conducting determine the state of this enable signal, when wherein this DC input voitage is stablized, this not conducting of the first transistor; Make this enable signal effective; When this DC input voitage was unstable, this first transistor conducting made this enable signal invalid.
7. direct voltage feeding mechanism according to claim 6, wherein this voltage pull-up circuit comprises:
One the 3rd resistance, its first end couples this DC input voitage, and its second end couples the drain electrode end of this first transistor, and receives this enable signal;
One first electric capacity, its first end couples second end of the 3rd resistance, and its second end couples earth terminal; And
One the 4th resistance, its first end couples second end of the 3rd resistance, and its second end couples earth terminal.
8. direct voltage feeding mechanism according to claim 1, wherein this latch lock unit comprises:
One delay cell, its input receive one second reference voltage signal, and postpone this second reference voltage signal, to produce the delay voltage signal;
One first switch element couples this delay cell, receives and according to this delay voltage signal and this enable signal; And whether determine this enable signal of breech lock; Wherein when this enable signal was invalid, this first switch element started with this enable signal maintenance disarmed state of breech lock, when this enable signal is effective; This first switch element does not start, and then this latch lock unit is failure to actuate.
9. direct voltage feeding mechanism according to claim 8, wherein this delay cell comprises:
One the 5th resistance, its first termination is received this second reference voltage signal, and its second end produces this delay voltage signal; And
One second electric capacity, its first end couples second end of the 5th resistance, and its second end couples earth terminal.
10. direct voltage feeding mechanism according to claim 8, wherein this first switch element comprises:
One transistor seconds, its drain electrode end receives this delay voltage signal, and its source terminal couples earth terminal, and its gate terminal receives this enable signal; And
One the 3rd transistor, its gate terminal couples the drain electrode end of this transistor seconds, and its drain electrode end couples the gate terminal of this transistor seconds, and its source terminal couples earth terminal.
11. direct voltage feeding mechanism according to claim 1, wherein this voltage conversion unit comprises:
One second switch unit; Couple this control unit, when this control signal is effective, this second switch cell conduction; This DC input voitage transmits via this second switch unit; When this control signal was invalid, this second switch not conducting of unit made this voltage conversion unit by receiving this DC input voitage; And
One voltage conversion circuit couples this second switch unit, when this second switch cell conduction, receives this DC input voitage, and converts this DC input voitage into this VD output.
12. direct voltage feeding mechanism according to claim 11, wherein this two switch element comprises:
One the 4th transistor, its gate terminal receives this control signal, and its drain electrode end receives this DC input voitage, and the 4th transistor determines whether transmit this DC input voitage by its source terminal according to the state of this control signal.
13. direct voltage feeding mechanism according to claim 1 also comprises:
One activation signal generation unit couples this enable signal processing unit, in order to produce this enable signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010575883.0A CN102480225B (en) | 2010-11-30 | 2010-11-30 | Direct voltage supplying device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010575883.0A CN102480225B (en) | 2010-11-30 | 2010-11-30 | Direct voltage supplying device |
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| Publication Number | Publication Date |
|---|---|
| CN102480225A true CN102480225A (en) | 2012-05-30 |
| CN102480225B CN102480225B (en) | 2014-03-12 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201010575883.0A Expired - Fee Related CN102480225B (en) | 2010-11-30 | 2010-11-30 | Direct voltage supplying device |
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| CN103532526A (en) * | 2013-10-22 | 2014-01-22 | 北京兆易创新科技股份有限公司 | Voltage conversion circuit and voltage conversion method |
| CN104065256A (en) * | 2013-03-18 | 2014-09-24 | 力林科技股份有限公司 | AC-DC conversion circuit and starting method thereof |
| CN104599707A (en) * | 2013-10-31 | 2015-05-06 | 飞思卡尔半导体公司 | SRAM with embedded ROM |
| CN107449953A (en) * | 2016-05-31 | 2017-12-08 | 群光电能科技股份有限公司 | Input voltage outage detection device and there is its power supply unit |
| CN110445374A (en) * | 2018-05-03 | 2019-11-12 | 广达电脑股份有限公司 | Voltage band logical enable circuit |
| CN113722253A (en) * | 2020-05-25 | 2021-11-30 | 瑞昱半导体股份有限公司 | Port control device |
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| US20070002661A1 (en) * | 2005-06-29 | 2007-01-04 | Yi-Shan Chu | Protection circuit of a memory module and the method thereof |
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| US6118675A (en) * | 1998-10-07 | 2000-09-12 | Stmicroelectronics S.R.L. | Method and apparatus for controlling power transfer in a flyback converter by modulating the power switch off time during transient conditions |
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| CN104065256A (en) * | 2013-03-18 | 2014-09-24 | 力林科技股份有限公司 | AC-DC conversion circuit and starting method thereof |
| CN104065256B (en) * | 2013-03-18 | 2017-04-12 | 力林科技股份有限公司 | AC-DC conversion circuit and starting method thereof |
| CN103532526A (en) * | 2013-10-22 | 2014-01-22 | 北京兆易创新科技股份有限公司 | Voltage conversion circuit and voltage conversion method |
| CN103532526B (en) * | 2013-10-22 | 2016-05-18 | 北京兆易创新科技股份有限公司 | Voltage conversion circuit and voltage conversion method |
| CN104599707A (en) * | 2013-10-31 | 2015-05-06 | 飞思卡尔半导体公司 | SRAM with embedded ROM |
| CN104599707B (en) * | 2013-10-31 | 2019-03-29 | 恩智浦美国有限公司 | SRAM with Embedded ROM |
| CN107449953A (en) * | 2016-05-31 | 2017-12-08 | 群光电能科技股份有限公司 | Input voltage outage detection device and there is its power supply unit |
| CN107449953B (en) * | 2016-05-31 | 2020-01-07 | 群光电能科技股份有限公司 | Input voltage power-off detection device and power supply with same |
| CN110445374A (en) * | 2018-05-03 | 2019-11-12 | 广达电脑股份有限公司 | Voltage band logical enable circuit |
| CN110445374B (en) * | 2018-05-03 | 2020-08-07 | 广达电脑股份有限公司 | Voltage band-pass enabling circuit |
| CN113722253A (en) * | 2020-05-25 | 2021-11-30 | 瑞昱半导体股份有限公司 | Port control device |
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| CN102480225B (en) | 2014-03-12 |
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