CN102479726B - Manufacturing method of semiconductor packaging component - Google Patents
Manufacturing method of semiconductor packaging component Download PDFInfo
- Publication number
- CN102479726B CN102479726B CN201010566822.8A CN201010566822A CN102479726B CN 102479726 B CN102479726 B CN 102479726B CN 201010566822 A CN201010566822 A CN 201010566822A CN 102479726 B CN102479726 B CN 102479726B
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- China
- Prior art keywords
- chip
- making
- semiconductor package
- aligning plate
- plate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 25
- 238000004519 manufacturing process Methods 0.000 title abstract description 10
- 238000004806 packaging method and process Methods 0.000 title abstract description 9
- 238000003825 pressing Methods 0.000 claims abstract description 4
- 238000000034 method Methods 0.000 claims description 34
- 239000000463 material Substances 0.000 claims description 25
- 238000005538 encapsulation Methods 0.000 claims description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 4
- 229910052802 copper Inorganic materials 0.000 claims description 4
- 239000010949 copper Substances 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- 239000002904 solvent Substances 0.000 claims description 3
- 239000011148 porous material Substances 0.000 abstract 3
- 239000012528 membrane Substances 0.000 description 12
- 238000006073 displacement reaction Methods 0.000 description 7
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000004090 dissolution Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 230000010354 integration Effects 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 241000218202 Coptis Species 0.000 description 1
- 235000002991 Coptis groenlandica Nutrition 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 238000012797 qualification Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
- Wire Bonding (AREA)
Abstract
The invention discloses a manufacturing method of a semiconductor packaging component, comprising the following steps: providing an aligning plate with a plurality of open pores, wherein the aligning plate is provided with aligning marks corresponding to the open pores; arranging chips at positions corresponding to the open pores on the aligning plate through the aligning marks; pressing the aligning plate with the chips and a bearing plate of which one surface is provided with a soft layer so that the chips are embedded in the soft layer of the bearing plate; and removing the aligning plate. The positions of the chips can be confirmed through the aligning marks on the aligning plate, and therefore, the precision of the positions of the chips is improved.
Description
Technical field
The present invention relates to a kind of method for making of semiconductor package part, particularly a kind of method for making of semiconductor package part of the setting accuracy that promotes chip.
Background technology
Flourish along with electronic industry, electronic product also marches toward multi-functional, high performance R&D direction gradually.Base plate for packaging in order to bearing semiconductor chip includes routing type base plate for packaging, chip size packages (CSP) substrate and covers brilliant substrate (FCBGA) etc. at present, for example: chip is connect and is placed on base plate for packaging, and conductive projection or gold thread are suitably set between this chip and base plate for packaging, this chip is electrically connected on this base plate for packaging.
And, high workload power multi-functional for reaching, and for meeting the package requirements of the high degree of integration of semiconductor package part (integration) and microminiaturized (miniaturization), then develop embedding bury type packaging part, be about to the packaged type of chip buried base plate.Referring to Figure 1A to 1C, is No. 2008/0012144 United States Patent (USP) and the 7th, the method for making of the semiconductor package part of 189, No. 596 disclosed existing wafer-level chip scale package of United States Patent (USP) (Wafer Level Chip Scale Package, WLCSP).
As shown in Figure 1A and 1A ', on four corners of a loading plate 10, be provided with alignment mark (alignment mark) K, and form glued membrane 11 on this loading plate 10, by this alignment mark K respectively, a plurality of chips 12 with electronic pads 120 are located on this loading plate 10, to make respectively this chip 12 arrays rows establish, and this electronic pads 120 is located on this glued membrane 11.As shown in Figure 1B, at this glued membrane 11 and respectively form encapsulation material 14 on this chip 12.As shown in Figure 1 C, remove this loading plate 10 and glued membrane 11, to expose outside this electronic pads 120.
Yet, the shortcoming of above-mentioned manufacture method is chip to be pasted on glued membrane and fixing mode with acting surface, often because being heated in manufacture process, glued membrane 11 there is flexible problem, cause sticky chip 12 positions that are placed on glued membrane 11 to be subjected to displacement, whether the position that now cannot confirm each chip 12 is correct, thereby affects follow-up circuit rerouting (Redistribution layer, RDL) manufacture process, make circuit cannot effectively be electrically connected this electronic pads 120, and reduce the rate of finished products of product.
Therefore, how to overcome the variety of problems of above-mentioned prior art, real is current target to be solved.
Summary of the invention
For overcoming the many disadvantages of prior art, the invention provides a kind of method for making of semiconductor package part, comprising: provide an aligning plate with a plurality of perforates, and this aligning plate is provided with the corresponding respectively alignment mark of this perforate; By this alignment mark respectively, in this aligning plate, the corresponding respectively position of this perforate arranges chip; This is provided with the aligning plate of chip and the loading plate that a surface has soft layer pressing, to make this chip embed in the soft layer of this loading plate; And remove this aligning plate.
In aforesaid method for making, the material of this loading plate is silicon or copper, and this soft layer is encapsulation material, dry film or an increasing layer dielectric film.
In aforesaid method for making, this alignment mark is positioned at the peritreme of this perforate.
In aforesaid method for making, between this loading plate and this soft layer, can be provided with fractal film (release tape).Therefore can pass through this fractal film, to remove easily this loading plate.
In aforesaid method for making, can chip be arranged in this aligning plate by adhesion material.In addition, this adhesion material can the peritreme of the pre-formed perforate in this aligning plate on.And when removing this aligning plate, preferably remove in the lump this adhesion material.The mode of removing again this adhesion material can be by this adhesion material of dissolution with solvents.
Aforesaid method for making further can be included in after this chip embedding bury enters this soft layer, first solidifies this soft layer, then removes this aligning plate.
As from the foregoing, the method for making of semiconductor package part of the present invention, by chip is located in aligning plate, but not on the glued membrane of prior art, be not subjected to displacement therefore chip can not be heated to stretch with glued membrane, then by chip buried soft layer, the material that makes to adhere also cannot drive chip to produce displacement, thereby can not affect follow-up circuit rerouting (RDL) manufacture process, make circuit can effectively be electrically connected chip, with the rate of finished products of improving product.
Moreover, by the alignment mark in aligning plate, can confirm the position of chip, thereby promote the accuracy of chip position.
Accompanying drawing explanation
Figure 1A to 1C is the generalized section of the method for making of existing semiconductor package part; Figure 1A ' is the top view of Figure 1A; And
The generalized section of the method for making that Fig. 2 A to 2E is semiconductor package part of the present invention; Fig. 2 A ' is the top view of Fig. 2 A, and Fig. 2 D ' and 2E ' are another embodiment of Fig. 2 D and 2E.
Main element symbol description
10,23 loading plates
11 glued membranes
12,22 chips
120 electronic padses
14 encapsulation materials
20 aligning plate
200 perforates
21 adhesion materials
230 fractal films
24 soft layers
K, M alignment mark.
Embodiment
By particular specific embodiment, embodiments of the present invention are described below, those skilled in the art can understand other advantages of the present invention and effect easily by content disclosed in the present specification.
Notice, the structure that the appended accompanying drawing of this specification illustrates, ratio, size etc., equal contents in order to coordinate specification to disclose only, understanding and reading for those skilled in the art, not in order to limit the enforceable qualifications of the present invention, therefore the technical essential meaning of tool not, the adjustment of the modification of any structure, the change of proportionate relationship or size, not affecting under the effect that the present invention can produce and the object that can reach, all should still drop on disclosed technology contents and obtain in the scope that can contain.Meanwhile, in this specification, quote as " one " and " on " etc. term, also understanding for ease of narration only, but not in order to limit the enforceable scope of the present invention, the change of its relativeness or adjustment, under without essence change technology contents, when being also considered as the enforceable category of the present invention.
Refer to Fig. 2 A to 2E, disclosed the method for making of semiconductor package part of the present invention.
As shown in Fig. 2 A and 2A ', one aligning plate 20 with a plurality of perforates 200 is provided, and this aligning plate 20 is provided with and is positioned at the respectively alignment mark of the peritreme of this perforate 200 (alignment mark) M, for example, at the diagonally opposing corner of each perforate 200, all there is this alignment mark M.
As shown in Figure 2 B, in the peritreme of the perforate 200 of this aligning plate 20, form the adhesion material 21 of multiple spot shape, but with this profile, be not limited.
As shown in Figure 2 C, by the corresponding adhesion material 21 around of this perforate 200 respectively, by chip 22 respectively this perforate 200 and being located in this aligning plate 20 of correspondence respectively.
As shown in Figure 2 D, this is provided with the aligning plate 20 of chip 22 and the loading plate 23 that a surface has soft layer 24 pressing, to make respectively this chip 22 embed completely in this soft layer 24; Solidify again this soft layer 24, to make respectively this chip 22 be fixed in this soft layer 24.
In the present embodiment, can be according to design or the demand of packaging part, select the material of loading plate 23, for example silicon or selection copper make this loading plate 23 as heat sink, and this soft layer 24 can be encapsulation material (molding compound), dry film (dry film) or increases the dielectric materials such as layer dielectric film (Ajinomoto Build-up Film, ABF).
As shown in Figure 2 E, can remove those adhesion materials 21 by dissolution with solvents, to remove this aligning plate 20, to expose respectively this chip 22.In the present embodiment, this aligning plate 20 can be soaked in acetone solution, acetone is flowed between this aligning plate 20 and this loading plate 23, the adhesion material 21 dissolving each other to dissolve this and acetone, and can utilize ultrasonic wave vibration accelerate dissolution.
In subsequent manufacturing processes, can carry out circuit rerouting (Redistribution layer, RDL) manufacture process; If this loading plate 23 is silicon wafer, the function that can provide support, to prevent warpage; If this loading plate 23 is copper coin, the function that not only can provide support to be to prevent warpage, and has the function of heat radiation.
The present invention is by this chip 22 is arranged in this aligning plate 20, but not on the glued membrane of prior art, therefore this chip 22 can be with glued membrane flexible not being subjected to displacement of being heated.Moreover, by this chip 22 respectively, imbed this soft layer 24, make this adhesion material 21 also cannot drive respectively this chip 22 to produce displacements.
Therefore, by the method for making of this case, this chip 22 can not produce displacement, thereby can not affect follow-up circuit rerouting (RDL) manufacture process, makes circuit can effectively be electrically connected respectively this chip 22, with the rate of finished products of improving product.
In addition, by the alignment mark M in this aligning plate 20 and perforate 200, can confirm respectively the respectively position of this chip 22, thereby promote the respectively accuracy of the position of this chip 22.
In another embodiment, as shown in Fig. 2 D ', between this loading plate 23 and this soft layer 24, there is fractal film 230.Then,, as shown in Fig. 2 E ', first remove this aligning plate 20 and adhesion material 21, then by this fractal film 230, to remove this loading plate 23, and expose respectively this chip 22.
In sum, the method for making of semiconductor package part of the present invention, is located in this aligning plate by this chip, again by this chip buried this soft layer, to guarantee that chip can not produce displacement, thereby can not affect follow-up circuit rerouting (RDL) manufacture process, with the rate of finished products of improving product.
Above-described embodiment is in order to illustrative principle of the present invention and effect thereof, but not for limiting the present invention.Any those skilled in the art all can, under spirit of the present invention and category, modify to above-described embodiment.So the scope of the present invention, should be as listed in claims scope.
Claims (11)
1. a method for making for semiconductor package part, comprising:
Provide an aligning plate with a plurality of perforates, and this aligning plate is provided with the corresponding respectively alignment mark of this perforate;
By respectively this alignment mark in this aligning plate, in this aligning plate, the corresponding respectively position of this perforate arranges chip, and wherein, respectively this chip is positioned at the top of respectively this perforate;
This is provided with the aligning plate of chip and the loading plate that a surface has soft layer pressing, to make this chip embed in the soft layer of this loading plate; And
Remove this aligning plate.
2. the method for making of semiconductor package part according to claim 1, is characterized in that, the material of this loading plate is one of them of silicon and copper.
3. the method for making of semiconductor package part according to claim 1, is characterized in that, this alignment mark is positioned at the peritreme of this perforate.
4. the method for making of semiconductor package part according to claim 1, is characterized in that, this soft layer is for encapsulation material, dry film and increase layer one of them of dielectric film (ABF).
5. the method for making of semiconductor package part according to claim 1, is characterized in that, between this loading plate and this soft layer, is provided with fractal film.
6. the method for making of semiconductor package part according to claim 5, is characterized in that, after being further included in this aligning plate of removal, by this fractal film, to remove this loading plate.
7. the method for making of semiconductor package part according to claim 1, is characterized in that, by adhesion material, chip is arranged in this aligning plate.
8. the method for making of semiconductor package part according to claim 7, is characterized in that, in the peritreme of the pre-formed perforate in this aligning plate of this adhesion material.
9. the method for making of semiconductor package part according to claim 7, is characterized in that, when removing this aligning plate, removes in the lump this adhesion material.
10. the method for making of semiconductor package part according to claim 9, is characterized in that, by this adhesion material of removal of solvents.
The method for making of 11. semiconductor package parts according to claim 1, is characterized in that, is further included in after this chip embedding bury enters this soft layer, solidifies this soft layer, then removes this aligning plate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010566822.8A CN102479726B (en) | 2010-11-26 | 2010-11-26 | Manufacturing method of semiconductor packaging component |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010566822.8A CN102479726B (en) | 2010-11-26 | 2010-11-26 | Manufacturing method of semiconductor packaging component |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102479726A CN102479726A (en) | 2012-05-30 |
| CN102479726B true CN102479726B (en) | 2014-01-22 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201010566822.8A Expired - Fee Related CN102479726B (en) | 2010-11-26 | 2010-11-26 | Manufacturing method of semiconductor packaging component |
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| Country | Link |
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| CN (1) | CN102479726B (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1763937A (en) * | 2004-10-19 | 2006-04-26 | 宏齐科技股份有限公司 | Wafer-level photoelectric semiconductor assembling structure and its manufacturing method |
| CN1925152A (en) * | 2005-08-30 | 2007-03-07 | 全懋精密科技股份有限公司 | Carrying structure for electron element |
| CN101488462A (en) * | 2008-01-15 | 2009-07-22 | 南茂科技股份有限公司 | Modulated multi-die package construction and method thereof |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6964881B2 (en) * | 2002-08-27 | 2005-11-15 | Micron Technology, Inc. | Multi-chip wafer level system packages and methods of forming same |
| TWI345276B (en) * | 2007-12-20 | 2011-07-11 | Chipmos Technologies Inc | Dice rearrangement package structure using layout process to form a compliant configuration |
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2010
- 2010-11-26 CN CN201010566822.8A patent/CN102479726B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1763937A (en) * | 2004-10-19 | 2006-04-26 | 宏齐科技股份有限公司 | Wafer-level photoelectric semiconductor assembling structure and its manufacturing method |
| CN1925152A (en) * | 2005-08-30 | 2007-03-07 | 全懋精密科技股份有限公司 | Carrying structure for electron element |
| CN101488462A (en) * | 2008-01-15 | 2009-07-22 | 南茂科技股份有限公司 | Modulated multi-die package construction and method thereof |
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| Publication number | Publication date |
|---|---|
| CN102479726A (en) | 2012-05-30 |
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Granted publication date: 20140122 Termination date: 20211126 |