CN102479712A - 一种双栅氧半导体器件制造方法 - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 107
- 230000009977 dual effect Effects 0.000 title claims abstract description 44
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 30
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 60
- 238000000034 method Methods 0.000 claims abstract description 56
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 48
- 230000003647 oxidation Effects 0.000 claims abstract description 41
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 41
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 31
- 238000005516 engineering process Methods 0.000 claims abstract description 26
- 239000011248 coating agent Substances 0.000 claims abstract description 16
- 238000000576 coating method Methods 0.000 claims abstract description 16
- 125000004433 nitrogen atom Chemical group N* 0.000 claims abstract description 14
- 238000005468 ion implantation Methods 0.000 claims abstract description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 40
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 37
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 29
- 238000002955 isolation Methods 0.000 claims description 29
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 29
- 230000015572 biosynthetic process Effects 0.000 claims description 10
- 238000005530 etching Methods 0.000 claims description 5
- 238000000151 deposition Methods 0.000 claims description 3
- 239000012774 insulation material Substances 0.000 claims description 3
- 238000002347 injection Methods 0.000 abstract description 3
- 239000007924 injection Substances 0.000 abstract description 3
- 239000010410 layer Substances 0.000 description 192
- 150000002500 ions Chemical class 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 230000002950 deficient Effects 0.000 description 3
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- 239000011241 protective layer Substances 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000673 Indium arsenide Inorganic materials 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 125000004429 atom Chemical group 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000012467 final product Substances 0.000 description 1
- VTGARNNDLOTBET-UHFFFAOYSA-N gallium antimonide Chemical compound [Sb]#[Ga] VTGARNNDLOTBET-UHFFFAOYSA-N 0.000 description 1
- WPYVAWXEWQSOGY-UHFFFAOYSA-N indium antimonide Chemical compound [Sb]#[In] WPYVAWXEWQSOGY-UHFFFAOYSA-N 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 238000010301 surface-oxidation reaction Methods 0.000 description 1
- OCGWQDWYSQAFTO-UHFFFAOYSA-N tellanylidenelead Chemical compound [Pb]=[Te] OCGWQDWYSQAFTO-UHFFFAOYSA-N 0.000 description 1
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Abstract
本发明实施例公开了一种双栅氧半导体器件制造方法,包括:在半导体晶片表面上依次通过涂布光刻胶、曝光、显影步骤形成厚栅氧层区域的光刻胶图形;以厚栅氧层区域的光刻胶图形为掩模、通过离子注入工艺向薄栅氧层区域注入氮原子,形成氮注入层;去除半导体晶片表面上的光刻胶;采用热氧化工艺在半导体晶片上的表面一次性形成厚栅氧层与薄栅氧层。本实施例提供的方案,相对比与现有技术,能够减少一次热氧化制程,所以能够简化工艺流程,降低生产成本,并提高生产效率。
Description
技术领域:
本发明涉及半导体器件制造技术领域,尤其涉及一种双栅氧半导体器件制造方法。
背景技术:
双栅氧半导体器件中包括一个源极、一个漏极和两个栅极,其中两个栅极互相独立,且两个栅极下的栅氧层的厚度不同,以满足不同应用场景的需求。例如:厚栅氧层一侧用于作为输入或输出的高压器件,薄栅氧层的一侧用于作为数字-逻辑运算的低压器件。上述双栅氧半导体器件的特性使其可以用于作为高频放大器、混频器、解调器或增益控制放大器等,因此,双栅氧半导体器件在大规模集成电路中得到了广泛的应用。
现有的双栅氧半导体器件制造工艺通常包括以下步骤:通过热氧化工艺在半导体晶片表面形成厚栅氧层;在厚栅氧层区域表面上依次通过涂布光刻胶、曝光、显影步骤形成厚栅氧层区域的光刻胶图形;以厚栅氧层区域的光刻胶图形为掩模、通过刻蚀工艺去除薄栅氧层区域的厚栅氧层;在去除厚栅氧层后的区域通过热氧化工艺形成薄栅氧层。
然而,上述现有的双栅氧半导体器件制造工艺存在以下缺陷:其需要用过两次热氧化制程才能分别形成厚栅氧层和薄栅氧层,因此,其工艺流程复杂,致使双栅氧半导体器件的生产成本较高,生产效率较低。
发明内容
为解决上述技术问题,本发明的目的在于提供一种双栅氧半导体器件制造方法,以解决现有技术的双栅氧半导体器件制造工艺存在的工艺流程复杂、生产成本较高和生产效率较低的缺陷。
为解决上述问题,本发明实施例提供了如下技术方案:
一种双栅氧半导体器件制造方法,包括:
在半导体晶片表面上依次通过涂布光刻胶、曝光、显影步骤形成厚栅氧层区域的光刻胶图形;
以厚栅氧层区域的光刻胶图形为掩模、通过离子注入工艺向薄栅氧层区域注入氮原子,形成氮注入层;
去除半导体晶片表面上的光刻胶;
采用热氧化工艺在半导体晶片表面一次性形成厚栅氧层与薄栅氧层。
优选的,
在所述涂布光刻胶之前,还包括:
在半导体晶片表面形成氧化硅层;
在形成栅氧层之前,向薄栅氧层区域注入氮原子之后,还包括:
去除所述氧化硅层。
优选的,
所述氧化硅层通过淀积工艺形成。
优选的,
所述氧化硅层的厚度为150~300埃。
优选的,
在形成所述氧化硅层之后,还包括:
进行离子注入工艺在半导体晶片中形成阱区。
优选的,
在形成所述氧化硅层之后,涂布光刻胶之前,还包括:
在氧化硅层表面上淀积形成氮化硅层;
在氮化硅层中形成局部场氧化隔离区域的图形;
以氮化硅层为掩模,进行氧化形成局部场氧化隔离,以划分厚栅氧层区域和薄栅氧层区域;
去除所述氮化硅层。
优选的,
在形成所述氧化硅层之后,涂布光刻胶之前,还包括:
在氧化硅层表面上淀积形成氮化硅层;
在氮化硅层中形成浅槽隔离区域的图形;
以氮化硅层为掩模,进行刻蚀工艺形成浅槽隔离,以划分厚栅氧层区域和薄栅氧层区域;
采用绝缘材质填充所述浅槽隔离;
去除所述氮化硅层。
与现有技术相比,上述技术方案具有以下优点:
应用本发明实施例所提供的技术方案,所述双栅氧半导体器件制造过程中,栅氧层形成之前,在设定的薄栅氧层区域中通过离子注入工艺注入氮原子,形成氮注入层,使后续通过热氧化工艺在半导体晶片表面形成栅氧层时,由于氮注入层会降低半导体晶片表面的氧化速率,而没有氮注入层的半导体晶片表面的氧化速率正常,因此,通过一次热氧化制程即可以实现:在有氮注入层区域的半导体晶片表面形成薄栅氧层,在没有氮注入层区域的半导体晶片表面形成厚栅氧层。因此,本实施例提供的方案,相对比与现有技术,能够减少一次热氧化制程,所以能够简化工艺流程,降低生产成本较高并提高生产效率。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案,下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图仅仅是本发明的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他的附图。
图1为本发明实施例一提供的双栅氧半导体器件制造方法流程示意图;
图2为形成厚栅氧层的光刻胶图形后的双栅氧器件结构示意图;
图3为形成氮注入层后的双栅氧半导体器件结构示意图;
图4为去除半导体晶片表面上的光刻胶后的双栅氧半导体器件结构示意图;
图5为形成栅氧层后的双栅氧半导体器件结构示意图;
图6为本发明实施例二提供的表面形成氧化硅层后的器件半导体器件结构示意图;
图7为包括氧化硅层的双栅氧半导体器件在形成氮注入层时的结构示意图;
图8为形成阱区之后的双栅氧半导体器件结构示意图;
图9为本发明实施例三提供的形成氮化硅层之后的双栅氧半导体器件结构示意图;
图10为形成局部场氧化隔离区域图形之后的双栅氧半导体器件结构示意图;
图11为形成局部场氧化隔离区域之后的双栅氧半导体器件结构示意图;
图12为本发明实施例三提供双栅氧半导体器件结构示意图。
其中,图2至图12中的图标分别表示:
201为半导体晶片,202为薄栅氧层区域和厚栅氧层区域之间的隔离区,203为厚栅氧层区域的光刻胶图形,204为预设的薄栅氧层区域,205为预设的厚栅氧层区域,206为氮原子注入层,207为薄栅氧层,208为厚栅氧层,209为氧化硅层,210为阱区,211为氮化硅层,212为局部场氧化隔离区域的图形。
具体实施方式
正如背景技术部分所述,现有的双栅氧半导体器件制造工艺中其需要用过两次热氧化制程才能分别形成厚栅氧层和薄栅氧层,因此,其存在工艺流程复杂,双栅氧半导体器件的生产成本较高,生产效率较低等缺陷。
为此,本发明实施例提供了一种双栅氧半导体器件制造方法,该方法包括以下步骤:
在半导体晶片表面上依次通过涂布光刻胶、曝光、显影步骤形成厚栅氧层区域的光刻胶图形;
以厚栅氧层区域的光刻胶图形为掩模、通过离子注入工艺向薄栅氧层区域注入氮原子,形成氮注入层;
去除半导体晶片表面上的光刻胶;
采用热氧化工艺在半导体晶片表面一次性形成厚栅氧层与薄栅氧层。
应用本发明实施例所提供的双栅氧半导体器件制造方法,在通过热氧化工艺在半导体晶片表面形成栅氧层时,由于氮注入层会降低半导体晶片表面的氧化速率,而没有氮注入层的半导体晶片表面的氧化速率正常,因此,通过一次热氧化工艺既可以实现:在有氮注入层的区域的半导体晶片表面形成薄栅氧层,在没有氮注入层的半导体晶片表面形成厚栅氧层。因此,本实施例提供的方案,相对比与现有技术,能够减少一次热氧化制程,所以能够简化工艺流程,降低生产成本较高并提高生产效率。
以上是本申请的核心思想,下面将结合本发明实施例中的附图,对本发明实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例仅仅是本发明一部分实施例,而不是全部的实施例。基于本发明中的实施例,本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例,都属于本发明保护的范围。
在下面的描述中阐述了很多具体细节以便于充分理解本发明,但是本发明还可以采用其他不同于在此描述的其它方式来实施,本领域技术人员可以在不违背本发明内涵的情况下做类似推广,因此本发明不受下面公开的具体实施例的限制。
其次,本发明结合示意图进行详细描述,在详述本发明实施例时,为便于说明,表示器件结构的剖面图会不依一般比例作局部放大,而且所述示意图只是示例,其在此不应限制本发明保护的范围。此外,在实际制作中应包含长度、宽度及深度的三维空间尺寸。
实施例一:
本实施例提供了一种双栅氧半导体器件制造方法,如图1所示,为该方法的一种流程示意图,该方法具体包括以下步骤:
步骤S101,在半导体晶片表面上依次通过涂布光刻胶、曝光、显影步骤形成厚栅氧层区域的光刻胶图形。
参见图2所示,为形成厚栅氧层区域的光刻胶图形后的双栅氧半导体器件结构示意图,其中:201为半导体晶片,204为预设的薄栅氧层区域,205为预设的厚栅氧层区域,202为预设的薄栅氧层区域204和厚栅氧层区域205之间的隔离区,203为厚栅氧层区域205的光刻胶图形。由图2可知,光刻胶层经显影后,薄栅氧层区域204表面上无光刻胶覆盖,厚栅氧层区域205表面上覆盖有光刻胶图形203。本实施例中所述的厚栅氧层区域和薄栅氧层区域均为栅氧层形成之前的区域。
需要说明的是,本实施例中的半导体晶片201可以包括半导体元素,例如单晶、多晶或非晶结构的硅或硅锗(SiGe),也可以包括混合的半导体结构,例如碳化硅、锑化铟、碲化铅、砷化铟、磷化铟、砷化镓或锑化镓、合金半导体或其组合;也可以是绝缘体上硅(SOI)。此外,半导体晶片201还可以包括其它的结构,例如外延层或掩埋层的多层结构。虽然在此描述了可以形成基底的材料的几个示例,但是可以作为半导体晶片的任何材料均落入本发明的精神和范围。
步骤S102,以厚栅氧层区域的光刻胶图形为掩模、通过离子注入工艺向薄栅氧层区域注入氮原子,形成氮注入层。
参见图3所示,为薄栅氧层区域形成氮注入层后的双栅氧半导体器件结构示意图,其中:201为半导体晶片,204为预设的薄栅氧层区域,205为预设的厚栅氧层区域,202为预设的薄栅氧层区域204和厚栅氧层区域205之间的隔离区,203为厚栅氧层区域205的光刻胶图形,206为薄栅氧层区域204中的氮原子注入层。所述氮原子注入层206与薄栅氧层区域204的形状重合。
步骤S103,去除半导体晶片表面上的光刻胶。
本步骤中,去除半导体晶片表面上的光刻胶具体指的是:去除半导体晶片表面上厚栅氧层区域对应的光刻胶图形203。如图4所示,为去除半导体晶片表面上的光刻胶后的双栅氧半导体器件结构示意图,其中:201为半导体晶片,204为预设的薄栅氧层区域,205为预设的厚栅氧层区域,202为预设的薄栅氧层区域204和厚栅氧层区域205之间的隔离区,206为薄栅氧层区域204中的氮原子注入层。
步骤S104,采用热氧化工艺在半导体晶片表面一次性形成厚栅氧层与薄栅氧层。
如图5所示,为形成栅氧层后的双栅氧半导体器件结构示意图,其中:201为半导体晶片,204为预设的薄栅氧层区域,205为预设的厚栅氧层区域,202为预设的薄栅氧层区域204和厚栅氧层区域205之间的隔离区,206为薄栅氧层区域204中的氮原子注入层,207为最终形成的薄栅氧层,208为最终形成的厚栅氧层。
由于薄栅氧层区域204中的氮注入层206会降低半导体晶片201表面的氧化速率,而没有氮注入层的厚栅氧层区域205对应的半导体晶片表面的氧化速率正常,因此,通过一次热氧化制程即可以实现:在有氮注入层的区域的半导体晶片表面形成薄栅氧层,在没有氮注入层的半导体晶片表面形成厚栅氧层。因此,本实施例提供的方案,相对比与现有技术,能够减少一次热氧化制程,所以能够简化工艺流程,降低生产成本较高并提高生产效率。
此外,在越来越小的线宽和越来越薄的栅氧层的要求下,现有工艺难以控制形成的薄栅氧层的厚度。而本发明实施例提供的方法中,可以通过控制氮注入层的氮原子的浓度和厚度,实现控制氮注入层对应的半导体晶片表面的氧化速率,进而控制热氧化工艺中形成的薄栅氧层的厚度,以得到厚度较薄的栅氧层。
实施例二:
本实施例为实施例一的优选实施例,在实施例一提供的方案的基础上,本实施例提供的方案,在形成厚栅氧层区域的光刻胶图形之前,具体的在所述涂布光刻胶之前,还可以包括:
在半导体晶片表面形成氧化硅层。
如图6所示,为形成半导体晶片表面形成氧化硅层后的双栅氧半导体器件结构示意图,其中,201为半导体晶片,209为氧化硅层。本实施例中,所述氧化硅层209可以通过淀积工艺形成。在后续的阱区或氮注入层形成过程中,氧化硅层209可以作为阻挡和保护层,控制离子或原子的注入的深度和浓度,并防止在注入过程中对半导体晶片过度损伤。具体的,所述氧化硅层209的厚度可以为150~300埃。
如图7所示,为包括氧化硅层209的双栅氧半导体器件在形成氮注入层后的结构示意图。同时,在形成氮注入层之后,可以去除所述氧化硅层209。
同时,本实施例提供的方法还可以包括阱区的形成过程,具体的,在形成氧化硅层之后,还可以包括:
进行离子注入,在半导体晶片中形成阱区。
阱区的形成过程具体可以包括:在氧化硅层209表面上依次通过涂布光刻胶、曝光、显影步骤形成阱区的光刻胶图形;以阱区的光刻胶图形为掩模,进行离子注入。
如图8所示,为形成阱区之后的双栅氧半导体器件结构示意图,其中,201为半导体晶片,209为氧化硅层,210为阱区。根据器件导电类型的不同,所述阱区210可以为N阱或P阱。在阱区210的形成过程中,氧化硅层209可以作为阻挡和保护层,控制离子注入的深度和浓度。
实施例三:
在上述实施例一和实施例二提供的方案的基础上,本实施例还优选的提供了在双栅氧半导体器件的薄栅氧层和厚栅氧层之间形成隔离区的方法,所述述隔离区可以为局部场氧化隔离或浅槽隔离。
其中,形成局部场氧化隔离的方法可以为:
在形成所述氧化硅层之后,涂布光刻胶之前,包括:
步骤31:在氧化硅层表面上淀积形成氮化硅层;
如图9所示,为形成氮化硅层之后的双栅氧半导体器件结构示意图,其中211为氮化硅层。氮化硅层211是一层坚固的掩模材料,能够在局部场氧化隔离形成过程中保护半导体晶片的有源区,并可作为抛光制程中的阻挡材质。
步骤32:在氮化硅层中形成局部场氧化隔离区域的图形。
如图10所示,为形成局部场氧化隔离区域图形之后的双栅氧半导体器件结构示意图,其中212为定义的局部场氧化隔离区域图形。
步骤33:以氮化硅层为掩模,进行氧化形成局部场氧化隔离,以划分厚栅氧层区域和薄栅氧层区域。
如图11所示,其中202为形成的局部场氧化隔离区域,202的一侧可设置为厚栅氧层区域,另一侧设置为薄栅氧层区域。由于局部场氧化隔离区域中为绝缘的氧化硅,因此,实现了厚栅氧层区域和薄栅氧层区域的隔离。
步骤34:去除所述氮化硅层。
如图12所示,为应用本实施例的方案最终形成的双栅氧半导体器件结构示意图。
此外,形成浅槽隔离的方法可以为:
在形成所述氧化硅层之后,涂布光刻胶之前,还包括:
步骤41:在氧化硅层表面上淀积形成氮化硅层。
步骤42:在氮化硅层中形成浅槽隔离区域的图形。
步骤43:以氮化硅层为掩模,进行刻蚀工艺形成浅槽隔离,以划分厚栅氧层区域和薄栅氧层区域。
步骤44:采用绝缘材质填充所述浅槽隔离。
步骤45:去除所述氮化硅层。
由于形成浅槽隔离的方法和形成局部场氧化隔离的方法类同,其相似之处可相互参见,不再赘述。浅槽隔离区域比局部场氧化隔离区域占用的面积更小,其隔离效果也更好,因此,非常适用于小尺寸双栅氧半导体器件中。
应用本发明实施例所提供的双栅氧半导体器件制造方法,在通过热氧化工艺在半导体晶片表面形成栅氧层时,由于氮注入层会降低半导体晶片表面的氧化速率,而没有氮注入层的半导体晶片表面氧化速率的氧化速率正常,因此,通过一次热氧化工艺既可以实现:在有氮注入层区域的半导体晶片表面形成薄栅氧层,在没有氮注入层区域的半导体晶片表面形成厚栅氧层。因此,本实施例提供的方案,相对比与现有技术,能够减少一次热氧化制程,所以能够简化工艺流程,降低生产成本较高并提高生产效率。
本说明书中各个部分采用递进的方式描述,每个部分重点说明的都是与其他部分的不同之处,各个部分之间相同相似部分互相参见即可。对所公开的实施例的上述说明,使本领域专业技术人员能够实现或使用本发明。对这些实施例的多种修改对本领域的专业技术人员来说将是显而易见的,本文中所定义的一般原理可以在不脱离本发明的精神或范围的情况下,在其它实施例中实现。因此,本发明将不会被限制于本文所示的实施例,而是要符合与本文所公开的原理和新颖特点相一致的最宽的范围。
Claims (7)
1.一种双栅氧半导体器件制造方法,其特征在于,包括:
在半导体晶片表面上依次通过涂布光刻胶、曝光、显影步骤形成厚栅氧层区域的光刻胶图形;
以厚栅氧层区域的光刻胶图形为掩模、通过离子注入工艺向薄栅氧层区域注入氮原子,形成氮注入层;
去除半导体晶片表面上的光刻胶;
采用热氧化工艺在半导体晶片表面一次性形成所述厚栅氧层与薄栅氧层。
2.根据权利要求1所述的方法,其特征在于:
在所述涂布光刻胶之前,还包括:
在半导体晶片表面形成氧化硅层;
在形成栅氧层之前,向薄栅氧层区域注入氮原子之后,还包括:
去除所述氧化硅层。
3.根据权利要求2所述的方法,其特征在于:
所述氧化硅层通过淀积工艺形成。
4.根据权利要求2或3所述的方法,其特征在于:
所述氧化硅层的厚度为150~300埃。
5.根据权利要求2所述的方法,其特征在于,在形成所述氧化硅层之后,还包括:
通过离子注入工艺在半导体晶片中形成阱区。
6.根据权利要求2所述的方法,其特征在于,在形成所述氧化硅层之后,涂布光刻胶之前,还包括:
在氧化硅层表面上淀积形成氮化硅层;
在氮化硅层中刻蚀形成局部场氧化隔离区域的图形;
以氮化硅层为掩模,通过氧化工艺形成局部场氧化隔离,以划分厚栅氧层区域和薄栅氧层区域;
去除所述氮化硅层。
7.根据权利要求2所述的方法,其特征在于,在形成所述氧化硅层之后,涂布光刻胶之前,还包括:
在氧化硅层表面上淀积形成氮化硅层;
在氮化硅层中形成浅槽隔离区域的图形;
以氮化硅层为掩模,通过刻蚀工艺形成浅槽隔离,以划分厚栅氧层区域和薄栅氧层区域;
采用绝缘材质填充所述浅槽隔离;
去除所述氮化硅层。
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CN108878278A (zh) * | 2018-06-29 | 2018-11-23 | 上海华虹宏力半导体制造有限公司 | 栅氧化层的制造方法 |
CN113257739A (zh) * | 2021-04-29 | 2021-08-13 | 长江存储科技有限责任公司 | 半导体器件的制备方法、半导体器件及存储装置 |
WO2023123762A1 (zh) * | 2021-12-28 | 2023-07-06 | 长鑫存储技术有限公司 | 一种半导体结构及其形成方法 |
US11862461B2 (en) | 2021-12-28 | 2024-01-02 | Changxin Memory Technologies, Inc. | Method of forming oxide layer on a doped substrate using nitridation and oxidation process |
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CN1479350A (zh) * | 2002-08-27 | 2004-03-03 | 上海宏力半导体制造有限公司 | 形成不同厚度的双栅极绝缘层的方法 |
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CN105097917A (zh) * | 2014-05-05 | 2015-11-25 | 中芯国际集成电路制造(上海)有限公司 | Ldmos器件及其制作方法 |
CN107479341A (zh) * | 2017-09-13 | 2017-12-15 | 武汉新芯集成电路制造有限公司 | 一种减少刻蚀阻挡层残留的显影方法 |
CN108878278A (zh) * | 2018-06-29 | 2018-11-23 | 上海华虹宏力半导体制造有限公司 | 栅氧化层的制造方法 |
CN108878278B (zh) * | 2018-06-29 | 2020-09-29 | 上海华虹宏力半导体制造有限公司 | 栅氧化层的制造方法 |
CN113257739A (zh) * | 2021-04-29 | 2021-08-13 | 长江存储科技有限责任公司 | 半导体器件的制备方法、半导体器件及存储装置 |
WO2023123762A1 (zh) * | 2021-12-28 | 2023-07-06 | 长鑫存储技术有限公司 | 一种半导体结构及其形成方法 |
US11862461B2 (en) | 2021-12-28 | 2024-01-02 | Changxin Memory Technologies, Inc. | Method of forming oxide layer on a doped substrate using nitridation and oxidation process |
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