CN102479702A - Method for manufacturing thin film transistor array panel - Google Patents
Method for manufacturing thin film transistor array panel Download PDFInfo
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- CN102479702A CN102479702A CN2011102141068A CN201110214106A CN102479702A CN 102479702 A CN102479702 A CN 102479702A CN 2011102141068 A CN2011102141068 A CN 2011102141068A CN 201110214106 A CN201110214106 A CN 201110214106A CN 102479702 A CN102479702 A CN 102479702A
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- 238000000034 method Methods 0.000 title claims abstract description 55
- 239000010409 thin film Substances 0.000 title claims abstract description 28
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 11
- 229910052751 metal Inorganic materials 0.000 claims abstract description 98
- 239000002184 metal Substances 0.000 claims abstract description 98
- 239000010408 film Substances 0.000 claims abstract description 70
- 238000005530 etching Methods 0.000 claims abstract description 37
- 238000002161 passivation Methods 0.000 claims abstract description 14
- 238000004380 ashing Methods 0.000 claims abstract description 7
- 239000004065 semiconductor Substances 0.000 claims description 35
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 34
- 238000009413 insulation Methods 0.000 claims description 15
- 239000010949 copper Substances 0.000 claims description 8
- 238000001312 dry etching Methods 0.000 claims description 8
- 239000000758 substrate Substances 0.000 claims description 8
- 239000010936 titanium Substances 0.000 claims description 8
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 5
- 229910000881 Cu alloy Inorganic materials 0.000 claims description 5
- 229910001069 Ti alloy Inorganic materials 0.000 claims description 5
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 5
- 229910052802 copper Inorganic materials 0.000 claims description 5
- 229910052719 titanium Inorganic materials 0.000 claims description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract 5
- 229910052710 silicon Inorganic materials 0.000 abstract 5
- 239000010703 silicon Substances 0.000 abstract 5
- 238000000635 electron micrograph Methods 0.000 description 4
- 230000005540 biological transmission Effects 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- ROOXNKNUYICQNP-UHFFFAOYSA-N ammonium persulfate Chemical compound [NH4+].[NH4+].[O-]S(=O)(=O)OOS([O-])(=O)=O ROOXNKNUYICQNP-UHFFFAOYSA-N 0.000 description 2
- 230000003628 erosive effect Effects 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- -1 nitric acid) of 2wt% Chemical class 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- QTBSBXVTEAMEQO-UHFFFAOYSA-M Acetate Chemical compound CC([O-])=O QTBSBXVTEAMEQO-UHFFFAOYSA-M 0.000 description 1
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 1
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 229910001870 ammonium persulfate Inorganic materials 0.000 description 1
- 239000007864 aqueous solution Substances 0.000 description 1
- 235000008429 bread Nutrition 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 150000007522 mineralic acids Chemical class 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- 150000007524 organic acids Chemical class 0.000 description 1
- 229920003023 plastic Polymers 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- H01—ELECTRIC ELEMENTS
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
- H01L29/456—Ohmic electrodes on silicon
- H01L29/458—Ohmic electrodes on silicon for thin film silicon, e.g. source or drain electrode
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- Mathematical Physics (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
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- Ceramic Engineering (AREA)
- Thin Film Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
- Liquid Crystal (AREA)
Abstract
A method for manufacturing a thin film transistor array panel, includes: sequentially forming a first silicon layer, a second silicon layer, a lower metal layer, and an upper metal layer on a gate insulating layer and a gate line; forming a first film pattern on the upper metal layer; forming a first lower metal pattern and a first upper metal pattern that includes a protrusion, by etching the upper metal layer and the lower metal layer; forming first and second silicon patterns by etching the first and second silicon layers; forming a second film pattern by ashing the first film pattern; forming a second upper metal pattern by etching the first upper metal pattern; forming a data line and a thin film transistor by etching the first lower metal pattern and the first and second silicon patterns; and forming a passivation layer and a pixel electrode on the resultant.
Description
Technical field
Aspect of the present invention relates to the thin-film transistor display panel manufacturing approach.
Background technology
Usually, thin-film transistor (TFT) arraying bread board is as the circuit board that is used for each pixel of drive in LCD, organic electroluminescent (EL) display unit etc.Thin-film transistor display panel comprise the gate line that transmits sweep signal or scan signal line, images signal data wire or image signal line, be connected to gate line and data wire thin-film transistor, be connected to the pixel electrode of thin-film transistor etc.
Thin-film transistor be included as the part of gate line gate electrode, comprise the semiconductor layer of raceway groove and be the source electrode and the drain electrode of the part of data wire.Thin-film transistor is for transmitting according to the sweep signal via the gate line transmission or interrupting via the switch element of data wire to pixel electrode image transmitted signal.
When forming thin-film transistor display panel,, use a mask to form data wire and semiconductor layer in order to reduce the number of times of mask process.That is the sidewall coplane of the sidewall of data wire and semiconductor layer.Yet, when etching data metal layer (data metal layer), owing to tilt to increase, so the sidewall of semiconductor layer comprises the protuberance that the sidewall of crossing data metal layer extends.
The above-mentioned information that in this background technology part, discloses only is used to strengthen the understanding to background of the present invention, therefore, may comprise the information that does not constitute prior art.
Summary of the invention
Be devoted to when making thin-film transistor display panel to minimize the protuberance of the sidewall of semiconductor layer, made the present invention with respect to the sidewall of data wire.
Other characteristics of the present invention will be set forth in the following description, and partly obvious from describe, and perhaps can from working of an invention, know.
Illustrative embodiments of the present invention provides a kind of thin-film transistor display panel manufacturing approach, and this method comprises: on insulated substrate, form the gate line that comprises gate electrode; On gate line, form gate insulation layer; Order forms first amorphous silicon layer, second amorphous silicon layer, following data metal layer and last data metal layer on gate insulation layer; On last data metal layer, form the first photosensitive film pattern, this first photosensitive film pattern comprises first and the second portion thicker than first; Use the first photosensitive film pattern as mask, form data metal pattern on first time data metal pattern and first through data metal layer in the etching and following data metal layer, this on first the data metal pattern comprise the protuberance of giving prominence to from its edge; Use the first photosensitive film pattern as mask, form the first amorphous silicon layer pattern and the second amorphous silicon layer pattern through etching first amorphous silicon layer and second amorphous silicon layer; Form the second photosensitive film pattern through the ashing first photosensitive film pattern; Through using the second photosensitive film pattern to form data metal pattern on second as data metal pattern on the mask etching first; Use the second photosensitive film pattern as mask, form data wire and comprise the thin-film transistor of drain electrode, semiconductor, ohmic contact layer and source electrode through first time data metal pattern of etching, the first amorphous silicon layer pattern and the second amorphous silicon layer pattern; On data wire, drain electrode and gate insulation layer, form passivation layer; And on passivation layer, form pixel electrode, make pixel electrode be connected to drain electrode.Data metal pattern and first time data metal pattern can undercutting (undercut, lateral erosion) the first photosensitive film patterns on first.
According to an illustrative embodiment of the invention, can minimize the protuberance of the sidewall of semiconductor layer with respect to the sidewall of data wire.
Should be understood that above-mentioned general description and following detailed description are exemplary with illustrative, and be intended to further explanation is provided desired the present invention.
Description of drawings
Accompanying drawing is incorporated in the application documents and constitutes the part of application documents, comprises this accompanying drawing the present invention is provided further understanding, and this accompanying drawing shows execution mode of the present invention, and is used for explaining principle of the present invention with specification.
Fig. 1 is the layout according to the thin-film transistor display panel of exemplary embodiment of the invention.
Fig. 2 is the sectional view along the line II-II of Fig. 1.
Fig. 3, Fig. 4, Fig. 5, Fig. 6, Fig. 7, Fig. 8, Fig. 9, Figure 10 and Figure 11 are that order illustrates the sectional view according to the manufacturing approach of the thin-film transistor display panel of exemplary embodiment of the invention.
Figure 12 (a) is the electron micrograph according to the sidewall protuberance of the semiconductor layer of prior art, and Figure 12 (b) is the electron micrograph according to the sidewall protuberance of the semiconductor layer of exemplary embodiment of the invention.
Figure 13, Figure 14, Figure 15, Figure 16, Figure 17 and Figure 18 are that order illustrates the diagrammatic sketch according to the manufacturing approach of the thin-film transistor display panel of another illustrative embodiments of the present invention.
Embodiment
Hereinafter, will the present invention be described in more detail with reference to accompanying drawing, the illustrative embodiments of invention shown in the drawings.Those skilled in the art can understand, and can make amendment to described execution mode with various mode, and this does not all break away from the spirit or scope of the present invention.
In the drawings, for clarity sake, the thickness in layer, film, panel, zone etc. is exaggerated.In application documents full text, identical reference number is represented identical parts.Should be understood that when element or layer be known as " " another element or layer " on " perhaps " be connected to " another element or when layer, can be directly on other elements or layer or be connected directly to other elements or layer, perhaps can exist and insert element or layer.On the contrary, when element or layer be known as " directly existing " another element or layer " on " or " being connected directly to " another element or when layer, do not exist and insert element or layer.
Fig. 1 is the layout that illustrates according to the thin-film transistor display panel of exemplary embodiment of the invention.Fig. 2 is the sectional view along the line II-II of Fig. 1.See figures.1.and.2, for example, comprise that many gate lines 121 of gate electrode 124 are formed on the substrate of being processed by insulating material (such as glass or plastics) 110.Order forms gate insulation layer 140, a plurality of semiconductor layer 154, a plurality of ohmic contact 163 and 165, many data wires 171 and a plurality of drain electrode 175 above that.
Here, the sidewall of semiconductor layer 154 is outstanding with respect to the sidewall of data wire 171 and drain electrode 175.The protuberance of the sidewall of semiconductor layer 154 is about 0.8 μ m, and this is less than the protuberance scope of 1.0 μ m to 1.2 μ m of the prior art.
For example, the passivation layer of being processed by silicon nitride and silica 180 is formed on data wire 171 and the drain electrode 175.The contact hole 185 that exposes drain electrode 175 is formed on the passivation layer 180.Pixel electrode 191 is formed on the passivation layer 180, and is connected to drain electrode 175 via contact hole 185.
Fig. 3 to Figure 11 is that order illustrates the sectional view according to the thin-film transistor display panel manufacturing approach of exemplary embodiment of the invention.As shown in Figure 3, on transparent insulation substrate 110, form and comprise after the gate line 121 of gate electrode 124, on insulated substrate 110 and gate electrode 124, form gate insulation layer 140.
As shown in Figure 4, sequence stack amorphous silicon layer 150, the amorphous silicon layer 160 that is mixed with impurity and data metal layer 170 on gate insulation layer 140.Data metal layer 170 for example comprises lower metal layer 170p that is formed by titanium (Ti) or titanium alloy and the last metal level 170r that is for example formed by copper (Cu) or copper alloy.
On data metal layer 170, form the first photosensitive film pattern 50.The first photosensitive film pattern 50 comprises 50a of first and the second portion 50b with different-thickness.Through applying the photosensitive film (not shown), use half-tone mask this film is made public, and the film after making public developed form the first photosensitive film pattern 50 with transparent region, semi-transparent semi-reflecting (trans-reflective) zone and zone of opacity.Can use semi-transparent semi-reflecting layer or slit pattern to form the semi-transparent semi-reflecting zone of half-tone mask.
As shown in Figure 5, carry out first wet etch process, use the first photosensitive film pattern 50 to come etching data metal layer 170 as mask.Data metal layer 170 after the etching has formed the undercutting (lateral erosion) that is positioned under the first photosensitive film pattern 50.In this case, the sidewall of last metal level 170r is outstanding, and the edge of lower metal layer 170p is positioned at the inboard of the sidewall of metal level 170r.In order to form this shape, in first wet etch process, use the ammonium persulfate ((NH that for example comprises 12wt%
4)
2S
2O
8), the inorganic acid (such as nitric acid) of 2wt%, the organic acid (such as acetate) of 1wt%, the hydrogen fluoride (HF) of 1wt%, the fluoboric acid (HBF of 0.7wt%
4) the aqueous solution.
As shown in Figure 6, the sidewall of last metal level 170r (edge) comprises the protuberance with upper surface, and this upper surface is in the angle A in about 30 degree to the scope of about 50 degree.The lower surface of this protuberance is in the angle B in about 30 degree to the scope of about 50 degree.In addition, the angle C between the lower surface of the line of the inside part of the lower surface of the inside part of the upper surface of connection protuberance and protuberance and last metal level 170r is about 90 degree.
As shown in Figure 7, carry out first dry etching and handle, use the first photosensitive film pattern 50 to come etching method for amorphous silicon layer 150 and amorphous silicon layer 160 as mask.
As shown in Figure 8, make a part and the second portion 50b of the 50a of first be removed through ashing (ashing) the first photosensitive film pattern 50 and form the second photosensitive film pattern 51.The second photosensitive film pattern 51 exposes goes up metal level and the corresponding part of the raceway groove thin-film transistor that forms subsequently.In this case, the sidewall of the second photosensitive film pattern 51 just in time is positioned at the sidewall top of lower metal layer 170p basically, makes the sidewall of the second photosensitive film pattern 51 be positioned at the inboard of the protuberance of metal level 170r.In other words, the circumference of lower metal layer 170p can be just in time corresponding to the circumference of the second photosensitive film pattern 51.
As shown in Figure 9, use the second photosensitive film pattern 51 to carry out second wet etch process with metal level 170r in the etching as mask.In this case, the part of the raceway groove top that is positioned at the thin-film transistor that forms subsequently of last metal level 170r is removed.In addition, the protuberance of last metal level 170r is etched, and makes that going up metal level has from the intilted sidewall of the upper surface of lower metal layer 170p.
Shown in figure 10, use the second photosensitive film pattern 51 as mask, handle data wire 171, drain electrode 175 and ohmic contact layer 163 and 165 that form semiconductor layer 154, comprise source electrode 173 through carrying out second dry etching.The processing of second dry etching comes etching lower metal layer 170p, doped amorphous silicon layer 160, amorphous silicon layer 150 through the hierarchic structure that the sidewall that makes semiconductor layer 154 has outwards outstanding about 0.8 μ m (less than the protuberance of 1.0 μ m to 1.2 μ m shown in the prior art).
Shown in figure 11, after removing the second photosensitive film pattern 51, on data wire 171, drain electrode 175 and gate insulation layer 140, form passivation layer 180.Of Fig. 2, after forming contact hole 185, on passivation layer 180, form pixel electrode 191.
Figure 12 A is the electron micrograph according to the sidewall ledge (protuberance) of the semiconductor layer of prior art, and Figure 12 B is the electron micrograph according to the sidewall ledge (protuberance) of the semiconductor layer of exemplary embodiment of the invention.
Table 1 has compared the size and the etching period of the protuberance of prior art and this illustrative embodiments.
(table 1)
| Etching period (second) | Protuberance (μ m) | |
| (a) | 146.8 | 1.01 |
| (b) | (122.3 improving 17%) | (0.83 improving 18%) |
Shown in Figure 12 and table 1, the outwards outstanding 0.83 μ m of the protuberance of illustrative embodiments, these 1.01 μ m than the protuberance shown in the prior art are little by 18%.In addition, the etching period of this illustrative embodiments lacks 17% than prior art.
Figure 13 to Figure 18 illustrates the manufacturing approach according to the thin-film transistor display panel of another illustrative embodiments of the present invention for order.Shown in figure 13, on transparent insulation substrate 110, form and comprise after the gate line 121 of gate electrode 124, on insulated substrate 110 and gate line 121, form gate insulation layer 140.Order forms amorphous silicon layer 150, is mixed with the amorphous silicon layer 160 and the data metal layer 170 of impurity on gate insulation layer 140.Here, data metal layer 170 comprises lower metal layer 170p that is formed by titanium (Ti) or titanium alloy and the last metal level 170r that is formed by copper (Cu) or copper alloy.
On data metal layer 170, form and comprise 50a of first with different-thickness and the first photosensitive film pattern 50 of second portion 50b.Form the first photosensitive film pattern 50 in the above described manner.
Use the first photosensitive film pattern 50 as mask, carry out first wet etch process and come etching data metal layer 170.Etching to data metal level 170 has formed the undercutting under the edge that is positioned at the first photosensitive film pattern 50.Particularly, the edge of lower metal layer 170p and last metal level 170r is gradually sharp, and lower metal layer 170p is more than last metal level 170r etching, thus the edge of metal level 170r in the lower metal layer 170p undercutting.
For lower metal layer 170p and last metal level 170r, the etching solution of first wet etch process has different etching selectivities.That is, etching solution is with the speed etching lower metal layer 170p higher than last metal level 170r.
Shown in figure 14, use the first photosensitive film pattern 50 as mask, carry out first dry etching and handle etching method for amorphous silicon layer 150 and doped amorphous silicon layer 160.
Shown in figure 15, make the edge of the 50a of first be etched and second portion 50b is removed and forms the second photosensitive film pattern 51 through the ashing first photosensitive film pattern 50.The second photosensitive film pattern 51 exposes goes up metal level and the corresponding part of the raceway groove thin-film transistor that forms subsequently.In this case, the edge of the second photosensitive film pattern 51 is corresponding to the circumference of lower metal layer 170p.In other words, the sidewall of the second photosensitive film pattern 51 can just in time be positioned at the outward flange top of lower metal layer 170p.
Shown in figure 16, use the second photosensitive film pattern 51 as mask, carry out second wet etch process and come metal level 170r in the etching.Like Figure 17 and shown in Figure 180, use the second photosensitive film pattern 51 as mask, carry out second dry etching and handle etching lower metal layer 170p, doped amorphous silicon layer 160, amorphous silicon layer 150.In this case, the edge of doped amorphous silicon layer 160 and amorphous silicon layer 150 is by etching together.As a result, the circumference at amorphous silicon layer 150 forms the stairstepping protuberance.
Thereafter, use the second photosensitive film pattern 51 as mask, etching doped amorphous silicon layer 160 is to expose the part of amorphous silicon layer 150.As a result, the data wire 171 that comprises source electrode 173, drain electrode 175, ohmic contact layer 163 and 165 and semiconductor layer 154 have been formed.
As shown in Figure 2, after removing the second photosensitive film pattern 51, on data wire 171, drain electrode 175 and gate insulation layer 140, form passivation layer 180.In addition, after forming contact hole 185, on passivation layer 180, form pixel electrode 191.
It will be apparent for a person skilled in the art that the present invention can carry out various distortion and modification and do not break away from the spirit and scope of the present invention.Therefore, the present invention is intended to contain various distortion of the present invention and modification, as long as they are in the scope of accompanying claims and equivalent thereof.
Claims (21)
1. thin-film transistor display panel manufacturing approach comprises:
On insulated substrate, form gate line, said gate line comprises gate electrode;
On said gate line, form gate insulation layer;
Order forms first amorphous silicon layer, second amorphous silicon layer, following data metal layer and last data metal layer on said gate insulation layer;
Form the first photosensitive film pattern on said on the data metal layer, the said first photosensitive film pattern comprises first and the second portion thicker than said first;
Carry out first etch processes through using the said first photosensitive film pattern as said upward data metal layer of mask etching and said data metal layer down; Forming data metal pattern on first time data metal pattern and first, the data metal pattern comprises the outward extending protuberance that is positioned at its circumference on said first;
Through using the said first photosensitive film pattern to carry out second etch processes, to form the first amorphous silicon layer pattern and the second amorphous silicon layer pattern as said first amorphous silicon layer of mask etching and said second amorphous silicon layer;
The said first photosensitive film pattern of ashing is to form the second photosensitive film pattern;
Through using the said second photosensitive film pattern to carry out the 3rd etch processes, to form data metal pattern on second as data metal pattern on the mask etching said first;
Through using the said second photosensitive film pattern to carry out the 4th etch processes, with source electrode, drain electrode, semiconductor and the ohmic contact layer between said source electrode and said drain electrode and said semiconductor that forms data wire, extends from said data wire as the said first time data metal pattern of mask etching, the said first amorphous silicon layer pattern and the said second amorphous silicon layer pattern;
On said data wire, said drain electrode and said gate insulation layer, form passivation layer; And
On said passivation layer, form pixel electrode, make said pixel electrode be connected to said drain electrode.
2. method according to claim 1, wherein, it is inboard that the circumference of data metal pattern and said first time data metal pattern is positioned at the circumference of the said first photosensitive film pattern on said first, thus the said first photosensitive film pattern of undercutting.
3. method according to claim 2, wherein, the said protuberance of data metal pattern extends the circumference of the said second photosensitive film pattern on said first.
4. method according to claim 3, wherein, the said protuberance of data metal pattern has upper surface and opposing lower surface on said first.
5. method according to claim 4, wherein, the said lower surface of said protuberance extends to the circumference of said first time data metal pattern from the edge of said upper surface.
6. method according to claim 5, wherein:
The said data metal layer that goes up comprises copper or copper alloy; And
Said data metal layer down comprises titanium or titanium alloy.
7. method according to claim 6, wherein:
Said first etch processes and said the 3rd etch processes comprise wet etch process; And
Said second etch processes and said the 4th etch processes comprise the dry etching processing.
8. method according to claim 7, wherein, the edge of the lower surface of the said protuberance of data metal pattern just in time is positioned at the circumference below of the said second photosensitive film pattern on said first.
9. method according to claim 1, wherein:
The said data metal layer that goes up comprises copper or copper alloy; And
Said data metal layer down comprises titanium or titanium alloy.
10. method according to claim 9, wherein:
Said first etch processes and said the 3rd etch processes comprise wet etch process; And
Said second etch processes and said the 4th etch processes comprise the dry etching processing.
11. method according to claim 10, wherein, the edge of the lower surface of the said protuberance of data metal pattern just in time is positioned at the circumference below of the said second photosensitive film pattern on said first.
12. method according to claim 1, wherein:
Said first etch processes and said the 3rd etch processes comprise wet etch process; And
Said second etch processes and said the 4th etch processes comprise the dry etching processing.
13. method according to claim 12, wherein, the said protuberance of data metal pattern extends the circumference of the said second photosensitive film pattern on said first.
14. method according to claim 1, wherein, the said protuberance of data metal pattern comprises upper surface and opposing lower surface on said first.
15. method according to claim 14, wherein, the said lower surface of the said protuberance of data metal pattern contacts the circumference of said first time data metal pattern on said first.
16. method according to claim 1, wherein, the outer rim of said first time data metal pattern is gradually sharp, and is positioned at the inboard of the said protuberance of data metal pattern on said first.
17. a thin-film transistor display panel manufacturing approach comprises:
Order forms first semiconductor layer, second semiconductor layer, lower conductiving layer and last conductive layer on substrate;
Form the first photosensitive film pattern on said on the conductive layer, the said first photosensitive film pattern comprises first and the second portion thicker than said first;
Carry out first etch processes through using the said first photosensitive film pattern as said upward conductive layer of mask etching and said lower conductiving layer; Forming conductive pattern on first time conductive pattern and first, conductive pattern comprises the outward extending protuberance at the circumference place that is positioned at conductive pattern on said first on said first;
Through using the said first photosensitive film pattern to carry out second etch processes, to form first semiconductor layer pattern and second semiconductor layer pattern as said first semiconductor layer of mask etching and said second semiconductor layer;
Form the second photosensitive film pattern from the said first photosensitive film pattern;
Through using the said second photosensitive film pattern to carry out the 3rd etch processes, to form conductive pattern on second as conductive pattern on the mask etching said first; And
Carry out the 4th etch processes through using the said second photosensitive film pattern as the said first time conductive pattern of mask etching, said first semiconductor layer pattern and said second semiconductor layer pattern.
18. method according to claim 17; Wherein, said the 4th etch processes source electrode, drain electrode, semiconductor and the ohmic contact layer between said source electrode and said drain electrode and said semiconductor that form data wire, extend from said data wire.
19. method according to claim 18 further comprises:
On said data wire and said drain electrode, form passivation layer; And
On said passivation layer, form pixel electrode, make said pixel electrode be connected to said drain electrode.
20. method according to claim 17, wherein, said first semiconductor layer and said second semiconductor layer include amorphous silicon.
21. method according to claim 17 wherein, forms the said second photosensitive film pattern from the said first photosensitive film pattern and comprises the said first photosensitive film pattern of ashing.
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| KR10-2010-0119744 | 2010-11-29 | ||
| KR1020100119744A KR101750430B1 (en) | 2010-11-29 | 2010-11-29 | Method for manufacturing thin film transistor substrate |
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| CN102479702A true CN102479702A (en) | 2012-05-30 |
| CN102479702B CN102479702B (en) | 2016-03-02 |
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| US (1) | US8557621B2 (en) |
| JP (1) | JP5788259B2 (en) |
| KR (1) | KR101750430B1 (en) |
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| WO2021128462A1 (en) * | 2019-12-26 | 2021-07-01 | Tcl华星光电技术有限公司 | Tft array substrate and manufacturing method therefor |
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| CN103730413B (en) * | 2013-12-31 | 2016-08-17 | 合肥京东方光电科技有限公司 | The preparation method of a kind of array base palte and array base palte, display device |
| KR102070148B1 (en) * | 2018-10-24 | 2020-01-29 | 삼성디스플레이 주식회사 | Display device and method of manufacturing the same |
| KR102596354B1 (en) * | 2018-11-05 | 2023-10-31 | 삼성디스플레이 주식회사 | Liquid crystal display and the method therrof |
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Also Published As
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| CN102479702B (en) | 2016-03-02 |
| KR101750430B1 (en) | 2017-06-26 |
| US8557621B2 (en) | 2013-10-15 |
| KR20120058109A (en) | 2012-06-07 |
| JP5788259B2 (en) | 2015-09-30 |
| US20120135555A1 (en) | 2012-05-31 |
| JP2012119659A (en) | 2012-06-21 |
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